diff --git a/arch/arm/include/at32/at32f43xxx_irq.h b/arch/arm/include/at32/at32f43xxx_irq.h index aadf5c38e5d..f5079c90445 100644 --- a/arch/arm/include/at32/at32f43xxx_irq.h +++ b/arch/arm/include/at32/at32f43xxx_irq.h @@ -115,7 +115,7 @@ #define AT32_IRQ_DMA1CH2 (AT32_IRQ_FIRST+57) /* 57: DMA1 Stream 2 global interrupt */ #define AT32_IRQ_DMA1CH3 (AT32_IRQ_FIRST+58) /* 58: DMA1 Stream 3 global interrupt */ #define AT32_IRQ_DMA1CH4 (AT32_IRQ_FIRST+59) /* 59: DMA1 Stream 4 global interrupt */ -#define AT32_IRQ_DMA1CH5 (AT32_IRQ_FIRST+60) /* 60: DMA1 Stream 5 global interrupt */ +#define AT32_IRQ_DMA1CH5 (AT32_IRQ_FIRST+60) /* 60: DMA1 Stream 5 global interrupt */ #if defined(CONFIG_AT32_AT32F437) # define AT32_IRQ_ETH (AT32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ # define AT32_IRQ_ETHWKUP (AT32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ diff --git a/arch/arm/src/at32/hardware/at32_can.h b/arch/arm/src/at32/hardware/at32_can.h index b70037dc1c9..7785812fb1a 100644 --- a/arch/arm/src/at32/hardware/at32_can.h +++ b/arch/arm/src/at32/hardware/at32_can.h @@ -136,40 +136,40 @@ # define AT32_CAN1_INTEN (AT32_CAN1_BASE+AT32_CAN_INTEN_OFFSET) # define AT32_CAN1_ESTS (AT32_CAN1_BASE+AT32_CAN_ESTS_OFFSET) # define AT32_CAN1_BTMG (AT32_CAN1_BASE+AT32_CAN_BTMG_OFFSET) -# define AT32_CAN1_TMI(x) (AT32_CAN1_BASE+AT32_CAN_TMI_OFFSET(x)) -# define AT32_CAN1_TMI0 (AT32_CAN1_BASE+AT32_CAN_TMI0_FFSET) -# define AT32_CAN1_TMI1 (AT32_CAN1_BASE+AT32_CAN_TMI1_FFSET) -# define AT32_CAN1_TMI2 (AT32_CAN1_BASE+AT32_CAN_TMI2_FFSET) -# define AT32_CAN1_TMC(x) (AT32_CAN1_BASE+AT32_CAN_TMC_OFFSET(x)) -# define AT32_CAN1_TMC0 (AT32_CAN1_BASE+AT32_CAN_TMC0_OFFSET) -# define AT32_CAN1_TMC1 (AT32_CAN1_BASE+AT32_CAN_TMC1_OFFSET) -# define AT32_CAN1_TMC2 (AT32_CAN1_BASE+AT32_CAN_TMC2_OFFSET) -# define AT32_CAN1_TMDTL(x) (AT32_CAN1_BASE+AT32_CAN_TMDTL_OFFSET(x)) -# define AT32_CAN1_TMDTL0 (AT32_CAN1_BASE+AT32_CAN_TMDTL0_OFFSET) -# define AT32_CAN1_TMDTL1 (AT32_CAN1_BASE+AT32_CAN_TMDTL1_OFFSET) -# define AT32_CAN1_TMDTL2 (AT32_CAN1_BASE+AT32_CAN_TMDTL2_OFFSET) -# define AT32_CAN1_TMDTH(x) (AT32_CAN1_BASE+AT32_CAN_TMDTH_OFFSET(x)) -# define AT32_CAN1_TMDTH0 (AT32_CAN1_BASE+AT32_CAN_TMDTH0_OFFSET) -# define AT32_CAN1_TMDTH1 (AT32_CAN1_BASE+AT32_CAN_TMDTH1_OFFSET) -# define AT32_CAN1_TMDTH2 (AT32_CAN1_BASE+AT32_CAN_TMDTH2_OFFSET) -# define AT32_CAN1_RFI(x) (AT32_CAN1_BASE+AT32_CAN_RFI_OFFSET(x)) -# define AT32_CAN1_RFI0 (AT32_CAN1_BASE+AT32_CAN_RFI0_OFFSET) -# define AT32_CAN1_RFI1 (AT32_CAN1_BASE+AT32_CAN_RFI1_OFFSET) -# define AT32_CAN1_RFC(x) (AT32_CAN1_BASE+AT32_CAN_RFC_OFFSET(x)) -# define AT32_CAN1_RFC0 (AT32_CAN1_BASE+AT32_CAN_RFC0_OFFSET) -# define AT32_CAN1_RFC1 (AT32_CAN1_BASE+AT32_CAN_RFC1_OFFSET) -# define AT32_CAN1_RFDTL(x) (AT32_CAN1_BASE+AT32_CAN_RFDTL_OFFSET(x)) -# define AT32_CAN1_RFDTL0 (AT32_CAN1_BASE+AT32_CAN_RFDTL0_OFFSET) -# define AT32_CAN1_RFDTL1 (AT32_CAN1_BASE+AT32_CAN_RFDTL1_OFFSET) -# define AT32_CAN1_RFDTH(x) (AT32_CAN1_BASE+AT32_CAN_RFDTH_OFFSET(x)) -# define AT32_CAN1_RFDTH0 (AT32_CAN1_BASE+AT32_CAN_RFDTH0_OFFSET) -# define AT32_CAN1_RFDTH1 (AT32_CAN1_BASE+AT32_CAN_RFDTH1_OFFSET) -# define AT32_CAN1_FCTRL (AT32_CAN1_BASE+AT32_CAN_FCTRL_OFFSET) -# define AT32_CAN1_FMCFG (AT32_CAN1_BASE+AT32_CAN_FMCFG_OFFSET) -# define AT32_CAN1_FSCFG (AT32_CAN1_BASE+AT32_CAN_FSCFG_OFFSET) -# define AT32_CAN1_FRF (AT32_CAN1_BASE+AT32_CAN_FRF_OFFSET) -# define AT32_CAN1_FACFG (AT32_CAN1_BASE+AT32_CAN_FACFG_OFFSET) -# define AT32_CAN1_FIR(b,i) (AT32_CAN1_BASE+AT32_CAN_FIR_OFFSET(b,i)) +# define AT32_CAN1_TMI(x) (AT32_CAN1_BASE+AT32_CAN_TMI_OFFSET(x)) +# define AT32_CAN1_TMI0 (AT32_CAN1_BASE+AT32_CAN_TMI0_FFSET) +# define AT32_CAN1_TMI1 (AT32_CAN1_BASE+AT32_CAN_TMI1_FFSET) +# define AT32_CAN1_TMI2 (AT32_CAN1_BASE+AT32_CAN_TMI2_FFSET) +# define AT32_CAN1_TMC(x) (AT32_CAN1_BASE+AT32_CAN_TMC_OFFSET(x)) +# define AT32_CAN1_TMC0 (AT32_CAN1_BASE+AT32_CAN_TMC0_OFFSET) +# define AT32_CAN1_TMC1 (AT32_CAN1_BASE+AT32_CAN_TMC1_OFFSET) +# define AT32_CAN1_TMC2 (AT32_CAN1_BASE+AT32_CAN_TMC2_OFFSET) +# define AT32_CAN1_TMDTL(x) (AT32_CAN1_BASE+AT32_CAN_TMDTL_OFFSET(x)) +# define AT32_CAN1_TMDTL0 (AT32_CAN1_BASE+AT32_CAN_TMDTL0_OFFSET) +# define AT32_CAN1_TMDTL1 (AT32_CAN1_BASE+AT32_CAN_TMDTL1_OFFSET) +# define AT32_CAN1_TMDTL2 (AT32_CAN1_BASE+AT32_CAN_TMDTL2_OFFSET) +# define AT32_CAN1_TMDTH(x) (AT32_CAN1_BASE+AT32_CAN_TMDTH_OFFSET(x)) +# define AT32_CAN1_TMDTH0 (AT32_CAN1_BASE+AT32_CAN_TMDTH0_OFFSET) +# define AT32_CAN1_TMDTH1 (AT32_CAN1_BASE+AT32_CAN_TMDTH1_OFFSET) +# define AT32_CAN1_TMDTH2 (AT32_CAN1_BASE+AT32_CAN_TMDTH2_OFFSET) +# define AT32_CAN1_RFI(x) (AT32_CAN1_BASE+AT32_CAN_RFI_OFFSET(x)) +# define AT32_CAN1_RFI0 (AT32_CAN1_BASE+AT32_CAN_RFI0_OFFSET) +# define AT32_CAN1_RFI1 (AT32_CAN1_BASE+AT32_CAN_RFI1_OFFSET) +# define AT32_CAN1_RFC(x) (AT32_CAN1_BASE+AT32_CAN_RFC_OFFSET(x)) +# define AT32_CAN1_RFC0 (AT32_CAN1_BASE+AT32_CAN_RFC0_OFFSET) +# define AT32_CAN1_RFC1 (AT32_CAN1_BASE+AT32_CAN_RFC1_OFFSET) +# define AT32_CAN1_RFDTL(x) (AT32_CAN1_BASE+AT32_CAN_RFDTL_OFFSET(x)) +# define AT32_CAN1_RFDTL0 (AT32_CAN1_BASE+AT32_CAN_RFDTL0_OFFSET) +# define AT32_CAN1_RFDTL1 (AT32_CAN1_BASE+AT32_CAN_RFDTL1_OFFSET) +# define AT32_CAN1_RFDTH(x) (AT32_CAN1_BASE+AT32_CAN_RFDTH_OFFSET(x)) +# define AT32_CAN1_RFDTH0 (AT32_CAN1_BASE+AT32_CAN_RFDTH0_OFFSET) +# define AT32_CAN1_RFDTH1 (AT32_CAN1_BASE+AT32_CAN_RFDTH1_OFFSET) +# define AT32_CAN1_FCTRL (AT32_CAN1_BASE+AT32_CAN_FCTRL_OFFSET) +# define AT32_CAN1_FMCFG (AT32_CAN1_BASE+AT32_CAN_FMCFG_OFFSET) +# define AT32_CAN1_FSCFG (AT32_CAN1_BASE+AT32_CAN_FSCFG_OFFSET) +# define AT32_CAN1_FRF (AT32_CAN1_BASE+AT32_CAN_FRF_OFFSET) +# define AT32_CAN1_FACFG (AT32_CAN1_BASE+AT32_CAN_FACFG_OFFSET) +# define AT32_CAN1_FIR(b,i) (AT32_CAN1_BASE+AT32_CAN_FIR_OFFSET(b,i)) #endif #if AT32_NCAN > 1 @@ -180,41 +180,41 @@ # define AT32_CAN2_RF1 (AT32_CAN2_BASE+AT32_CAN_RF1_OFFSET) # define AT32_CAN2_INTEN (AT32_CAN2_BASE+AT32_CAN_INTEN_OFFSET) # define AT32_CAN2_ESTS (AT32_CAN2_BASE+AT32_CAN_ESTS_OFFSET) -# define AT32_CAN2_BTMG (AT32_CAN2_BASE+AT32_CAN_BTMG_OFFSET) -# define AT32_CAN2_TMI(x) (AT32_CAN2_BASE+AT32_CAN_TMI_OFFSET(x)) -# define AT32_CAN2_TMI0 (AT32_CAN2_BASE+AT32_CAN_TMI0_FFSET) -# define AT32_CAN2_TMI1 (AT32_CAN2_BASE+AT32_CAN_TMI1_FFSET) -# define AT32_CAN2_TMI2 (AT32_CAN2_BASE+AT32_CAN_TMI2_FFSET) -# define AT32_CAN2_TMC(x) (AT32_CAN2_BASE+AT32_CAN_TMC_OFFSET(x)) -# define AT32_CAN2_TMC0 (AT32_CAN2_BASE+AT32_CAN_TMC0_OFFSET) -# define AT32_CAN2_TMC1 (AT32_CAN2_BASE+AT32_CAN_TMC1_OFFSET) -# define AT32_CAN2_TMC2 (AT32_CAN2_BASE+AT32_CAN_TMC2_OFFSET) -# define AT32_CAN2_TMDTL(x) (AT32_CAN2_BASE+AT32_CAN_TMDTL_OFFSET(x)) -# define AT32_CAN2_TMDTL0 (AT32_CAN2_BASE+AT32_CAN_TMDTL0_OFFSET) -# define AT32_CAN2_TMDTL1 (AT32_CAN2_BASE+AT32_CAN_TMDTL1_OFFSET) -# define AT32_CAN2_TMDTL2 (AT32_CAN2_BASE+AT32_CAN_TMDTL2_OFFSET) -# define AT32_CAN2_TMDTH(x) (AT32_CAN2_BASE+AT32_CAN_TMDTH_OFFSET(x)) -# define AT32_CAN2_TMDTH0 (AT32_CAN2_BASE+AT32_CAN_TMDTH0_OFFSET) -# define AT32_CAN2_TMDTH1 (AT32_CAN2_BASE+AT32_CAN_TMDTH1_OFFSET) -# define AT32_CAN2_TMDTH2 (AT32_CAN2_BASE+AT32_CAN_TMDTH2_OFFSET) -# define AT32_CAN2_RFI(x) (AT32_CAN2_BASE+AT32_CAN_RFI_OFFSET(x)) -# define AT32_CAN2_RFI0 (AT32_CAN2_BASE+AT32_CAN_RFI0_OFFSET) -# define AT32_CAN2_RFI1 (AT32_CAN2_BASE+AT32_CAN_RFI1_OFFSET) -# define AT32_CAN2_RFC(x) (AT32_CAN2_BASE+AT32_CAN_RFC_OFFSET(x)) -# define AT32_CAN2_RFC0 (AT32_CAN2_BASE+AT32_CAN_RFC0_OFFSET) -# define AT32_CAN2_RFC1 (AT32_CAN2_BASE+AT32_CAN_RFC1_OFFSET) -# define AT32_CAN2_RFDTL(x) (AT32_CAN2_BASE+AT32_CAN_RFDTL_OFFSET(x)) -# define AT32_CAN2_RFDTL0 (AT32_CAN2_BASE+AT32_CAN_RFDTL0_OFFSET) -# define AT32_CAN2_RFDTL1 (AT32_CAN2_BASE+AT32_CAN_RFDTL1_OFFSET) -# define AT32_CAN2_RFDTH(x) (AT32_CAN2_BASE+AT32_CAN_RFDTH_OFFSET(x)) -# define AT32_CAN2_RFDTH0 (AT32_CAN2_BASE+AT32_CAN_RFDTH0_OFFSET) -# define AT32_CAN2_RFDTH1 (AT32_CAN2_BASE+AT32_CAN_RFDTH1_OFFSET) -# define AT32_CAN2_FCTRL (AT32_CAN2_BASE+AT32_CAN_FCTRL_OFFSET) -# define AT32_CAN2_FMCFG (AT32_CAN2_BASE+AT32_CAN_FMCFG_OFFSET) -# define AT32_CAN2_FSCFG (AT32_CAN2_BASE+AT32_CAN_FSCFG_OFFSET) -# define AT32_CAN2_FRF (AT32_CAN2_BASE+AT32_CAN_FRF_OFFSET) -# define AT32_CAN2_FACFG (AT32_CAN2_BASE+AT32_CAN_FACFG_OFFSET) -# define AT32_CAN2_FIR(b,i) (AT32_CAN2_BASE+AT32_CAN_FIR_OFFSET(b,i)) +# define AT32_CAN2_BTMG (AT32_CAN2_BASE+AT32_CAN_BTMG_OFFSET) +# define AT32_CAN2_TMI(x) (AT32_CAN2_BASE+AT32_CAN_TMI_OFFSET(x)) +# define AT32_CAN2_TMI0 (AT32_CAN2_BASE+AT32_CAN_TMI0_FFSET) +# define AT32_CAN2_TMI1 (AT32_CAN2_BASE+AT32_CAN_TMI1_FFSET) +# define AT32_CAN2_TMI2 (AT32_CAN2_BASE+AT32_CAN_TMI2_FFSET) +# define AT32_CAN2_TMC(x) (AT32_CAN2_BASE+AT32_CAN_TMC_OFFSET(x)) +# define AT32_CAN2_TMC0 (AT32_CAN2_BASE+AT32_CAN_TMC0_OFFSET) +# define AT32_CAN2_TMC1 (AT32_CAN2_BASE+AT32_CAN_TMC1_OFFSET) +# define AT32_CAN2_TMC2 (AT32_CAN2_BASE+AT32_CAN_TMC2_OFFSET) +# define AT32_CAN2_TMDTL(x) (AT32_CAN2_BASE+AT32_CAN_TMDTL_OFFSET(x)) +# define AT32_CAN2_TMDTL0 (AT32_CAN2_BASE+AT32_CAN_TMDTL0_OFFSET) +# define AT32_CAN2_TMDTL1 (AT32_CAN2_BASE+AT32_CAN_TMDTL1_OFFSET) +# define AT32_CAN2_TMDTL2 (AT32_CAN2_BASE+AT32_CAN_TMDTL2_OFFSET) +# define AT32_CAN2_TMDTH(x) (AT32_CAN2_BASE+AT32_CAN_TMDTH_OFFSET(x)) +# define AT32_CAN2_TMDTH0 (AT32_CAN2_BASE+AT32_CAN_TMDTH0_OFFSET) +# define AT32_CAN2_TMDTH1 (AT32_CAN2_BASE+AT32_CAN_TMDTH1_OFFSET) +# define AT32_CAN2_TMDTH2 (AT32_CAN2_BASE+AT32_CAN_TMDTH2_OFFSET) +# define AT32_CAN2_RFI(x) (AT32_CAN2_BASE+AT32_CAN_RFI_OFFSET(x)) +# define AT32_CAN2_RFI0 (AT32_CAN2_BASE+AT32_CAN_RFI0_OFFSET) +# define AT32_CAN2_RFI1 (AT32_CAN2_BASE+AT32_CAN_RFI1_OFFSET) +# define AT32_CAN2_RFC(x) (AT32_CAN2_BASE+AT32_CAN_RFC_OFFSET(x)) +# define AT32_CAN2_RFC0 (AT32_CAN2_BASE+AT32_CAN_RFC0_OFFSET) +# define AT32_CAN2_RFC1 (AT32_CAN2_BASE+AT32_CAN_RFC1_OFFSET) +# define AT32_CAN2_RFDTL(x) (AT32_CAN2_BASE+AT32_CAN_RFDTL_OFFSET(x)) +# define AT32_CAN2_RFDTL0 (AT32_CAN2_BASE+AT32_CAN_RFDTL0_OFFSET) +# define AT32_CAN2_RFDTL1 (AT32_CAN2_BASE+AT32_CAN_RFDTL1_OFFSET) +# define AT32_CAN2_RFDTH(x) (AT32_CAN2_BASE+AT32_CAN_RFDTH_OFFSET(x)) +# define AT32_CAN2_RFDTH0 (AT32_CAN2_BASE+AT32_CAN_RFDTH0_OFFSET) +# define AT32_CAN2_RFDTH1 (AT32_CAN2_BASE+AT32_CAN_RFDTH1_OFFSET) +# define AT32_CAN2_FCTRL (AT32_CAN2_BASE+AT32_CAN_FCTRL_OFFSET) +# define AT32_CAN2_FMCFG (AT32_CAN2_BASE+AT32_CAN_FMCFG_OFFSET) +# define AT32_CAN2_FSCFG (AT32_CAN2_BASE+AT32_CAN_FSCFG_OFFSET) +# define AT32_CAN2_FRF (AT32_CAN2_BASE+AT32_CAN_FRF_OFFSET) +# define AT32_CAN2_FACFG (AT32_CAN2_BASE+AT32_CAN_FACFG_OFFSET) +# define AT32_CAN2_FIR(b,i) (AT32_CAN2_BASE+AT32_CAN_FIR_OFFSET(b,i)) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/at32/hardware/at32_tim.h b/arch/arm/src/at32/hardware/at32_tim.h index 3e8835b0c55..0d3e9e7db49 100644 --- a/arch/arm/src/at32/hardware/at32_tim.h +++ b/arch/arm/src/at32/hardware/at32_tim.h @@ -646,13 +646,13 @@ /* Capture/compare mode register 3 -- Output compare mode */ -#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ -#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ /* Capture/compare enable register */ diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h b/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h index 0b30817341f..1f23582d3b9 100644 --- a/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h +++ b/arch/arm/src/mx8mp/hardware/mx8mp_pinmux.h @@ -922,7 +922,7 @@ /* Helpers for common configurations */ -#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE2) -#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE) +#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE2) +#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE) #endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_PINMUX_H */ diff --git a/boards/arm/at32/at32f437-mini/include/board.h b/boards/arm/at32/at32f437-mini/include/board.h index 8d5a724b5cf..8f0f75cc9b1 100644 --- a/boards/arm/at32/at32f437-mini/include/board.h +++ b/boards/arm/at32/at32f437-mini/include/board.h @@ -198,7 +198,7 @@ * board the AT32F437-MINI. The following definitions describe how NuttX * controls the LEDs: * - * SYMBOL Meaning LED state + * SYMBOL Meaning LED state * LED1 LED2 * ------------------- ----------------------- -------- -------- * LED_STARTED NuttX has been started OFF OFF @@ -221,13 +221,11 @@ #define LED_ASSERTION 2 #define LED_PANIC 3 -/* USB */ - -/** +/* USB * pll clock = AT32_HCLK_FREQUENCY(288MHz) * usb clock use pll * usb_clk = 288/6 = 48MHz - * **/ + */ #define USB_CONFIG_USBDIV (CRM_MISC2_USBDIV_6P0) /* USART1 */ @@ -254,9 +252,9 @@ /* ETH */ -#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1 //PB11 -#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1 //PB12 -#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 //PB13 +#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1 /* PB11 */ +#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1 /* PB12 */ +#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 /* PB13 */ /* I2C */ diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h index 3fd1fac623a..210f56e2a25 100644 --- a/include/nuttx/fs/ioctl.h +++ b/include/nuttx/fs/ioctl.h @@ -656,8 +656,8 @@ /* (see nuttx/include/crypto/se05x.h */ -#define _SEIOCVALID(c) (_IOC_TYPE(c)==_SEIOCBASE) -#define _SEIOC(nr) _IOC(_SEIOCBASE,nr) +#define _SEIOCVALID(c) (_IOC_TYPE(c)==_SEIOCBASE) +#define _SEIOC(nr) _IOC(_SEIOCBASE,nr) /* syslog driver ioctl definitions ******************************************/