diff --git a/arch/arm/src/stm32h5/stm32_timerisr.c b/arch/arm/src/stm32h5/stm32_timerisr.c
index 448f063b87f..d985e469cfc 100644
--- a/arch/arm/src/stm32h5/stm32_timerisr.c
+++ b/arch/arm/src/stm32h5/stm32_timerisr.c
@@ -58,9 +58,9 @@
  * And I don't know now to re-configure it yet
  */
 
-#undef CONFIG_STM32H5_SYSTICK_HCLKd8
+#undef CONFIG_STM32_SYSTICK_HCLKd8
 
-#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
 #else
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
@@ -123,7 +123,7 @@ void up_timer_initialize(void)
 
 #if 0 /* Does not work.  Comes up with HCLK source and I can't change it */
   regval = getreg32(NVIC_SYSTICK_CTRL);
-#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
   regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
 #else
   regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
diff --git a/arch/arm/src/stm32h7/stm32_timerisr.c b/arch/arm/src/stm32h7/stm32_timerisr.c
index b2f37b5f580..e5bd4cf0515 100644
--- a/arch/arm/src/stm32h7/stm32_timerisr.c
+++ b/arch/arm/src/stm32h7/stm32_timerisr.c
@@ -66,14 +66,14 @@
  *     224-1).
  */
 
-#undef CONFIG_STM32H7_SYSTICK_HCLKd8
+#undef CONFIG_STM32_SYSTICK_HCLKd8
 
 /* REVISIT:
  *   It looks like SYSTICK for H7 is always clocked from CPUCLK and doesn't
  *   depend on the SYSTICK_CTRL_CLKSOURCE bit settings.
  */
 
-#ifdef CONFIG_STM32H7_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
 #  define STM32_SYSTICK_CLOCK  (STM32_HCLK_FREQUENCY / 8)
 #else
 #  define STM32_SYSTICK_CLOCK  (STM32_CPUCLK_FREQUENCY)
@@ -155,7 +155,7 @@ void up_timer_initialize(void)
    */
 
   regval  = (NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE);
-#ifndef CONFIG_STM32H7_SYSTICK_HCLKd8
+#ifndef CONFIG_STM32_SYSTICK_HCLKd8
   regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
 #else
   regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c
index 6f0b332f960..2c2b0747a38 100644
--- a/arch/arm/src/stm32l4/stm32l4_timerisr.c
+++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c
@@ -54,10 +54,10 @@
  * register.
  */
 
-#undef CONFIG_STM32L4_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
+#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
                                    /* And I don't know now to re-configure it yet */
 
-#ifdef CONFIG_STM32L4_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
 #else
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
@@ -120,7 +120,7 @@ void up_timer_initialize(void)
 
 #if 0 /* Does not work.  Comes up with HCLK source and I can't change it */
   regval = getreg32(NVIC_SYSTICK_CTRL);
-#ifdef CONFIG_STM32L4_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
   regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
 #else
   regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c
index 169200141ce..0415a3ece42 100644
--- a/arch/arm/src/stm32l5/stm32l5_timerisr.c
+++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c
@@ -58,9 +58,9 @@
  * And I don't know now to re-configure it yet
  */
 
-#undef CONFIG_STM32L5_SYSTICK_HCLKd8
+#undef CONFIG_STM32_SYSTICK_HCLKd8
 
-#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
 #else
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
@@ -123,7 +123,7 @@ void up_timer_initialize(void)
 
 #if 0 /* Does not work.  Comes up with HCLK source and I can't change it */
   regval = getreg32(NVIC_SYSTICK_CTRL);
-#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
   regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
 #else
   regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
diff --git a/arch/arm/src/stm32u5/stm32_timerisr.c b/arch/arm/src/stm32u5/stm32_timerisr.c
index 5cd2f7175dd..3c6aee94222 100644
--- a/arch/arm/src/stm32u5/stm32_timerisr.c
+++ b/arch/arm/src/stm32u5/stm32_timerisr.c
@@ -58,9 +58,9 @@
  * And I don't know now to re-configure it yet
  */
 
-#undef CONFIG_STM32U5_SYSTICK_HCLKd8
+#undef CONFIG_STM32_SYSTICK_HCLKd8
 
-#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
 #else
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
@@ -123,7 +123,7 @@ void up_timer_initialize(void)
 
 #if 0 /* Does not work.  Comes up with HCLK source and I can't change it */
   regval = getreg32(NVIC_SYSTICK_CTRL);
-#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
   regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
 #else
   regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c
index 393417ca3d9..4de3d6b3936 100644
--- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c
+++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c
@@ -59,9 +59,9 @@
  * And I don't know now to re-configure it yet
  */
 
-#undef CONFIG_STM32WL5_SYSTICK_HCLKd8
+#undef CONFIG_STM32_SYSTICK_HCLKd8
 
-#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
 #else
 #  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
@@ -124,7 +124,7 @@ void up_timer_initialize(void)
 
 #if 0 /* Does not work.  Comes up with HCLK source and I can't change it */
   regval = getreg32(NVIC_SYSTICK_CTRL);
-#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8
+#ifdef CONFIG_STM32_SYSTICK_HCLKd8
   regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
 #else
   regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;