From 2d92d7825dc70c5ec96afbf39b00aad0c0c9d2ff Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Thu, 26 Dec 2013 10:45:21 -0600
Subject: [PATCH] STM32F107 OTG FS clock presecaler cannot be configurated
 after the USB clock is enabled

---
 arch/arm/src/stm32/chip/stm32f10xxx_rcc.h |  5 ++++-
 arch/arm/src/stm32/stm32f10xxx_rcc.c      | 25 +++++++++++++++--------
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
index 80a55809517..0eaf2f3107a 100644
--- a/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
@@ -164,7 +164,10 @@
 #  define RCC_CFGR_PLLMUL_CLKx15    (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
 #  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
 #ifndef CONFIG_STM32_VALUELINE
-#  define RCC_CFGR_USBPRE           (1 << 22) /* Bit 22: USB/OTG FS prescaler */
+#  define RCC_CFGR_USBPRE           (1 << 22) /* Bit 22: USB FS prescaler */
+#endif
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_CFGR_OTGFSPRE         (1 << 22) /* Bit 22: OTG FS prescaler */
 #endif
 #define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 27-24: Microcontroller Clock Output */
 #define RCC_CFGR_MCO_MASK           (15 << RCC_CFGR_MCO_SHIFT)
diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c
index bd660e1b3da..f887f89959f 100644
--- a/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -114,6 +114,18 @@ static inline void rcc_enableahb(void)
 {
   uint32_t regval;
 
+#if defined(CONFIG_STM32_CONNECTIVITYLINE) && defined(CONFIG_STM32_OTGFS)
+  /* USB clock divider for USB OTG FS.  This bit must be valid before
+   * enabling the USB clock in the RCC_AHBENR register.  This bit can't be
+   * reset if the USB clock is enabled.
+   */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_OTGFSPRE;
+  regval |= STM32_CFGR_OTGFSPRE;
+  putreg32(regval, STM32_RCC_CFGR);
+#endif
+
   /* Always enable FLITF clock and SRAM clock */
 
   regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN;
@@ -176,16 +188,13 @@ static inline void rcc_enableahb(void)
 static inline void rcc_enableapb1(void)
 {
   uint32_t regval;
-
-#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_OTGFS)
-  /* USB clock divider for USB FD device or USB OTG FS (OTGFS naming for this
-   * bit is different, but it is the same bit.
-   *
-   * This bit must be valid before enabling the either the USB clock in the
-   * RCC_APB1ENR register ro the OTG FS clock in the AHBENR reigser. This
-   * bit can’t be reset if the USB clock is enabled.
+#ifdef CONFIG_STM32_USB
+  /* USB clock divider for USB FS device.  This bit must be valid before
+   * enabling the USB clock in the RCC_APB1ENR register. This bit can't be
+   * reset if the USB clock is enabled.
    */
 
+
   regval  = getreg32(STM32_RCC_CFGR);
   regval &= ~RCC_CFGR_USBPRE;
   regval |= STM32_CFGR_USBPRE;