diff --git a/arch/risc-v/include/fe310/irq.h b/arch/risc-v/include/fe310/irq.h
index 948e464a55d..987ea93e5f1 100644
--- a/arch/risc-v/include/fe310/irq.h
+++ b/arch/risc-v/include/fe310/irq.h
@@ -43,9 +43,14 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Machine Interrupt Enable bit in mstatus register */
+/* In mstatus register */
 
-#define MSTATUS_MIE  (0x1 << 3)
+#define MSTATUS_MIE   (0x1 << 3)  /* Machine Interrupt Enable */
+
+/* In mie (machine interrupt enable) register */
+
+#define MIE_MTIE      (0x1 << 7)  /* Machine Timer Interrupt Enable */
+#define MIE_MEIE      (0x1 << 11) /* Machine External Interrupt Enable */
 
 /* Map RISC-V exception code to NuttX IRQ */
 
diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c
index 90bdbe11262..5dd26a0b01a 100644
--- a/arch/risc-v/src/fe310/fe310_irq.c
+++ b/arch/risc-v/src/fe310/fe310_irq.c
@@ -51,12 +51,6 @@
 
 #include "fe310.h"
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-volatile uint32_t *g_current_regs;
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -71,6 +65,11 @@ void up_irqinitialize(void)
 
   (void)up_irq_save();
 
+  /* Disable all global interrupts */
+
+  putreg32(0x0, FE310_PLIC_ENABLE1);
+  putreg32(0x0, FE310_PLIC_ENABLE2);
+
   /* Colorize the interrupt stack for debug purposes */
 
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
@@ -120,8 +119,15 @@ void up_irqinitialize(void)
 void up_disable_irq(int irq)
 {
   int extirq;
+  uint32_t oldstat;
 
-  if (irq > FE310_IRQ_MEXT)
+  if (irq == FE310_IRQ_MTIMER)
+    {
+      /* Read mstatus & clear machine timer interrupt enable in mie */
+
+      asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
+    }
+  else if (irq > FE310_IRQ_MEXT)
     {
       extirq = irq - FE310_IRQ_MEXT;
       ASSERT(31 >= extirq); /* TODO */
@@ -143,8 +149,15 @@ void up_disable_irq(int irq)
 void up_enable_irq(int irq)
 {
   int extirq;
+  uint32_t oldstat;
 
-  if (irq > FE310_IRQ_MEXT)
+  if (irq == FE310_IRQ_MTIMER)
+    {
+      /* Read mstatus & set machine timer interrupt enable in mie */
+
+      asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
+    }
+  else if (irq > FE310_IRQ_MEXT)
     {
       extirq = irq - FE310_IRQ_MEXT;
       ASSERT(31 >= extirq); /* TODO */
@@ -224,18 +237,13 @@ void up_irq_restore(irqstate_t flags)
 irqstate_t up_irq_enable(void)
 {
   uint32_t oldstat;
-  uint32_t newstat;
-  uint32_t mie;
 
 #if 1
-  /* Enable MEIE (machine external interrupt enable)
-   * and MTIE (machine timer interrupt enable)
-   */
+  /* Enable MEIE (machine external interrupt enable) */
 
   /* TODO: should move to up_enable_irq() */
 
-  mie = 0x1 << 11 | 0x1 << 7;
-  asm volatile("csrw mie, %0" : /* no output */ : "r" (mie));
+  asm volatile("csrw mie, %0" : /* no output */ : "r"(MIE_MEIE));
 #endif
 
   /* Read mstatus & set machine interrupt enable (MIE) in mstatus */
diff --git a/arch/risc-v/src/fe310/fe310_lowputc.c b/arch/risc-v/src/fe310/fe310_lowputc.c
index 765e7baf2e3..4675e2a3842 100644
--- a/arch/risc-v/src/fe310/fe310_lowputc.c
+++ b/arch/risc-v/src/fe310/fe310_lowputc.c
@@ -79,6 +79,8 @@
 #  endif
 #endif /* HAVE_CONSOLE */
 
+#define HFCLK 16000000 /* TODO */
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -124,8 +126,14 @@ void fe310_lowsetup(void)
 
 #if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
 
-  /* TODO: Configure the UART Baud Rate */
+  /* Configure the UART Baud Rate */
 
+  uint32_t div = HFCLK / 115200 - 1;
+  putreg32(div, FE310_CONSOLE_BASE + UART_DIV_OFFSET);
+
+  /* Enable TX */
+
+  putreg32(1, FE310_CONSOLE_BASE + UART_TXCTL_OFFSET);
 #endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
 #endif /* HAVE_UART */
 }
diff --git a/arch/risc-v/src/fe310/fe310_start.c b/arch/risc-v/src/fe310/fe310_start.c
index 7a35d3915bf..75b88ff766c 100644
--- a/arch/risc-v/src/fe310/fe310_start.c
+++ b/arch/risc-v/src/fe310/fe310_start.c
@@ -100,17 +100,20 @@ void __fe310_start(void)
       *dest++ = *src++;
     }
 
-  showprogress('A');
+  /* TODO: Setup PLL */
 
   /* Configure the UART so we can get debug output */
 
   fe310_lowsetup();
 
-  showprogress('B');
+  showprogress('A');
 
 #ifdef USE_EARLYSERIALINIT
   up_earlyserialinit();
 #endif
+
+  showprogress('B');
+
   /* Do board initialization */
 
   fe310_boardinitialize();
diff --git a/arch/risc-v/src/fe310/hardware/fe310_plic.h b/arch/risc-v/src/fe310/hardware/fe310_plic.h
index 66311742600..cb6a75ace17 100644
--- a/arch/risc-v/src/fe310/hardware/fe310_plic.h
+++ b/arch/risc-v/src/fe310/hardware/fe310_plic.h
@@ -40,6 +40,7 @@
 #define FE310_PLIC_PRIORITY    (FE310_PLIC_BASE + 0x000000)
 #define FE310_PLIC_PENDING1    (FE310_PLIC_BASE + 0x001000)
 #define FE310_PLIC_ENABLE1     (FE310_PLIC_BASE + 0x002000)
+#define FE310_PLIC_ENABLE2     (FE310_PLIC_BASE + 0x002004)
 #define FE310_PLIC_THRESHOLD   (FE310_PLIC_BASE + 0x200000)
 #define FE310_PLIC_CLAIM       (FE310_PLIC_BASE + 0x200004)
 
diff --git a/boards/risc-v/fe310/hifive1-revb/README-qemu.txt b/boards/risc-v/fe310/hifive1-revb/README-qemu.txt
new file mode 100644
index 00000000000..9130d528d28
--- /dev/null
+++ b/boards/risc-v/fe310/hifive1-revb/README-qemu.txt
@@ -0,0 +1,43 @@
+1. Download and install toolchain
+
+  $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
+
+2. Build and install qemu
+
+  $ git clone https://github.com/qemu/qemu
+  $ cd qemu
+  $ ./configure --target-list=riscv32-softmmu
+  $ make
+  $ sudo make install
+
+3. Modify flash origin address
+
+index 559c1813b8..a67c37b576 100644
+--- a/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
++++ b/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
+@@ -35,7 +35,7 @@
+
+ MEMORY
+ {
+-  flash (rx) : ORIGIN = 0x20010000, LENGTH = 4096K
++  flash (rx) : ORIGIN = 0x20400000, LENGTH = 4096K
+   sram (rwx) : ORIGIN = 0x80000000, LENGTH = 16K
+ }
+
+4. Configure and build NuttX
+
+  $ mkdir ./nuttx; cd ./nuttx
+  $ git clone https://bitbucket.org/nuttx/nuttx.git
+  $ git clone https://bitbucket.org/nuttx/apps.git
+  $ cd nuttx
+  $ make distclean
+  $ ./tools/configure.sh hifive1-revb:nsh
+  $ make V=1
+
+5. Run the nuttx with qemu
+
+  $ qemu-system-riscv32 -nographic -machine sifive_e -kernel ./nuttx
+
+6. TODO
+
+  Support RISC-V User mode
diff --git a/boards/risc-v/fe310/hifive1-revb/README.txt b/boards/risc-v/fe310/hifive1-revb/README.txt
index 56e050984fc..dd8ab419b9b 100644
--- a/boards/risc-v/fe310/hifive1-revb/README.txt
+++ b/boards/risc-v/fe310/hifive1-revb/README.txt
@@ -2,13 +2,11 @@
 
   $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
 
-2. Build and install qemu
+2. Download and install J-Link Software Documentation Pack
 
-  $ git clone https://github.com/qemu/qemu
-  $ cd qemu
-  $ ./configure --target-list=riscv32-softmmu
-  $ make
-  $ sudo make install
+  https://www.segger.com/downloads/jlink/
+
+  $ sudo apt install JLink_Linux_V656b_x86_64.deb
 
 3. Configure and build NuttX
 
@@ -20,13 +18,19 @@
   $ ./tools/configure.sh hifive1-revb:nsh
   $ make V=1
 
-4. Run the nuttx with qemu
+4. Flash the nuttx with J-Link and run
 
-  $ qemu-system-riscv32 -nographic -machine sifive_e -kernel ./nuttx
+  $ picocom -b 115200 /dev/ttyACM0
+
+  $ /opt/SEGGER/JLink_V656b/JLinkGDBServer -device FE310
+
+  $ riscv64-unknown-elf-gdb ./nuttx
+  (gdb) target extended-remote:2331
+  (gdb) load nuttx
+  (gdb) c
 
 5. TODO
 
-  Configure PLL and UART divisor
-  Run nuttx on HiFive1-Rev.B board
+  Configure PLL
   Support GPIO/SPI/I2C/RTC/WDT/PWM
   Support RISC-V User mode
diff --git a/boards/risc-v/fe310/hifive1-revb/scripts/ld.script b/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
index a67c37b5768..559c1813b88 100644
--- a/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
+++ b/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
@@ -35,7 +35,7 @@
 
 MEMORY
 {
-  flash (rx) : ORIGIN = 0x20400000, LENGTH = 4096K
+  flash (rx) : ORIGIN = 0x20010000, LENGTH = 4096K
   sram (rwx) : ORIGIN = 0x80000000, LENGTH = 16K
 }