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https://github.com/apache/nuttx.git
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arch/arm, board/arm: Rename all up_* functions to arm_*
Summary The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private functions begin with the name of the architecture, not up_. This PR addresses only these name changes for the ARM-private functions prototyped in arm_internal.h This change to the files only modifies the name of called functions. nxstyle fixes were made for all core architecture files. However, there are well over 5000 additional complaints from MCU drivers and board logic that are unrelated to to this change but were affected by the name change. It is not humanly possible to fix all of these. I ask that this change be treated like other cosmetic changes that we have done which do not require full nxstyle compliance. Impact There should be not impact of this change (other that one step toward more consistent naming). Testing stm32f4discovery:netnsh
This commit is contained in:
Gregory Nutt
Abdelatif Guettouche
parent
c1beda50f8
commit
2aa85fd17e
338 changed files with 1401 additions and 1506 deletions
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@ -342,7 +342,7 @@ void arm_boot(void)
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* driver.
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*/
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up_earlyserialinit();
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arm_earlyserialinit();
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#endif
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/* Perform board-specific initialization, This must include:
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@ -191,14 +191,14 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_lowputc
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* Name: arm_lowputc
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*
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* Description:
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* Output one byte on the serial console
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*
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****************************************************************************/
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void up_lowputc(char ch)
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void arm_lowputc(char ch)
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{
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#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE
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/* Wait for the transmitter to be available */
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@ -1452,19 +1452,19 @@ static bool up_txempty(struct uart_dev_s *dev)
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#ifdef USE_EARLYSERIALINIT
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/****************************************************************************
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* Name: up_earlyserialinit
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* Name: arm_earlyserialinit
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*
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* Description:
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* Performs the low level UART initialization early in debug so that the
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* serial console will be available during bootup. This must be called
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* before up_serialinit.
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* before arm_serialinit.
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*
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* NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
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* very early in the boot sequence.
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*
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****************************************************************************/
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void up_earlyserialinit(void)
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void arm_earlyserialinit(void)
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{
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/* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
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@ -1535,15 +1535,15 @@ void up_earlyserialinit(void)
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#endif
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/****************************************************************************
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* Name: up_serialinit
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* Name: arm_serialinit
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*
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* Description:
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* Register serial console and serial ports. This assumes that
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* up_earlyserialinit was called previously.
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* arm_earlyserialinit was called previously.
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*
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****************************************************************************/
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void up_serialinit(void)
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void arm_serialinit(void)
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{
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#ifdef CONSOLE_DEV
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uart_register("/dev/console", &CONSOLE_DEV);
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@ -1596,10 +1596,10 @@ int up_putc(int ch)
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{
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/* Add CR */
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up_lowputc('\r');
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arm_lowputc('\r');
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}
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up_lowputc(ch);
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arm_lowputc(ch);
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#ifdef HAVE_SERIAL_CONSOLE
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up_restoreuartint(priv, ier);
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#endif
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@ -1626,10 +1626,10 @@ int up_putc(int ch)
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{
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/* Add CR */
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up_lowputc('\r');
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arm_lowputc('\r');
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}
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up_lowputc(ch);
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arm_lowputc(ch);
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#endif
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return ch;
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}
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@ -82,7 +82,7 @@
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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# define showprogress(c) up_lowputc(c)
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# define showprogress(c) arm_lowputc(c)
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#else
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# define showprogress(c)
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#endif
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@ -464,7 +464,7 @@ void arm_boot(void)
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* driver.
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*/
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up_earlyserialinit();
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arm_earlyserialinit();
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#endif
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/* Perform board-specific initialization, This must include:
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@ -161,14 +161,14 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_lowputc
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* Name: arm_lowputc
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*
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* Description:
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* Output one byte on the serial console
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*
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****************************************************************************/
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void up_lowputc(char ch)
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void arm_lowputc(char ch)
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{
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#if defined(HAVE_UART_DEVICE) && defined(HAVE_SERIAL_CONSOLE)
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/* Wait for the transmitter to be available */
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@ -1269,19 +1269,19 @@ static bool up_txempty(struct uart_dev_s *dev)
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#ifdef USE_EARLYSERIALINIT
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/****************************************************************************
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* Name: up_earlyserialinit
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* Name: arm_earlyserialinit
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*
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* Description:
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* Performs the low level UART initialization early in debug so that the
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* serial console will be available during bootup. This must be called
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* before up_serialinit.
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* before arm_serialinit.
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*
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* NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
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* very early in the boot sequence.
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*
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****************************************************************************/
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void up_earlyserialinit(void)
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void arm_earlyserialinit(void)
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{
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/* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
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@ -1338,15 +1338,15 @@ void up_earlyserialinit(void)
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#endif
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/****************************************************************************
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* Name: up_serialinit
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* Name: arm_serialinit
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*
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* Description:
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* Register serial console and serial ports. This assumes that
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* up_earlyserialinit was called previously.
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* arm_earlyserialinit was called previously.
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*
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****************************************************************************/
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void up_serialinit(void)
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void arm_serialinit(void)
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{
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#ifdef CONSOLE_DEV
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uart_register("/dev/console", &CONSOLE_DEV);
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@ -1393,10 +1393,10 @@ int up_putc(int ch)
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{
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/* Add CR */
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up_lowputc('\r');
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arm_lowputc('\r');
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}
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up_lowputc(ch);
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arm_lowputc(ch);
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#ifdef HAVE_SERIAL_CONSOLE
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up_restoreuartint(priv, ier);
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#endif
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@ -1423,10 +1423,10 @@ int up_putc(int ch)
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{
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/* Add CR */
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up_lowputc('\r');
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arm_lowputc('\r');
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}
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up_lowputc(ch);
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arm_lowputc(ch);
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#endif
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return ch;
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}
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@ -203,7 +203,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
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*/
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uintptr_t oldvaddr = PG_POOL_NDX2VA(g_ptemap[pgndx]);
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pte = up_va2pte(oldvaddr);
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pte = arm_va2pte(oldvaddr);
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*pte = 0;
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/* Invalidate instruction TLB corresponding to the virtual address */
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@ -227,7 +227,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
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* non-cached (MMU_L2_ALLOCFLAGS).
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*/
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pte = up_va2pte(vaddr);
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pte = arm_va2pte(vaddr);
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*pte = (paddr | MMU_L2_ALLOCFLAGS);
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/* And save the new L1 index */
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@ -98,7 +98,7 @@ bool up_checkmapping(FAR struct tcb_s *tcb)
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/* Get the PTE associated with this virtual address */
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pte = up_va2pte(vaddr);
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pte = arm_va2pte(vaddr);
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/* Return true if this virtual address is mapped. */
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@ -42,7 +42,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_dataabort
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* Name: arm_dataabort
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*
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* Input Parameters:
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* regs - The standard, ARM register save array.
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@ -64,7 +64,7 @@
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****************************************************************************/
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#ifdef CONFIG_PAGING
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void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
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void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
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{
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struct tcb_s *tcb = this_task();
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#ifdef CONFIG_PAGING
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@ -148,7 +148,7 @@ segfault:
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#else /* CONFIG_PAGING */
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void up_dataabort(uint32_t *regs)
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void arm_dataabort(uint32_t *regs)
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{
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/* Save the saved processor context in CURRENT_REGS where it can be
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* accessed for register dumps and possibly context switching.
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@ -57,7 +57,7 @@
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* Public Functions
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****************************************************************************/
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void up_doirq(int irq, uint32_t *regs)
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void arm_doirq(int irq, uint32_t *regs)
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{
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board_autoled_on(LED_INIRQ);
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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@ -75,7 +75,7 @@ void up_doirq(int irq, uint32_t *regs)
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/* Acknowledge the interrupt */
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up_ack_irq(irq);
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arm_ack_irq(irq);
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/* Deliver the IRQ */
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@ -94,7 +94,7 @@ void up_doirq(int irq, uint32_t *regs)
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#ifdef CONFIG_ARCH_FPU
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/* Restore floating point registers */
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up_restorefpu((uint32_t *)CURRENT_REGS);
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arm_restorefpu((uint32_t *)CURRENT_REGS);
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#endif
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#ifdef CONFIG_ARCH_ADDRENV
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@ -211,7 +211,7 @@
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#ifdef CONFIG_DEBUG_FEATURES
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.macro showprogress, code
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mov r0, #\code
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bl up_lowputc
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bl arm_lowputc
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.endm
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#else
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.macro showprogress, code
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@ -52,7 +52,7 @@
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#ifdef CONFIG_DEBUG_FEATURES
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.macro showprogress, code
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mov r0, #\code
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bl up_lowputc
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bl arm_lowputc
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.endm
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#else
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.macro showprogress, code
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@ -112,7 +112,7 @@ __start:
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mov fp, #0
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#ifdef USE_EARLYSERIALINIT
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bl up_earlyserialinit
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bl arm_earlyserialinit
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#endif
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#ifdef CONFIG_DEBUG_FEATURES
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@ -51,7 +51,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_pginitialize()
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* Name: arm_pginitialize()
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*
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* Description:
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* Initialize the MMU for on-demand paging support..
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@ -69,10 +69,10 @@
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*
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****************************************************************************/
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void up_pginitialize(void)
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void arm_pginitialize(void)
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{
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/* None needed at present. This file is just retained in case the need
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* arises in the future. Nothing calls up_pginitialize() now. If needed,
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* arises in the future. Nothing calls arm_pginitialize() now. If needed,
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* if should be called early in arm_boot.c to assure that all paging is
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* ready.
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*/
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@ -52,7 +52,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_prefetchabort
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* Name: arm_prefetchabort
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*
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* Description:
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* This is the prefetch abort exception handler. The ARM prefetch abort
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@ -61,7 +61,7 @@
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*
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****************************************************************************/
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void up_prefetchabort(uint32_t *regs)
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void arm_prefetchabort(uint32_t *regs)
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{
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#ifdef CONFIG_PAGING
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uint32_t *savestate;
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@ -148,7 +148,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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* disabled
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*/
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CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
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CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
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CURRENT_REGS[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
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/* And make sure that the saved context in the TCB
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@ -180,7 +180,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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* disabled
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*/
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tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
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tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
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tcb->xcp.regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
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}
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}
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@ -58,7 +58,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_sigdeliver
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* Name: arm_sigdeliver
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*
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* Description:
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* This is the a signal handling trampoline. When a signal action was
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@ -67,7 +67,7 @@
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*
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****************************************************************************/
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void up_sigdeliver(void)
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void arm_sigdeliver(void)
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{
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struct tcb_s *rtcb = this_task();
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uint32_t regs[XCPTCONTEXT_REGS];
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@ -52,7 +52,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_syscall
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* Name: arm_syscall
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*
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* Description:
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* SWI interrupts will vector here with insn=the SWI instruction and
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@ -64,7 +64,7 @@
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*
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****************************************************************************/
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void up_syscall(uint32_t *regs)
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void arm_syscall(uint32_t *regs)
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{
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_alert("Syscall from 0x%x\n", regs[REG_PC]);
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CURRENT_REGS = regs;
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@ -52,10 +52,10 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_undefinedinsn
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* Name: arm_undefinedinsn
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****************************************************************************/
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void up_undefinedinsn(uint32_t *regs)
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void arm_undefinedinsn(uint32_t *regs)
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{
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_alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
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CURRENT_REGS = regs;
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@ -69,7 +69,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_va2pte()
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* Name: arm_va2pte()
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*
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* Description:
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* Convert a virtual address within the paged text region into a pointer to
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@ -89,7 +89,7 @@
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*
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****************************************************************************/
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uint32_t *up_va2pte(uintptr_t vaddr)
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uint32_t *arm_va2pte(uintptr_t vaddr)
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{
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uint32_t L1;
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uint32_t *L2;
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@ -75,9 +75,9 @@
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*
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************************************************************************************/
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.globl up_vectoraddrexcptn
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.type up_vectoraddrexcptn, %function
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up_vectoraddrexcptn:
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b up_vectoraddrexcptn
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.size up_vectoraddrexcptn, . - up_vectoraddrexcptn
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.globl arm_vectoraddrexcptn
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.type arm_vectoraddrexcptn, %function
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arm_vectoraddrexcptn:
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b arm_vectoraddrexcptn
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.size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn
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.end
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@ -79,16 +79,16 @@ g_aborttmp:
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.text
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/************************************************************************************
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* Name: up_vectorirq
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* Name: arm_vectorirq
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*
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* Description:
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* Interrupt exception. Entered in IRQ mode with spsr = SVC CPSR, lr = SVC PC
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*
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************************************************************************************/
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.globl up_vectorirq
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.type up_vectorirq, %function
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up_vectorirq:
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.globl arm_vectorirq
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.type arm_vectorirq, %function
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arm_vectorirq:
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/* On entry, we are in IRQ mode. We are free to use
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* the IRQ mode r13 and r14.
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||||
*/
|
||||
|
|
@ -133,10 +133,10 @@ up_vectorirq:
|
|||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
ldr sp, .Lirqstackbase /* SP = interrupt stack base */
|
||||
str r0, [sp] /* Save the user stack pointer */
|
||||
bl up_decodeirq /* Call the handler */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
ldr sp, [sp] /* Restore the user stack pointer */
|
||||
#else
|
||||
bl up_decodeirq /* Call the handler */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
#endif
|
||||
|
||||
/* Restore the CPSR, SVC mode registers and return */
|
||||
|
|
@ -151,20 +151,20 @@ up_vectorirq:
|
|||
.Lirqstackbase:
|
||||
.word g_intstackbase
|
||||
#endif
|
||||
.size up_vectorirq, . - up_vectorirq
|
||||
.size arm_vectorirq, . - arm_vectorirq
|
||||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Function: up_vectorswi
|
||||
* Function: arm_vectorswi
|
||||
*
|
||||
* Description:
|
||||
* SWI interrupt. We enter the SWI in SVC mode.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorswi
|
||||
.type up_vectorswi, %function
|
||||
up_vectorswi:
|
||||
.globl arm_vectorswi
|
||||
.type arm_vectorswi, %function
|
||||
arm_vectorswi:
|
||||
|
||||
/* Create a context structure. First set aside a stack frame
|
||||
* and store r0-r12 into the frame.
|
||||
|
|
@ -185,24 +185,24 @@ up_vectorswi:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the SWI handler with interrupts disabled.
|
||||
* void up_syscall(struct xcptcontext *xcp)
|
||||
* void arm_syscall(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_syscall /* Call the handler */
|
||||
bl arm_syscall /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC mode registers and return */
|
||||
|
||||
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
||||
msr spsr, r0
|
||||
ldmia sp, {r0-r15}^ /* Return */
|
||||
.size up_vectorswi, . - up_vectorswi
|
||||
.size arm_vectorswi, . - arm_vectorswi
|
||||
|
||||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectordata
|
||||
* Name: arm_vectordata
|
||||
*
|
||||
* Description:
|
||||
* This is the data abort exception dispatcher. The ARM data abort exception occurs
|
||||
|
|
@ -212,9 +212,9 @@ up_vectorswi:
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectordata
|
||||
.type up_vectordata, %function
|
||||
up_vectordata:
|
||||
.globl arm_vectordata
|
||||
.type arm_vectordata, %function
|
||||
arm_vectordata:
|
||||
/* On entry we are free to use the ABORT mode registers
|
||||
* r13 and r14
|
||||
*/
|
||||
|
|
@ -252,7 +252,7 @@ up_vectordata:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the data abort handler with interrupts disabled.
|
||||
* void up_dataabort(struct xcptcontext *xcp)
|
||||
* void arm_dataabort(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
|
|
@ -261,7 +261,7 @@ up_vectordata:
|
|||
mrc p15, 0, r2, c5, c0, 0 /* Get r2=FSR */
|
||||
mrc p15, 0, r1, c6, c0, 0 /* Get R1=FAR */
|
||||
#endif
|
||||
bl up_dataabort /* Call the handler */
|
||||
bl arm_dataabort /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC mode registers and return */
|
||||
|
||||
|
|
@ -271,12 +271,12 @@ up_vectordata:
|
|||
|
||||
.Ldaborttmp:
|
||||
.word g_aborttmp
|
||||
.size up_vectordata, . - up_vectordata
|
||||
.size arm_vectordata, . - arm_vectordata
|
||||
|
||||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorprefetch
|
||||
* Name: arm_vectorprefetch
|
||||
*
|
||||
* Description:
|
||||
* This is the prefetch abort exception dispatcher. The ARM prefetch abort exception
|
||||
|
|
@ -286,9 +286,9 @@ up_vectordata:
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorprefetch
|
||||
.type up_vectorprefetch, %function
|
||||
up_vectorprefetch:
|
||||
.globl arm_vectorprefetch
|
||||
.type arm_vectorprefetch, %function
|
||||
arm_vectorprefetch:
|
||||
/* On entry we are free to use the ABORT mode registers
|
||||
* r13 and r14
|
||||
*/
|
||||
|
|
@ -326,12 +326,12 @@ up_vectorprefetch:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the prefetch abort handler with interrupts disabled.
|
||||
* void up_prefetchabort(struct xcptcontext *xcp)
|
||||
* void arm_prefetchabort(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_prefetchabort /* Call the handler */
|
||||
bl arm_prefetchabort /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC mode registers and return */
|
||||
|
||||
|
|
@ -341,12 +341,12 @@ up_vectorprefetch:
|
|||
|
||||
.Lpaborttmp:
|
||||
.word g_aborttmp
|
||||
.size up_vectorprefetch, . - up_vectorprefetch
|
||||
.size arm_vectorprefetch, . - arm_vectorprefetch
|
||||
|
||||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorundefinsn
|
||||
* Name: arm_vectorundefinsn
|
||||
*
|
||||
* Description:
|
||||
* Undefined instruction entry exception. Entered in UND mode, spsr = SVC CPSR,
|
||||
|
|
@ -354,9 +354,9 @@ up_vectorprefetch:
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorundefinsn
|
||||
.type up_vectorundefinsn, %function
|
||||
up_vectorundefinsn:
|
||||
.globl arm_vectorundefinsn
|
||||
.type arm_vectorundefinsn, %function
|
||||
arm_vectorundefinsn:
|
||||
/* On entry we are free to use the UND mode registers
|
||||
* r13 and r14
|
||||
*/
|
||||
|
|
@ -393,12 +393,12 @@ up_vectorundefinsn:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the undef insn handler with interrupts disabled.
|
||||
* void up_undefinedinsn(struct xcptcontext *xcp)
|
||||
* void arm_undefinedinsn(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_undefinedinsn /* Call the handler */
|
||||
bl arm_undefinedinsn /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC mode registers and return */
|
||||
|
||||
|
|
@ -408,23 +408,23 @@ up_vectorundefinsn:
|
|||
|
||||
.Lundeftmp:
|
||||
.word g_undeftmp
|
||||
.size up_vectorundefinsn, . - up_vectorundefinsn
|
||||
.size arm_vectorundefinsn, . - arm_vectorundefinsn
|
||||
|
||||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorfiq
|
||||
* Name: arm_vectorfiq
|
||||
*
|
||||
* Description:
|
||||
* Shouldn't happen
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorfiq
|
||||
.type up_vectorfiq, %function
|
||||
up_vectorfiq:
|
||||
.globl arm_vectorfiq
|
||||
.type arm_vectorfiq, %function
|
||||
arm_vectorfiq:
|
||||
subs pc, lr, #4
|
||||
.size up_vectorfiq, . - up_vectorfiq
|
||||
.size arm_vectorfiq, . - arm_vectorfiq
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc/g_intstackbase
|
||||
|
|
|
|||
|
|
@ -73,30 +73,30 @@ _vector_start:
|
|||
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
|
||||
|
||||
.globl __start
|
||||
.globl up_vectorundefinsn
|
||||
.globl up_vectorswi
|
||||
.globl up_vectorprefetch
|
||||
.globl up_vectordata
|
||||
.globl up_vectoraddrexcptn
|
||||
.globl up_vectorirq
|
||||
.globl up_vectorfiq
|
||||
.globl arm_vectorundefinsn
|
||||
.globl arm_vectorswi
|
||||
.globl arm_vectorprefetch
|
||||
.globl arm_vectordata
|
||||
.globl arm_vectoraddrexcptn
|
||||
.globl arm_vectorirq
|
||||
.globl arm_vectorfiq
|
||||
|
||||
.Lresethandler:
|
||||
.long __start
|
||||
.Lundefinedhandler:
|
||||
.long up_vectorundefinsn
|
||||
.long arm_vectorundefinsn
|
||||
.Lswihandler:
|
||||
.long up_vectorswi
|
||||
.long arm_vectorswi
|
||||
.Lprefetchaborthandler:
|
||||
.long up_vectorprefetch
|
||||
.long arm_vectorprefetch
|
||||
.Ldataaborthandler:
|
||||
.long up_vectordata
|
||||
.long arm_vectordata
|
||||
.Laddrexcptnhandler:
|
||||
.long up_vectoraddrexcptn
|
||||
.long arm_vectoraddrexcptn
|
||||
.Lirqhandler:
|
||||
.long up_vectorirq
|
||||
.long arm_vectorirq
|
||||
.Lfiqhandler:
|
||||
.long up_vectorfiq
|
||||
.long arm_vectorfiq
|
||||
|
||||
.globl _vector_end
|
||||
_vector_end:
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t *up_doirq(int irq, uint32_t *regs)
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
{
|
||||
board_autoled_on(LED_INIRQ);
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
|
@ -80,7 +80,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
|
|||
|
||||
/* Acknowledge the interrupt */
|
||||
|
||||
up_ack_irq(irq);
|
||||
arm_ack_irq(irq);
|
||||
|
||||
/* Deliver the IRQ */
|
||||
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ exception_common:
|
|||
mrs r0, ipsr /* R0=exception number */
|
||||
|
||||
/* Disable interrupts, select the stack to use for interrupt handling
|
||||
* and call up_doirq to handle the interrupt
|
||||
* and call arm_doirq to handle the interrupt
|
||||
*/
|
||||
|
||||
cpsid i /* Disable further interrupts */
|
||||
|
|
@ -155,15 +155,15 @@ exception_common:
|
|||
ldr r7, =g_intstackbase /* R7=Base of the interrupt stack */
|
||||
mov sp, r7 /* Set the new stack point */
|
||||
push {r1} /* Save the MSP on the interrupt stack */
|
||||
bl up_doirq /* R0=IRQ, R1=register save area on stack */
|
||||
bl arm_doirq /* R0=IRQ, R1=register save area on stack */
|
||||
pop {r1} /* Recover R1=main stack pointer */
|
||||
#else
|
||||
msr msp, r1 /* We are using the main stack pointer */
|
||||
bl up_doirq /* R0=IRQ, R1=register save area on stack */
|
||||
bl arm_doirq /* R0=IRQ, R1=register save area on stack */
|
||||
mrs r1, msp /* Recover R1=main stack pointer */
|
||||
#endif
|
||||
|
||||
/* On return from up_doirq, r0 will hold a pointer to register context
|
||||
/* On return from arm_doirq, r0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_hardfault
|
||||
* Name: arm_hardfault
|
||||
*
|
||||
* Description:
|
||||
* This is Hard Fault exception handler. It also catches SVC call
|
||||
|
|
@ -81,7 +81,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_hardfault(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_hardfault(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
uint32_t *regs = (uint32_t *)context;
|
||||
|
||||
|
|
@ -121,7 +121,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
|
|||
if (insn == INSN_SVC0)
|
||||
{
|
||||
hfinfo("Forward SVCall\n");
|
||||
return up_svcall(irq, context, NULL);
|
||||
return arm_svcall(irq, context, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* privileged thread mode.
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
CURRENT_REGS[REG_PRIMASK] = 1;
|
||||
CURRENT_REGS[REG_XPSR] = ARMV6M_XPSR_T;
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
|
|
@ -186,7 +186,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
tcb->xcp.regs[REG_PRIMASK] = 1;
|
||||
tcb->xcp.regs[REG_XPSR] = ARMV6M_XPSR_T;
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_sigdeliver
|
||||
* Name: arm_sigdeliver
|
||||
*
|
||||
* Description:
|
||||
* This is the a signal handling trampoline. When a signal action was
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_sigdeliver(void)
|
||||
void arm_sigdeliver(void)
|
||||
{
|
||||
/* NOTE the "magic" guard space added to regs. This is a little kludge
|
||||
* because arm_fullcontextrestore (called below) will do a stack-to-stack
|
||||
|
|
|
|||
|
|
@ -109,14 +109,14 @@ static void dispatch_syscall(void)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_svcall
|
||||
* Name: arm_svcall
|
||||
*
|
||||
* Description:
|
||||
* This is SVCall exception handler that performs context switching
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_svcall(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_svcall(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
uint32_t *regs = (uint32_t *)context;
|
||||
uint32_t cmd;
|
||||
|
|
@ -223,7 +223,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
|
|||
|
||||
/* R0=SYS_syscall_return: This a syscall return command:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*
|
||||
* At this point, the following values are saved in context:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@
|
|||
#ifdef CONFIG_LIB_SYSCALL
|
||||
/* SYS call 3:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*/
|
||||
|
||||
#define SYS_syscall_return (3)
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ void arm_copyarmstate(uint32_t *dest, uint32_t *src)
|
|||
* registers at indices ARM_CONTEXT_REGS through (XCPTCONTEXT_REGS-1)
|
||||
*/
|
||||
|
||||
up_savefpu(dest);
|
||||
arm_savefpu(dest);
|
||||
|
||||
/* Then copy all of the ARM registers (omitting the floating point
|
||||
* registers). Indices: 0 through (ARM_CONTEXT_REGS-1).
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
|
|||
#ifdef CONFIG_ARCH_FPU
|
||||
/* Restore floating point registers */
|
||||
|
||||
up_restorefpu((uint32_t *)CURRENT_REGS);
|
||||
arm_restorefpu((uint32_t *)CURRENT_REGS);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_ADDRENV
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@
|
|||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
.macro showprogress, code
|
||||
mov r0, #\code
|
||||
bl up_lowputc
|
||||
bl arm_lowputc
|
||||
.endm
|
||||
#else
|
||||
.macro showprogress, code
|
||||
|
|
|
|||
|
|
@ -293,7 +293,7 @@ static void pl310_flush_all(void)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_l2ccinitialize
|
||||
* Name: arm_l2ccinitialize
|
||||
*
|
||||
* Description:
|
||||
* One time configuration of the L2 cache. The L2 cache will be enabled
|
||||
|
|
@ -308,7 +308,7 @@ static void pl310_flush_all(void)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_l2ccinitialize(void)
|
||||
void arm_l2ccinitialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
int i;
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@
|
|||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
.macro showprogress, code
|
||||
mov r0, #\code
|
||||
bl up_lowputc
|
||||
bl arm_lowputc
|
||||
.endm
|
||||
#else
|
||||
.macro showprogress, code
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_pginitialize()
|
||||
* Name: arm_pginitialize()
|
||||
*
|
||||
* Description:
|
||||
* Initialize the MMU for on-demand paging support..
|
||||
|
|
@ -72,10 +72,10 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_pginitialize(void)
|
||||
void arm_pginitialize(void)
|
||||
{
|
||||
/* None needed at present. This file is just retained in case the need
|
||||
* arises in the future. Nothing calls up_pginitialize() now. If needed,
|
||||
* arises in the future. Nothing calls arm_pginitialize() now. If needed,
|
||||
* if should be called early in arm_boot.c to assure that all paging is
|
||||
* ready.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@
|
|||
* Public Symbols
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_restorefpu
|
||||
.globl arm_restorefpu
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
|
|
@ -58,14 +58,14 @@
|
|||
.text
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_restorefpu
|
||||
* Name: arm_restorefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), restore the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_restorefpu(const uint32_t *regs);
|
||||
* void arm_restorefpu(const uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area containing the floating point
|
||||
|
|
@ -77,10 +77,10 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_restorefpu
|
||||
.type up_restorefpu, function
|
||||
.globl arm_restorefpu
|
||||
.type arm_restorefpu, function
|
||||
|
||||
up_restorefpu:
|
||||
arm_restorefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -98,6 +98,6 @@ up_restorefpu:
|
|||
vmsr fpscr, r2 /* Restore the FPCSR */
|
||||
bx lr
|
||||
|
||||
.size up_restorefpu, .-up_restorefpu
|
||||
.size arm_restorefpu, .-arm_restorefpu
|
||||
#endif /* CONFIG_ARCH_FPU */
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
* Public Symbols
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_savefpu
|
||||
.globl arm_savefpu
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
|
|
@ -62,14 +62,14 @@
|
|||
.text
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_savefpu
|
||||
* Name: arm_savefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), save the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_savefpu(uint32_t *regs);
|
||||
* void arm_savefpu(uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area in which to save the floating point
|
||||
|
|
@ -80,10 +80,10 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_savefpu
|
||||
.type up_savefpu, function
|
||||
.globl arm_savefpu
|
||||
.type arm_savefpu, function
|
||||
|
||||
up_savefpu:
|
||||
arm_savefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -101,6 +101,6 @@ up_savefpu:
|
|||
str r2, [r1], #4 /* Save the floating point control and status register */
|
||||
bx lr
|
||||
|
||||
.size up_savefpu, .-up_savefpu
|
||||
.size arm_savefpu, .-arm_savefpu
|
||||
#endif /* CONFIG_ARCH_FPU */
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* disabled
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
#ifdef CONFIG_ARM_THUMB
|
||||
CURRENT_REGS[REG_CPSR] |= PSR_T_BIT;
|
||||
|
|
@ -187,7 +187,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
#ifdef CONFIG_ARM_THUMB
|
||||
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
|
||||
|
|
@ -280,7 +280,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
#ifdef CONFIG_ARM_THUMB
|
||||
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
|
||||
|
|
@ -305,7 +305,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* privileged thread mode.
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
#ifdef CONFIG_ARM_THUMB
|
||||
CURRENT_REGS[REG_CPSR] |= PSR_T_BIT;
|
||||
|
|
@ -329,7 +329,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* involves spinlocks that are configured per the TCB irqcount
|
||||
* field. This is logically equivalent to enter_critical_section().
|
||||
* The matching call to leave_critical_section() will be
|
||||
* performed in up_sigdeliver().
|
||||
* performed in arm_sigdeliver().
|
||||
*/
|
||||
|
||||
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
|
||||
|
|
@ -371,7 +371,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
#ifdef CONFIG_ARM_THUMB
|
||||
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_sigdeliver
|
||||
* Name: arm_sigdeliver
|
||||
*
|
||||
* Description:
|
||||
* This is the a signal handling trampoline. When a signal action was
|
||||
|
|
@ -67,7 +67,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_sigdeliver(void)
|
||||
void arm_sigdeliver(void)
|
||||
{
|
||||
struct tcb_s *rtcb = this_task();
|
||||
uint32_t regs[XCPTCONTEXT_REGS];
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
|||
{
|
||||
/* R0=SYS_syscall_return: This a SYSCALL return command:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*
|
||||
* At this point, the following values are saved in context:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ extern "C"
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_l2ccinitialize
|
||||
* Name: arm_l2ccinitialize
|
||||
*
|
||||
* Description:
|
||||
* One time configuration of the L2 cache. The L2 cache will be enabled
|
||||
|
|
@ -82,7 +82,7 @@ extern "C"
|
|||
****************************************************************************/
|
||||
|
||||
#if 0 /* Prototyped in arm_internal.h */
|
||||
void up_l2ccinitialize(void);
|
||||
void arm_l2ccinitialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@
|
|||
|
||||
/* SYS call 0:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*/
|
||||
|
||||
#define SYS_syscall_return (0)
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ void arm_copyarmstate(uint32_t *dest, uint32_t *src)
|
|||
* registers at indices SW_INT_REGS through (SW_INT_REGS+SW_FPU_REGS-1)
|
||||
*/
|
||||
|
||||
up_savefpu(dest);
|
||||
arm_savefpu(dest);
|
||||
|
||||
/* Save the block of ARM registers that were saved by the interrupt
|
||||
* handling logic. Indices: 0 through (SW_INT_REGS-1).
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t *up_doirq(int irq, uint32_t *regs)
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
{
|
||||
board_autoled_on(LED_INIRQ);
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
|
@ -64,7 +64,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
|
|||
|
||||
/* Acknowledge the interrupt */
|
||||
|
||||
up_ack_irq(irq);
|
||||
arm_ack_irq(irq);
|
||||
|
||||
/* Deliver the IRQ */
|
||||
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_hardfault
|
||||
* Name: arm_hardfault
|
||||
*
|
||||
* Description:
|
||||
* This is Hard Fault exception handler. It also catches SVC call
|
||||
|
|
@ -71,7 +71,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_hardfault(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_hardfault(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
/* Get the value of the program counter where the fault occurred */
|
||||
|
||||
|
|
@ -112,7 +112,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
|
|||
if (insn == INSN_SVC0)
|
||||
{
|
||||
hfinfo("Forward SVCall\n");
|
||||
return up_svcall(irq, context, arg);
|
||||
return arm_svcall(irq, context, arg);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_memfault
|
||||
* Name: arm_memfault
|
||||
*
|
||||
* Description:
|
||||
* This is Memory Management Fault exception handler. Normally we get
|
||||
|
|
@ -60,7 +60,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_memfault(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_memfault(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
/* Dump some memory management fault info */
|
||||
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* privileged thread mode.
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -191,7 +191,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -299,7 +299,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* to be here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -337,7 +337,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* privileged thread mode.
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -367,7 +367,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* field. This is logically equivalent to
|
||||
* enter_critical_section(). The matching call to
|
||||
* leave_critical_section() will be performed in
|
||||
* up_sigdeliver().
|
||||
* arm_sigdeliver().
|
||||
*/
|
||||
|
||||
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
|
||||
|
|
@ -417,7 +417,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_sigdeliver
|
||||
* Name: arm_sigdeliver
|
||||
*
|
||||
* Description:
|
||||
* This is the a signal handling trampoline. When a signal action was
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_sigdeliver(void)
|
||||
void arm_sigdeliver(void)
|
||||
{
|
||||
struct tcb_s *rtcb = this_task();
|
||||
uint32_t regs[XCPTCONTEXT_REGS];
|
||||
|
|
|
|||
|
|
@ -117,14 +117,14 @@ static void dispatch_syscall(void)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_svcall
|
||||
* Name: arm_svcall
|
||||
*
|
||||
* Description:
|
||||
* This is SVCall exception handler that performs context switching
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_svcall(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_svcall(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
uint32_t *regs = (uint32_t *)context;
|
||||
uint32_t cmd;
|
||||
|
|
@ -179,7 +179,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
|
|||
DEBUGASSERT(regs[REG_R1] != 0);
|
||||
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
|
||||
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
|
||||
up_savefpu((uint32_t *)regs[REG_R1]);
|
||||
arm_savefpu((uint32_t *)regs[REG_R1]);
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
|
|
@ -229,7 +229,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
|
|||
DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0);
|
||||
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
|
||||
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
|
||||
up_savefpu((uint32_t *)regs[REG_R1]);
|
||||
arm_savefpu((uint32_t *)regs[REG_R1]);
|
||||
#endif
|
||||
CURRENT_REGS = (uint32_t *)regs[REG_R2];
|
||||
}
|
||||
|
|
@ -237,7 +237,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
|
|||
|
||||
/* R0=SYS_syscall_return: This a syscall return command:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*
|
||||
* At this point, the following values are saved in context:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ exception_common:
|
|||
/* Save the non-volatile FP registers here.
|
||||
*
|
||||
* This routine is the only point where we can save these registers; either before
|
||||
* or after calling up_doirq. The compiler is free to use them at any time as long
|
||||
* or after calling arm_doirq. The compiler is free to use them at any time as long
|
||||
* as they are restored before returning, so we can't assume that we can get at the
|
||||
* true values of these registers in any routine called from here.
|
||||
*
|
||||
|
|
@ -179,7 +179,7 @@ exception_common:
|
|||
|
||||
stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP/PRIMASK values */
|
||||
|
||||
/* There are two arguments to up_doirq:
|
||||
/* There are two arguments to arm_doirq:
|
||||
*
|
||||
* R0 = The IRQ number
|
||||
* R1 = The top of the stack points to the saved state
|
||||
|
|
@ -210,10 +210,10 @@ exception_common:
|
|||
|
||||
#endif
|
||||
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
bl arm_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, r4 /* Recover R1=main stack pointer */
|
||||
|
||||
/* On return from up_doirq, R0 will hold a pointer to register context
|
||||
/* On return from arm_doirq, R0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -41,8 +41,8 @@
|
|||
* Public Symbols
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_savefpu
|
||||
.globl up_restorefpu
|
||||
.globl arm_savefpu
|
||||
.globl arm_restorefpu
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
|
@ -53,14 +53,14 @@
|
|||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_savefpu
|
||||
* Name: arm_savefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), save the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_savefpu(uint32_t *regs);
|
||||
* void arm_savefpu(uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area in which to save the floating point
|
||||
|
|
@ -72,8 +72,8 @@
|
|||
************************************************************************************/
|
||||
|
||||
.thumb_func
|
||||
.type up_savefpu, function
|
||||
up_savefpu:
|
||||
.type arm_savefpu, function
|
||||
arm_savefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -155,17 +155,17 @@ up_savefpu:
|
|||
#endif
|
||||
bx lr
|
||||
|
||||
.size up_savefpu, .-up_savefpu
|
||||
.size arm_savefpu, .-arm_savefpu
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_restorefpu
|
||||
* Name: arm_restorefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), restore the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_restorefpu(const uint32_t *regs);
|
||||
* void arm_restorefpu(const uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area containing the floating point
|
||||
|
|
@ -178,8 +178,8 @@ up_savefpu:
|
|||
************************************************************************************/
|
||||
|
||||
.thumb_func
|
||||
.type up_restorefpu, function
|
||||
up_restorefpu:
|
||||
.type arm_restorefpu, function
|
||||
arm_restorefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -265,6 +265,6 @@ up_restorefpu:
|
|||
#endif
|
||||
bx lr
|
||||
|
||||
.size up_restorefpu, .-up_restorefpu
|
||||
.size arm_restorefpu, .-arm_restorefpu
|
||||
#endif /* CONFIG_ARCH_FPU */
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ exception_common:
|
|||
stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */
|
||||
#endif
|
||||
|
||||
/* There are two arguments to up_doirq:
|
||||
/* There are two arguments to arm_doirq:
|
||||
*
|
||||
* R0 = The IRQ number
|
||||
* R1 = The top of the stack points to the saved state
|
||||
|
|
@ -205,10 +205,10 @@ exception_common:
|
|||
|
||||
#endif
|
||||
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
bl arm_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, r4 /* Recover R1=main stack pointer */
|
||||
|
||||
/* On return from up_doirq, R0 will hold a pointer to register context
|
||||
/* On return from arm_doirq, R0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
|
@ -227,12 +227,12 @@ exception_common:
|
|||
* Here:
|
||||
* r0 = Address of the register save area
|
||||
*
|
||||
* NOTE: It is a requirement that up_restorefpu() preserve the value of
|
||||
* NOTE: It is a requirement that arm_restorefpu() preserve the value of
|
||||
* r0!
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
bl up_restorefpu /* Restore the FPU registers */
|
||||
bl arm_restorefpu /* Restore the FPU registers */
|
||||
#endif
|
||||
|
||||
/* We are returning with a pending context switch. This case is different
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@
|
|||
#ifdef CONFIG_LIB_SYSCALL
|
||||
/* SYS call 3:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*/
|
||||
|
||||
#define SYS_syscall_return (3)
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ void arm_copyarmstate(uint32_t *dest, uint32_t *src)
|
|||
* registers at indices ARM_CONTEXT_REGS through (XCPTCONTEXT_REGS-1)
|
||||
*/
|
||||
|
||||
up_savefpu(dest);
|
||||
arm_savefpu(dest);
|
||||
|
||||
/* Then copy all of the ARM registers (omitting the floating point
|
||||
* registers). Indices: 0 through (ARM_CONTEXT_REGS-1).
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
|
|||
{
|
||||
/* Restore floating point registers */
|
||||
|
||||
up_restorefpu((uint32_t *)CURRENT_REGS);
|
||||
arm_restorefpu((uint32_t *)CURRENT_REGS);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -293,7 +293,7 @@ static void pl310_flush_all(void)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_l2ccinitialize
|
||||
* Name: arm_l2ccinitialize
|
||||
*
|
||||
* Description:
|
||||
* One time configuration of the L2 cache. The L2 cache will be enabled
|
||||
|
|
@ -308,7 +308,7 @@ static void pl310_flush_all(void)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_l2ccinitialize(void)
|
||||
void arm_l2ccinitialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
int i;
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
* Public Symbols
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_restorefpu
|
||||
.globl arm_restorefpu
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
.cpu cortex-r4f
|
||||
|
|
@ -64,14 +64,14 @@
|
|||
.text
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_restorefpu
|
||||
* Name: arm_restorefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), restore the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_restorefpu(const uint32_t *regs);
|
||||
* void arm_restorefpu(const uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area containing the floating point
|
||||
|
|
@ -83,10 +83,10 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_restorefpu
|
||||
.type up_restorefpu, function
|
||||
.globl arm_restorefpu
|
||||
.type arm_restorefpu, function
|
||||
|
||||
up_restorefpu:
|
||||
arm_restorefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -104,6 +104,6 @@ up_restorefpu:
|
|||
vmsr fpscr, r2 /* Restore the FPCSR */
|
||||
bx lr
|
||||
|
||||
.size up_restorefpu, .-up_restorefpu
|
||||
.size arm_restorefpu, .-arm_restorefpu
|
||||
#endif /* CONFIG_ARCH_FPU */
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
* Public Symbols
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_savefpu
|
||||
.globl arm_savefpu
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
|
|
@ -62,14 +62,14 @@
|
|||
.text
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_savefpu
|
||||
* Name: arm_savefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), save the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_savefpu(uint32_t *regs);
|
||||
* void arm_savefpu(uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area in which to save the floating point
|
||||
|
|
@ -80,10 +80,10 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_savefpu
|
||||
.type up_savefpu, function
|
||||
.globl arm_savefpu
|
||||
.type arm_savefpu, function
|
||||
|
||||
up_savefpu:
|
||||
arm_savefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -101,6 +101,6 @@ up_savefpu:
|
|||
str r2, [r1], #4 /* Save the floating point control and status register */
|
||||
bx lr
|
||||
|
||||
.size up_savefpu, .-up_savefpu
|
||||
.size arm_savefpu, .-arm_savefpu
|
||||
#endif /* CONFIG_ARCH_FPU */
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* disabled
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
|
||||
#ifdef CONFIG_ENDIAN_BIG
|
||||
|
|
@ -183,7 +183,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
|
||||
#ifdef CONFIG_ENDIAN_BIG
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_sigdeliver
|
||||
* Name: arm_sigdeliver
|
||||
*
|
||||
* Description:
|
||||
* This is the a signal handling trampoline. When a signal action was
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_sigdeliver(void)
|
||||
void arm_sigdeliver(void)
|
||||
{
|
||||
struct tcb_s *rtcb = this_task();
|
||||
uint32_t regs[XCPTCONTEXT_REGS];
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
|||
{
|
||||
/* R0=SYS_syscall_return: This a SYSCALL return command:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*
|
||||
* At this point, the following values are saved in context:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ extern "C"
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_l2ccinitialize
|
||||
* Name: arm_l2ccinitialize
|
||||
*
|
||||
* Description:
|
||||
* One time configuration of the L2 cache. The L2 cache will be enabled
|
||||
|
|
@ -82,7 +82,7 @@ extern "C"
|
|||
****************************************************************************/
|
||||
|
||||
#if 0 /* Prototyped in arm_internal.h */
|
||||
void up_l2ccinitialize(void);
|
||||
void arm_l2ccinitialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@
|
|||
|
||||
/* SYS call 0:
|
||||
*
|
||||
* void up_syscall_return(void);
|
||||
* void arm_syscall_return(void);
|
||||
*/
|
||||
|
||||
#define SYS_syscall_return (0)
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ void arm_copyarmstate(uint32_t *dest, uint32_t *src)
|
|||
* registers at indices SW_INT_REGS through (SW_INT_REGS+SW_FPU_REGS-1)
|
||||
*/
|
||||
|
||||
up_savefpu(dest);
|
||||
arm_savefpu(dest);
|
||||
|
||||
/* Save the block of ARM registers that were saved by the interrupt
|
||||
* handling logic. Indices: 0 through (SW_INT_REGS-1).
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t *up_doirq(int irq, uint32_t *regs)
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
{
|
||||
board_autoled_on(LED_INIRQ);
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
|
@ -64,7 +64,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
|
|||
|
||||
/* Acknowledge the interrupt */
|
||||
|
||||
up_ack_irq(irq);
|
||||
arm_ack_irq(irq);
|
||||
|
||||
/* Deliver the IRQ */
|
||||
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ exception_common:
|
|||
/* Save the non-volatile FP registers here.
|
||||
*
|
||||
* This routine is the only point where we can save these registers; either before
|
||||
* or after calling up_doirq. The compiler is free to use them at any time as long
|
||||
* or after calling arm_doirq. The compiler is free to use them at any time as long
|
||||
* as they are restored before returning, so we can't assume that we can get at the
|
||||
* true values of these registers in any routine called from here.
|
||||
*
|
||||
|
|
@ -179,7 +179,7 @@ exception_common:
|
|||
|
||||
stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP/PRIMASK values */
|
||||
|
||||
/* There are two arguments to up_doirq:
|
||||
/* There are two arguments to arm_doirq:
|
||||
*
|
||||
* R0 = The IRQ number
|
||||
* R1 = The top of the stack points to the saved state
|
||||
|
|
@ -210,10 +210,10 @@ exception_common:
|
|||
|
||||
#endif
|
||||
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
bl arm_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, r4 /* Recover R1=main stack pointer */
|
||||
|
||||
/* On return from up_doirq, R0 will hold a pointer to register context
|
||||
/* On return from arm_doirq, R0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -41,8 +41,8 @@
|
|||
* Public Symbols
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_savefpu
|
||||
.globl up_restorefpu
|
||||
.globl arm_savefpu
|
||||
.globl arm_restorefpu
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
|
@ -53,14 +53,14 @@
|
|||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_savefpu
|
||||
* Name: arm_savefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), save the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_savefpu(uint32_t *regs);
|
||||
* void arm_savefpu(uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area in which to save the floating point
|
||||
|
|
@ -72,8 +72,8 @@
|
|||
************************************************************************************/
|
||||
|
||||
.thumb_func
|
||||
.type up_savefpu, function
|
||||
up_savefpu:
|
||||
.type arm_savefpu, function
|
||||
arm_savefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -155,17 +155,17 @@ up_savefpu:
|
|||
#endif
|
||||
bx lr
|
||||
|
||||
.size up_savefpu, .-up_savefpu
|
||||
.size arm_savefpu, .-arm_savefpu
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_restorefpu
|
||||
* Name: arm_restorefpu
|
||||
*
|
||||
* Description:
|
||||
* Given the pointer to a register save area (in R0), restore the state of the
|
||||
* floating point registers.
|
||||
*
|
||||
* C Function Prototype:
|
||||
* void up_restorefpu(const uint32_t *regs);
|
||||
* void arm_restorefpu(const uint32_t *regs);
|
||||
*
|
||||
* Input Parameters:
|
||||
* regs - A pointer to the register save area containing the floating point
|
||||
|
|
@ -178,8 +178,8 @@ up_savefpu:
|
|||
************************************************************************************/
|
||||
|
||||
.thumb_func
|
||||
.type up_restorefpu, function
|
||||
up_restorefpu:
|
||||
.type arm_restorefpu, function
|
||||
arm_restorefpu:
|
||||
|
||||
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
|
||||
|
||||
|
|
@ -265,6 +265,6 @@ up_restorefpu:
|
|||
#endif
|
||||
bx lr
|
||||
|
||||
.size up_restorefpu, .-up_restorefpu
|
||||
.size arm_restorefpu, .-arm_restorefpu
|
||||
#endif /* CONFIG_ARCH_FPU */
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_hardfault
|
||||
* Name: arm_hardfault
|
||||
*
|
||||
* Description:
|
||||
* This is Hard Fault exception handler. It also catches SVC call
|
||||
|
|
@ -71,7 +71,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_hardfault(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_hardfault(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
/* Get the value of the program counter where the fault occurred */
|
||||
|
||||
|
|
@ -112,7 +112,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
|
|||
if (insn == INSN_SVC0)
|
||||
{
|
||||
hfinfo("Forward SVCall\n");
|
||||
return up_svcall(irq, context, arg);
|
||||
return arm_svcall(irq, context, arg);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ exception_common:
|
|||
stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */
|
||||
#endif
|
||||
|
||||
/* There are two arguments to up_doirq:
|
||||
/* There are two arguments to arm_doirq:
|
||||
*
|
||||
* R0 = The IRQ number
|
||||
* R1 = The top of the stack points to the saved state
|
||||
|
|
@ -205,10 +205,10 @@ exception_common:
|
|||
|
||||
#endif
|
||||
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
bl arm_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, r4 /* Recover R1=main stack pointer */
|
||||
|
||||
/* On return from up_doirq, R0 will hold a pointer to register context
|
||||
/* On return from arm_doirq, R0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
|
@ -227,12 +227,12 @@ exception_common:
|
|||
* Here:
|
||||
* r0 = Address of the register save area
|
||||
*
|
||||
* NOTE: It is a requirement that up_restorefpu() preserve the value of
|
||||
* NOTE: It is a requirement that arm_restorefpu() preserve the value of
|
||||
* r0!
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
bl up_restorefpu /* Restore the FPU registers */
|
||||
bl arm_restorefpu /* Restore the FPU registers */
|
||||
#endif
|
||||
|
||||
/* We are returning with a pending context switch. This case is different
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_memfault
|
||||
* Name: arm_memfault
|
||||
*
|
||||
* Description:
|
||||
* This is Memory Management Fault exception handler. Normally we get
|
||||
|
|
@ -60,7 +60,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_memfault(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_memfault(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
/* Dump some memory management fault info */
|
||||
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* privileged thread mode.
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -191,7 +191,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -299,7 +299,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* to be here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -337,7 +337,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* privileged thread mode.
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
@ -367,7 +367,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* field. This is logically equivalent to
|
||||
* enter_critical_section(). The matching call to
|
||||
* leave_critical_section() will be performed in
|
||||
* up_sigdeliver().
|
||||
* arm_sigdeliver().
|
||||
*/
|
||||
|
||||
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
|
||||
|
|
@ -417,7 +417,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
|||
* here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_sigdeliver
|
||||
* Name: arm_sigdeliver
|
||||
*
|
||||
* Description:
|
||||
* This is the a signal handling trampoline. When a signal action was
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_sigdeliver(void)
|
||||
void arm_sigdeliver(void)
|
||||
{
|
||||
struct tcb_s *rtcb = this_task();
|
||||
uint32_t regs[XCPTCONTEXT_REGS];
|
||||
|
|
|
|||
|
|
@ -117,14 +117,14 @@ static void dispatch_syscall(void)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_svcall
|
||||
* Name: arm_svcall
|
||||
*
|
||||
* Description:
|
||||
* This is SVCall exception handler that performs context switching
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_svcall(int irq, FAR void *context, FAR void *arg)
|
||||
int arm_svcall(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
uint32_t *regs = (uint32_t *)context;
|
||||
uint32_t cmd;
|
||||
|
|
@ -179,7 +179,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
|
|||
DEBUGASSERT(regs[REG_R1] != 0);
|
||||
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
|
||||
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV8M_LAZYFPU)
|
||||
up_savefpu((uint32_t *)regs[REG_R1]);
|
||||
arm_savefpu((uint32_t *)regs[REG_R1]);
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
|
|
@ -229,7 +229,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
|
|||
DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0);
|
||||
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
|
||||
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV8M_LAZYFPU)
|
||||
up_savefpu((uint32_t *)regs[REG_R1]);
|
||||
arm_savefpu((uint32_t *)regs[REG_R1]);
|
||||
#endif
|
||||
CURRENT_REGS = (uint32_t *)regs[REG_R2];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2426,7 +2426,7 @@ static void c5471_macassign(struct c5471_driver_s *priv)
|
|||
|
||||
/* Initialize the DM90x0 chip and driver */
|
||||
|
||||
void up_netinitialize(void)
|
||||
void arm_netinitialize(void)
|
||||
{
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
|
|
|
|||
|
|
@ -84,13 +84,13 @@ extern int _svectors; /* Type does not matter */
|
|||
static up_vector_t g_vectorinittab[] =
|
||||
{
|
||||
(up_vector_t)NULL,
|
||||
up_vectorundefinsn,
|
||||
up_vectorswi,
|
||||
up_vectorprefetch,
|
||||
up_vectordata,
|
||||
up_vectoraddrexcptn,
|
||||
up_vectorirq,
|
||||
up_vectorfiq
|
||||
arm_vectorundefinsn,
|
||||
arm_vectorswi,
|
||||
arm_vectorprefetch,
|
||||
arm_vectordata,
|
||||
arm_vectoraddrexcptn,
|
||||
arm_vectorirq,
|
||||
arm_vectorfiq
|
||||
};
|
||||
#define NVECTORS ((sizeof(g_vectorinittab)) / sizeof(up_vector_t))
|
||||
|
||||
|
|
@ -224,14 +224,14 @@ void up_enable_irq(int irq)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the interrupt
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_ack_irq(int irq)
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@
|
|||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_lowputc
|
||||
* Name: arm_lowputc
|
||||
**************************************************************************/
|
||||
|
||||
/* This assembly language version has the advantage that it can does not
|
||||
|
|
@ -81,9 +81,9 @@
|
|||
*/
|
||||
|
||||
.text
|
||||
.global up_lowputc
|
||||
.type up_lowputc, function
|
||||
up_lowputc:
|
||||
.global arm_lowputc
|
||||
.type arm_lowputc, function
|
||||
arm_lowputc:
|
||||
/* On entry, r0 holds the character to be printed */
|
||||
|
||||
#ifdef CONFIG_SERIAL_IRDA_CONSOLE
|
||||
|
|
|
|||
|
|
@ -795,16 +795,16 @@ static bool up_txempty(struct uart_dev_s *dev)
|
|||
#ifdef USE_EARLYSERIALINIT
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_serialinit
|
||||
* Name: arm_serialinit
|
||||
*
|
||||
* Description:
|
||||
* Performs the low level UART initialization early in
|
||||
* debug so that the serial console will be available
|
||||
* during bootup. This must be called before up_serialinit.
|
||||
* during bootup. This must be called before arm_serialinit.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_earlyserialinit(void)
|
||||
void arm_earlyserialinit(void)
|
||||
{
|
||||
up_disableuartint(TTYS0_DEV.priv, NULL);
|
||||
up_disableuartint(TTYS1_DEV.priv, NULL);
|
||||
|
|
@ -815,15 +815,15 @@ void up_earlyserialinit(void)
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_serialinit
|
||||
* Name: arm_serialinit
|
||||
*
|
||||
* Description:
|
||||
* Register serial console and serial ports. This assumes
|
||||
* that up_earlyserialinit was called previously.
|
||||
* that arm_earlyserialinit was called previously.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_serialinit(void)
|
||||
void arm_serialinit(void)
|
||||
{
|
||||
uart_register("/dev/console", &CONSOLE_DEV);
|
||||
uart_register("/dev/ttyS0", &TTYS0_DEV);
|
||||
|
|
|
|||
|
|
@ -80,16 +80,16 @@ g_aborttmp:
|
|||
.text
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorirq
|
||||
* Name: arm_vectorirq
|
||||
*
|
||||
* Description:
|
||||
* Interrupt exception. Entered in IRQ mode with spsr = SVC
|
||||
* CPSR, lr = SVC PC
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorirq
|
||||
.type up_vectorirq, %function
|
||||
up_vectorirq:
|
||||
.globl arm_vectorirq
|
||||
.type arm_vectorirq, %function
|
||||
arm_vectorirq:
|
||||
/* On entry, we are in IRQ mode. We are free to use
|
||||
* the IRQ mode r13 and r14.
|
||||
*
|
||||
|
|
@ -163,10 +163,10 @@ up_vectorirq:
|
|||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
ldr sp, .Lirqstackbase /* SP = interrupt stack base */
|
||||
str r1, [sp] /* Save the user stack pointer */
|
||||
bl up_doirq /* Call the handler */
|
||||
bl arm_doirq /* Call the handler */
|
||||
ldr sp, [sp] /* Restore the user stack pointer */
|
||||
#else
|
||||
bl up_doirq /* Call the handler */
|
||||
bl arm_doirq /* Call the handler */
|
||||
#endif
|
||||
|
||||
/* Restore the CPSR, SVC modr registers and return */
|
||||
|
|
@ -184,15 +184,15 @@ up_vectorirq:
|
|||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Function: up_vectorswi
|
||||
* Function: arm_vectorswi
|
||||
*
|
||||
* Description:
|
||||
* SWI interrupt. We enter the SWI in SVC mode
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorswi
|
||||
.type up_vectorswi, %function
|
||||
up_vectorswi:
|
||||
.globl arm_vectorswi
|
||||
.type arm_vectorswi, %function
|
||||
arm_vectorswi:
|
||||
|
||||
/* The c547x rrload bootloader intemediates all
|
||||
* interrupts. For the* case of the SWI, it mucked
|
||||
|
|
@ -221,12 +221,12 @@ up_vectorswi:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the SWI handler with interrupt disabled.
|
||||
* void up_syscall(struct xcptcontext *xcp)
|
||||
* void arm_syscall(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_syscall /* Call the handler */
|
||||
bl arm_syscall /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC modr registers and return */
|
||||
|
||||
|
|
@ -237,7 +237,7 @@ up_vectorswi:
|
|||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectordata
|
||||
* Name: arm_vectordata
|
||||
*
|
||||
* Description:
|
||||
* Data abort Exception dispatcher. Give control to data
|
||||
|
|
@ -246,9 +246,9 @@ up_vectorswi:
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectordata
|
||||
.type up_vectordata, %function
|
||||
up_vectordata:
|
||||
.globl arm_vectordata
|
||||
.type arm_vectordata, %function
|
||||
arm_vectordata:
|
||||
/* On entry we are free to use the ABORT mode registers
|
||||
* r13 and r14
|
||||
*/
|
||||
|
|
@ -286,12 +286,12 @@ up_vectordata:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the data abort handler with interrupt disabled.
|
||||
* void up_dataabort(struct xcptcontext *xcp)
|
||||
* void arm_dataabort(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_dataabort /* Call the handler */
|
||||
bl arm_dataabort /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC modr registers and return */
|
||||
|
||||
|
|
@ -305,16 +305,16 @@ up_vectordata:
|
|||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorprefetch
|
||||
* Name: arm_vectorprefetch
|
||||
*
|
||||
* Description:
|
||||
* Prefetch abort exception. Entered in ABT mode with
|
||||
* spsr = SVC CPSR, lr = SVC PC
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorprefetch
|
||||
.type up_vectorprefetch, %function
|
||||
up_vectorprefetch:
|
||||
.globl arm_vectorprefetch
|
||||
.type arm_vectorprefetch, %function
|
||||
arm_vectorprefetch:
|
||||
/* On entry we are free to use the ABORT mode registers
|
||||
* r13 and r14
|
||||
*/
|
||||
|
|
@ -352,12 +352,12 @@ up_vectorprefetch:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the prefetch abort handler with interrupt disabled.
|
||||
* void up_prefetchabort(struct xcptcontext *xcp)
|
||||
* void arm_prefetchabort(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_prefetchabort /* Call the handler */
|
||||
bl arm_prefetchabort /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC modr registers and return */
|
||||
|
||||
|
|
@ -371,7 +371,7 @@ up_vectorprefetch:
|
|||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorundefinsn
|
||||
* Name: arm_vectorundefinsn
|
||||
*
|
||||
* Description:
|
||||
* Undefined instruction entry exception. Entered in
|
||||
|
|
@ -379,9 +379,9 @@ up_vectorprefetch:
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorundefinsn
|
||||
.type up_vectorundefinsn, %function
|
||||
up_vectorundefinsn:
|
||||
.globl arm_vectorundefinsn
|
||||
.type arm_vectorundefinsn, %function
|
||||
arm_vectorundefinsn:
|
||||
/* On entry we are free to use the UND mode registers
|
||||
* r13 and r14
|
||||
*/
|
||||
|
|
@ -418,12 +418,12 @@ up_vectorundefinsn:
|
|||
stmia r0, {r1-r4}
|
||||
|
||||
/* Then call the undef insn handler with interrupt disabled.
|
||||
* void up_undefinedinsn(struct xcptcontext *xcp)
|
||||
* void arm_undefinedinsn(struct xcptcontext *xcp)
|
||||
*/
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
bl up_undefinedinsn /* Call the handler */
|
||||
bl arm_undefinedinsn /* Call the handler */
|
||||
|
||||
/* Restore the CPSR, SVC modr registers and return */
|
||||
|
||||
|
|
@ -437,15 +437,15 @@ up_vectorundefinsn:
|
|||
.align 5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_vectorfiq
|
||||
* Name: arm_vectorfiq
|
||||
*
|
||||
* Description:
|
||||
* Shouldn't happen
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectorfiq
|
||||
.type up_vectorfiq, %function
|
||||
up_vectorfiq:
|
||||
.globl arm_vectorfiq
|
||||
.type arm_vectorfiq, %function
|
||||
arm_vectorfiq:
|
||||
subs pc, lr, #4
|
||||
|
||||
/************************************************************************************
|
||||
|
|
@ -456,10 +456,10 @@ up_vectorfiq:
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
.globl up_vectoraddrexcptn
|
||||
.type up_vectoraddrexcptn, %function
|
||||
up_vectoraddrexcptn:
|
||||
b up_vectoraddrexcptn
|
||||
.globl arm_vectoraddrexcptn
|
||||
.type arm_vectoraddrexcptn, %function
|
||||
arm_vectoraddrexcptn:
|
||||
b arm_vectoraddrexcptn
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc/g_intstackbase
|
||||
|
|
|
|||
|
|
@ -354,10 +354,10 @@ static int wdt_close(struct file *filep)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_wdtinit
|
||||
* Name: arm_wdtinit
|
||||
****************************************************************************/
|
||||
|
||||
int up_wdtinit(void)
|
||||
int arm_wdtinit(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -237,7 +237,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
|
|||
sizeof(struct tls_info_s);
|
||||
stack_size = tcb->adj_stack_size -
|
||||
sizeof(struct tls_info_s);
|
||||
up_stack_color((FAR void *)stack_base, stack_size);
|
||||
arm_stack_color((FAR void *)stack_base, stack_size);
|
||||
|
||||
#endif /* CONFIG_STACK_COLORATION */
|
||||
#else /* CONFIG_TLS */
|
||||
|
|
@ -247,7 +247,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
|
|||
* water marks.
|
||||
*/
|
||||
|
||||
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
|
||||
arm_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
|
||||
|
||||
#endif /* CONFIG_STACK_COLORATION */
|
||||
#endif /* CONFIG_TLS */
|
||||
|
|
@ -260,7 +260,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_stack_color
|
||||
* Name: arm_stack_color
|
||||
*
|
||||
* Description:
|
||||
* Write a well know value into the stack
|
||||
|
|
@ -268,7 +268,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
|
|||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STACK_COLORATION
|
||||
void up_stack_color(FAR void *stackbase, size_t nbytes)
|
||||
void arm_stack_color(FAR void *stackbase, size_t nbytes)
|
||||
{
|
||||
/* Take extra care that we do not write outsize the stack boundaries */
|
||||
|
||||
|
|
|
|||
|
|
@ -46,25 +46,25 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_netinitialize (stub)
|
||||
* Name: arm_netinitialize (stub)
|
||||
*
|
||||
* Description:
|
||||
* This is a stub version os up_netinitialize. Normally, up_netinitialize
|
||||
* This is a stub version os arm_netinitialize. Normally, arm_netinitialize
|
||||
* is defined in board/xyz_network.c for board-specific Ethernet
|
||||
* implementations, or chip/xyx_ethernet.c for chip-specific Ethernet
|
||||
* implementations. The stub version here is used in the corner case where
|
||||
* the network is enable yet there is no Ethernet driver to be initialized.
|
||||
* In this case, up_initialize will still try to call up_netinitialize()
|
||||
* In this case, up_initialize will still try to call arm_netinitialize()
|
||||
* when one does not exist. This corner case would occur if, for example,
|
||||
* only a USB network interface is being used or perhaps if a SLIP is
|
||||
* being used).
|
||||
*
|
||||
* Use of this stub is deprecated. The preferred mechanism is to use
|
||||
* CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in
|
||||
* CONFIG_NETDEV_LATEINIT=y to suppress the call to arm_netinitialize() in
|
||||
* up_initialize(). Then this stub would not be needed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_netinitialize(void)
|
||||
void arm_netinitialize(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ void up_initialize(void)
|
|||
|
||||
/* Add any extra memory fragments to the memory manager */
|
||||
|
||||
up_addregion();
|
||||
arm_addregion();
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
/* Initialize the power management subsystem. This MCU-specific function
|
||||
|
|
@ -121,19 +121,19 @@ void up_initialize(void)
|
|||
* with the power management subsystem).
|
||||
*/
|
||||
|
||||
up_pminitialize();
|
||||
arm_pminitialize();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_DMA
|
||||
/* Initialize the DMA subsystem if the weak function up_dma_initialize has
|
||||
/* Initialize the DMA subsystem if the weak function arm_dma_initialize has
|
||||
* been brought into the build
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
|
||||
if (up_dma_initialize)
|
||||
if (arm_dma_initialize)
|
||||
#endif
|
||||
{
|
||||
up_dma_initialize();
|
||||
arm_dma_initialize();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -167,7 +167,7 @@ void up_initialize(void)
|
|||
/* Initialize the serial device driver */
|
||||
|
||||
#ifdef USE_SERIALDRIVER
|
||||
up_serialinit();
|
||||
arm_serialinit();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RPMSG_UART
|
||||
|
|
@ -203,7 +203,7 @@ void up_initialize(void)
|
|||
#ifndef CONFIG_NETDEV_LATEINIT
|
||||
/* Initialize the network */
|
||||
|
||||
up_netinitialize();
|
||||
arm_netinitialize();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NET_LOOPBACK
|
||||
|
|
@ -227,11 +227,11 @@ void up_initialize(void)
|
|||
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
|
||||
/* Initialize USB -- device and/or host */
|
||||
|
||||
up_usbinitialize();
|
||||
arm_usbinitialize();
|
||||
#endif
|
||||
|
||||
/* Initialize the L2 cache if present and selected */
|
||||
|
||||
up_l2ccinitialize();
|
||||
arm_l2ccinitialize();
|
||||
board_autoled_on(LED_IRQSENABLED);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -298,21 +298,21 @@ void arm_copyfullstate(uint32_t *dest, uint32_t *src);
|
|||
#ifdef CONFIG_ARCH_FPU
|
||||
void arm_copyarmstate(uint32_t *dest, uint32_t *src);
|
||||
#endif
|
||||
void up_decodeirq(uint32_t *regs);
|
||||
uint32_t *arm_decodeirq(uint32_t *regs);
|
||||
int arm_saveusercontext(uint32_t *saveregs);
|
||||
void arm_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
|
||||
void arm_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
|
||||
|
||||
/* Signal handling **********************************************************/
|
||||
|
||||
void up_sigdeliver(void);
|
||||
void arm_sigdeliver(void);
|
||||
|
||||
/* Power management *********************************************************/
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
void up_pminitialize(void);
|
||||
void arm_pminitialize(void);
|
||||
#else
|
||||
# define up_pminitialize()
|
||||
# define arm_pminitialize()
|
||||
#endif
|
||||
|
||||
/* Interrupt handling *******************************************************/
|
||||
|
|
@ -324,17 +324,17 @@ void up_pminitialize(void);
|
|||
|
||||
/* Interrupt acknowledge and dispatch */
|
||||
|
||||
void up_ack_irq(int irq);
|
||||
uint32_t *up_doirq(int irq, uint32_t *regs);
|
||||
void arm_ack_irq(int irq);
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs);
|
||||
|
||||
/* Exception Handlers */
|
||||
|
||||
int up_svcall(int irq, FAR void *context, FAR void *arg);
|
||||
int up_hardfault(int irq, FAR void *context, FAR void *arg);
|
||||
int arm_svcall(int irq, FAR void *context, FAR void *arg);
|
||||
int arm_hardfault(int irq, FAR void *context, FAR void *arg);
|
||||
|
||||
# if defined(CONFIG_ARCH_ARMV7M) || defined(CONFIG_ARCH_ARMV8M)
|
||||
|
||||
int up_memfault(int irq, FAR void *context, FAR void *arg);
|
||||
int arm_memfault(int irq, FAR void *context, FAR void *arg);
|
||||
|
||||
# endif /* CONFIG_ARCH_CORTEXM3,4,7 */
|
||||
|
||||
|
|
@ -354,7 +354,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs);
|
|||
void arm_pginitialize(void);
|
||||
uint32_t *arm_va2pte(uintptr_t vaddr);
|
||||
#else /* CONFIG_PAGING */
|
||||
# define up_pginitialize()
|
||||
# define arm_pginitialize()
|
||||
#endif /* CONFIG_PAGING */
|
||||
|
||||
/* Exception Handlers */
|
||||
|
|
@ -370,58 +370,58 @@ uint32_t *arm_undefinedinsn(uint32_t *regs);
|
|||
|
||||
/* Interrupt acknowledge and dispatch */
|
||||
|
||||
void up_ack_irq(int irq);
|
||||
void up_doirq(int irq, uint32_t *regs);
|
||||
void arm_ack_irq(int irq);
|
||||
void arm_doirq(int irq, uint32_t *regs);
|
||||
|
||||
/* Paging support (and exception handlers) */
|
||||
|
||||
#ifdef CONFIG_PAGING
|
||||
void up_pginitialize(void);
|
||||
uint32_t *up_va2pte(uintptr_t vaddr);
|
||||
void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
|
||||
void arm_pginitialize(void);
|
||||
uint32_t *arm_va2pte(uintptr_t vaddr);
|
||||
void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
|
||||
#else /* CONFIG_PAGING */
|
||||
# define up_pginitialize()
|
||||
void up_dataabort(uint32_t *regs);
|
||||
# define arm_pginitialize()
|
||||
void arm_dataabort(uint32_t *regs);
|
||||
#endif /* CONFIG_PAGING */
|
||||
|
||||
/* Exception handlers */
|
||||
|
||||
void up_prefetchabort(uint32_t *regs);
|
||||
void up_syscall(uint32_t *regs);
|
||||
void up_undefinedinsn(uint32_t *regs);
|
||||
void arm_prefetchabort(uint32_t *regs);
|
||||
void arm_syscall(uint32_t *regs);
|
||||
void arm_undefinedinsn(uint32_t *regs);
|
||||
|
||||
#endif /* CONFIG_ARCH_CORTEXM0,3,4,7 */
|
||||
|
||||
void up_vectorundefinsn(void);
|
||||
void up_vectorswi(void);
|
||||
void up_vectorprefetch(void);
|
||||
void up_vectordata(void);
|
||||
void up_vectoraddrexcptn(void);
|
||||
void up_vectorirq(void);
|
||||
void up_vectorfiq(void);
|
||||
void arm_vectorundefinsn(void);
|
||||
void arm_vectorswi(void);
|
||||
void arm_vectorprefetch(void);
|
||||
void arm_vectordata(void);
|
||||
void arm_vectoraddrexcptn(void);
|
||||
void arm_vectorirq(void);
|
||||
void arm_vectorfiq(void);
|
||||
|
||||
/* Floating point unit ******************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
void up_savefpu(uint32_t *regs);
|
||||
void up_restorefpu(const uint32_t *regs);
|
||||
void arm_savefpu(uint32_t *regs);
|
||||
void arm_restorefpu(const uint32_t *regs);
|
||||
#else
|
||||
# define up_savefpu(regs)
|
||||
# define up_restorefpu(regs)
|
||||
# define arm_savefpu(regs)
|
||||
# define arm_restorefpu(regs)
|
||||
#endif
|
||||
|
||||
/* Low level serial output **************************************************/
|
||||
|
||||
void up_lowputc(char ch);
|
||||
void arm_lowputc(char ch);
|
||||
void up_puts(const char *str);
|
||||
void up_lowputs(const char *str);
|
||||
void arm_lowputs(const char *str);
|
||||
|
||||
#ifdef USE_SERIALDRIVER
|
||||
void up_serialinit(void);
|
||||
void arm_serialinit(void);
|
||||
#endif
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
void up_earlyserialinit(void);
|
||||
void arm_earlyserialinit(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RPMSG_UART
|
||||
|
|
@ -437,28 +437,28 @@ void lwlconsole_init(void);
|
|||
/* DMA **********************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_DMA
|
||||
void weak_function up_dma_initialize(void);
|
||||
void weak_function arm_dma_initialize(void);
|
||||
#endif
|
||||
|
||||
/* Cache control ************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_L2CACHE
|
||||
void up_l2ccinitialize(void);
|
||||
void arm_l2ccinitialize(void);
|
||||
#else
|
||||
# define up_l2ccinitialize()
|
||||
# define arm_l2ccinitialize()
|
||||
#endif
|
||||
|
||||
/* Memory management ********************************************************/
|
||||
|
||||
#if CONFIG_MM_REGIONS > 1
|
||||
void up_addregion(void);
|
||||
void arm_addregion(void);
|
||||
#else
|
||||
# define up_addregion()
|
||||
# define arm_addregion()
|
||||
#endif
|
||||
|
||||
/* Watchdog timer ***********************************************************/
|
||||
|
||||
void up_wdtinit(void);
|
||||
void arm_wdtinit(void);
|
||||
|
||||
/* Networking ***************************************************************/
|
||||
|
||||
|
|
@ -468,29 +468,29 @@ void up_wdtinit(void);
|
|||
* network is enabled yet there is no Ethernet driver to be initialized.
|
||||
*
|
||||
* Use of common/arm_etherstub.c is deprecated. The preferred mechanism is
|
||||
* to use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize()
|
||||
* to use CONFIG_NETDEV_LATEINIT=y to suppress the call to arm_netinitialize()
|
||||
* in up_initialize(). Then this stub would not be needed.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
|
||||
void up_netinitialize(void);
|
||||
void arm_netinitialize(void);
|
||||
#else
|
||||
# define up_netinitialize()
|
||||
# define arm_netinitialize()
|
||||
#endif
|
||||
|
||||
/* USB **********************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void up_usbinitialize(void);
|
||||
void up_usbuninitialize(void);
|
||||
void arm_usbinitialize(void);
|
||||
void arm_usbuninitialize(void);
|
||||
#else
|
||||
# define up_usbinitialize()
|
||||
# define up_usbuninitialize()
|
||||
# define arm_usbinitialize()
|
||||
# define arm_usbuninitialize()
|
||||
#endif
|
||||
|
||||
/* Debug ********************************************************************/
|
||||
#ifdef CONFIG_STACK_COLORATION
|
||||
void up_stack_color(FAR void *stackbase, size_t nbytes);
|
||||
void arm_stack_color(FAR void *stackbase, size_t nbytes);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
|
|
|
|||
|
|
@ -46,17 +46,17 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_lowputs
|
||||
* Name: arm_lowputs
|
||||
*
|
||||
* Description:
|
||||
* This is a low-level helper function used to support debug.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_lowputs(const char *str)
|
||||
void arm_lowputs(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
{
|
||||
up_lowputc(*str++);
|
||||
arm_lowputc(*str++);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -149,11 +149,11 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
|
|||
*/
|
||||
|
||||
#ifdef CONFIG_TLS
|
||||
up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
|
||||
arm_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
|
||||
sizeof(struct tls_info_s)),
|
||||
tcb->adj_stack_size - sizeof(struct tls_info_s));
|
||||
#else
|
||||
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
|
||||
arm_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
# define showprogress(c) up_lowputc(c)
|
||||
# define showprogress(c) arm_lowputc(c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -726,7 +726,7 @@ static int dma_stop(int ch)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function up_dma_initialize(void)
|
||||
void weak_function arm_dma_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
|||
|
|
@ -358,8 +358,8 @@ void up_irqinitialize(void)
|
|||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(CXD56_IRQ_SVCALL, up_svcall, NULL);
|
||||
irq_attach(CXD56_IRQ_HARDFAULT, up_hardfault, NULL);
|
||||
irq_attach(CXD56_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(CXD56_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
|
|
@ -378,7 +378,7 @@ void up_irqinitialize(void)
|
|||
*/
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
irq_attach(CXD56_IRQ_MEMFAULT, up_memfault, NULL);
|
||||
irq_attach(CXD56_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(CXD56_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
|
|
@ -387,7 +387,7 @@ void up_irqinitialize(void)
|
|||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(CXD56_IRQ_NMI, cxd56_nmi, NULL);
|
||||
# ifndef CONFIG_ARM_MPU
|
||||
irq_attach(CXD56_IRQ_MEMFAULT, up_memfault, NULL);
|
||||
irq_attach(CXD56_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
# endif
|
||||
irq_attach(CXD56_IRQ_BUSFAULT, cxd56_busfault, NULL);
|
||||
irq_attach(CXD56_IRQ_USAGEFAULT, cxd56_usagefault, NULL);
|
||||
|
|
@ -538,14 +538,14 @@ void up_enable_irq(int irq)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_ack_irq(int irq)
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
/* Check for external interrupt */
|
||||
|
||||
|
|
|
|||
|
|
@ -885,12 +885,12 @@ static bool up_txempty(FAR struct uart_dev_s *dev)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_serialinit
|
||||
* Name: arm_serialinit
|
||||
*
|
||||
* Description:
|
||||
* Performs the low level UART initialization early in debug so that the
|
||||
* serial console will be available during bootup. This must be called
|
||||
* before up_serialinit.
|
||||
* before arm_serialinit.
|
||||
*
|
||||
* NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
|
||||
* very early in the boot sequence.
|
||||
|
|
@ -898,7 +898,7 @@ static bool up_txempty(FAR struct uart_dev_s *dev)
|
|||
****************************************************************************/
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
void up_earlyserialinit(void)
|
||||
void arm_earlyserialinit(void)
|
||||
{
|
||||
/* Configuration whichever one is the console */
|
||||
|
||||
|
|
@ -910,15 +910,15 @@ void up_earlyserialinit(void)
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_serialinit
|
||||
* Name: arm_serialinit
|
||||
*
|
||||
* Description:
|
||||
* Register serial console and serial ports. This assumes that
|
||||
* up_earlyserialinit was called previously.
|
||||
* arm_earlyserialinit was called previously.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_serialinit(void)
|
||||
void arm_serialinit(void)
|
||||
{
|
||||
#ifdef CONSOLE_DEV
|
||||
uart_register("/dev/console", &CONSOLE_DEV);
|
||||
|
|
@ -953,10 +953,10 @@ int up_putc(int ch)
|
|||
{
|
||||
/* Add CR */
|
||||
|
||||
up_lowputc('\r');
|
||||
arm_lowputc('\r');
|
||||
}
|
||||
|
||||
up_lowputc(ch);
|
||||
arm_lowputc(ch);
|
||||
#ifdef HAVE_CONSOLE
|
||||
up_restoreuartint(priv, ier);
|
||||
#endif
|
||||
|
|
@ -983,10 +983,10 @@ int up_putc(int ch)
|
|||
{
|
||||
/* Add CR */
|
||||
|
||||
up_lowputc('\r');
|
||||
arm_lowputc('\r');
|
||||
}
|
||||
|
||||
up_lowputc(ch);
|
||||
arm_lowputc(ch);
|
||||
#endif
|
||||
return ch;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ static void go_nx_start(void *pv, unsigned int nbytes)
|
|||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
# define showprogress(c) up_lowputc(c)
|
||||
# define showprogress(c) arm_lowputc(c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
|
@ -330,7 +330,7 @@ void __start(void)
|
|||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
up_earlyserialinit();
|
||||
arm_earlyserialinit();
|
||||
#endif
|
||||
showprogress('E');
|
||||
|
||||
|
|
|
|||
|
|
@ -325,14 +325,14 @@ static int cxd56_uart_clockchange(uint8_t id)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_lowputc
|
||||
* Name: arm_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_lowputc(char ch)
|
||||
void arm_lowputc(char ch)
|
||||
{
|
||||
#if defined HAVE_UART && defined HAVE_CONSOLE
|
||||
/* Wait for the transmitter to be available */
|
||||
|
|
|
|||
|
|
@ -3100,14 +3100,14 @@ static int cxd56_vbusninterrupt(int irq, FAR void *context, FAR void *arg)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_usbinitialize
|
||||
* Name: arm_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize USB hardware
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_usbinitialize(void)
|
||||
void arm_usbinitialize(void)
|
||||
{
|
||||
usbtrace(TRACE_DEVINIT, 0);
|
||||
|
||||
|
|
@ -3155,14 +3155,14 @@ void up_usbinitialize(void)
|
|||
return;
|
||||
|
||||
errout:
|
||||
up_usbuninitialize();
|
||||
arm_usbuninitialize();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_usbuninitialize
|
||||
* Name: arm_usbuninitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_usbuninitialize(void)
|
||||
void arm_usbuninitialize(void)
|
||||
{
|
||||
FAR struct cxd56_usbdev_s *priv = &g_usbdev;
|
||||
irqstate_t flags;
|
||||
|
|
|
|||
|
|
@ -231,6 +231,6 @@ void arm_boot(void)
|
|||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
up_earlyserialinit();
|
||||
arm_earlyserialinit();
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,35 +1,20 @@
|
|||
/********************************************************************************
|
||||
* arch/arm/src/dm320/dm320_decodeirq.c
|
||||
*
|
||||
* Copyright (C) 2007, 2009, 2011, 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
********************************************************************************/
|
||||
|
||||
|
|
@ -55,12 +40,13 @@
|
|||
* Public Functions
|
||||
********************************************************************************/
|
||||
|
||||
void up_decodeirq(uint32_t *regs)
|
||||
uint32_t *arm_decodeirq(uint32_t *regs)
|
||||
{
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
CURRENT_REGS = regs;
|
||||
err("ERROR: Unexpected IRQ\n");
|
||||
PANIC();
|
||||
return NULL;
|
||||
#else
|
||||
/* Decode the interrupt. First, fetch the interrupt id register. */
|
||||
|
||||
|
|
@ -80,7 +66,7 @@ void up_decodeirq(uint32_t *regs)
|
|||
{
|
||||
/* Acknowledge the interrupt */
|
||||
|
||||
up_ack_irq(irq);
|
||||
arm_ack_irq(irq);
|
||||
|
||||
/* Current regs non-zero indicates that we are processing an interrupt;
|
||||
* CURRENT_REGS is also used to manage interrupt level context switches.
|
||||
|
|
@ -108,7 +94,7 @@ void up_decodeirq(uint32_t *regs)
|
|||
#ifdef CONFIG_ARCH_FPU
|
||||
/* Restore floating point registers */
|
||||
|
||||
up_restorefpu((uint32_t *)CURRENT_REGS);
|
||||
arm_restorefpu((uint32_t *)CURRENT_REGS);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_ADDRENV
|
||||
|
|
@ -131,4 +117,6 @@ void up_decodeirq(uint32_t *regs)
|
|||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return NULL; /* Return not used in this architecture */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -207,14 +207,14 @@ void up_enable_irq(int irq)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the interrupt
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_ack_irq(int irq)
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
/* Acknowledge the interrupt by setting the corresponding bit in the
|
||||
* IRQ status register.
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@
|
|||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_lowputc
|
||||
* Name: arm_lowputc
|
||||
**************************************************************************/
|
||||
|
||||
/* This assembly language version has the advantage that it can does not
|
||||
|
|
@ -82,9 +82,9 @@
|
|||
*/
|
||||
|
||||
.text
|
||||
.global up_lowputc
|
||||
.type up_lowputc, function
|
||||
up_lowputc:
|
||||
.global arm_lowputc
|
||||
.type arm_lowputc, function
|
||||
arm_lowputc:
|
||||
/* On entry, r0 holds the character to be printed */
|
||||
|
||||
#ifdef CONFIG_UART1_SERIAL_CONSOLE
|
||||
|
|
|
|||
|
|
@ -709,16 +709,16 @@ static bool up_txempty(struct uart_dev_s *dev)
|
|||
#ifdef USE_EARLYSERIALINIT
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_earlyserialinit
|
||||
* Name: arm_earlyserialinit
|
||||
*
|
||||
* Description:
|
||||
* Performs the low level UART initialization early in
|
||||
* debug so that the serial console will be available
|
||||
* during bootup. This must be called before up_serialinit.
|
||||
* during bootup. This must be called before arm_serialinit.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_earlyserialinit(void)
|
||||
void arm_earlyserialinit(void)
|
||||
{
|
||||
up_disableuartint(TTYS0_DEV.priv, NULL);
|
||||
up_disableuartint(TTYS1_DEV.priv, NULL);
|
||||
|
|
@ -729,15 +729,15 @@ void up_earlyserialinit(void)
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_serialinit
|
||||
* Name: arm_serialinit
|
||||
*
|
||||
* Description:
|
||||
* Register serial console and serial ports. This assumes
|
||||
* that up_earlyserialinit was called previously.
|
||||
* that arm_earlyserialinit was called previously.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_serialinit(void)
|
||||
void arm_serialinit(void)
|
||||
{
|
||||
uart_register("/dev/console", &CONSOLE_DEV);
|
||||
uart_register("/dev/ttyS0", &TTYS0_DEV);
|
||||
|
|
|
|||
|
|
@ -1867,8 +1867,8 @@ static void dm320_ctrlinitialize(FAR struct dm320_usbdev_s *priv)
|
|||
|
||||
/* Initialize interrupts *****************************************************/
|
||||
|
||||
up_ack_irq(DM320_IRQ_USB0); /* Clear USB controller interrupt */
|
||||
up_ack_irq(DM320_IRQ_USB1); /* Clear USB DMA interrupt flag */
|
||||
arm_ack_irq(DM320_IRQ_USB0); /* Clear USB controller interrupt */
|
||||
arm_ack_irq(DM320_IRQ_USB1); /* Clear USB DMA interrupt flag */
|
||||
|
||||
dm320_getreg8(DM320_USB_INTRTX1); /* Clear TX interrupt */
|
||||
dm320_getreg8(DM320_USB_INTRRX1); /* Clear RX interrupt */
|
||||
|
|
@ -2392,14 +2392,14 @@ static int dm320_pullup(struct usbdev_s *dev, bool enable)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_usbinitialize
|
||||
* Name: arm_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize USB hardware
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_usbinitialize(void)
|
||||
void arm_usbinitialize(void)
|
||||
{
|
||||
struct dm320_usbdev_s *priv = &g_usbdev;
|
||||
struct dm320_ep_s *privep;
|
||||
|
|
@ -2499,14 +2499,14 @@ void up_usbinitialize(void)
|
|||
return;
|
||||
|
||||
errout:
|
||||
up_usbuninitialize();
|
||||
arm_usbuninitialize();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_usbuninitialize
|
||||
* Name: arm_usbuninitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_usbuninitialize(void)
|
||||
void arm_usbuninitialize(void)
|
||||
{
|
||||
struct dm320_usbdev_s *priv = &g_usbdev;
|
||||
|
||||
|
|
|
|||
|
|
@ -260,7 +260,7 @@ static int efm32_dmac_interrupt(int irq, void *context, FAR void *arg)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_initialize
|
||||
* Name: arm_dma_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DMA subsystem
|
||||
|
|
@ -270,7 +270,7 @@ static int efm32_dmac_interrupt(int irq, void *context, FAR void *arg)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function up_dma_initialize(void)
|
||||
void weak_function arm_dma_initialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
int i;
|
||||
|
|
|
|||
|
|
@ -373,8 +373,8 @@ void up_irqinitialize(void)
|
|||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(EFM32_IRQ_SVCALL, up_svcall, NULL);
|
||||
irq_attach(EFM32_IRQ_HARDFAULT, up_hardfault, NULL);
|
||||
irq_attach(EFM32_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(EFM32_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
|
|
@ -387,7 +387,7 @@ void up_irqinitialize(void)
|
|||
*/
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault, NULL);
|
||||
irq_attach(EFM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(EFM32_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
|
|
@ -396,7 +396,7 @@ void up_irqinitialize(void)
|
|||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(EFM32_IRQ_NMI, efm32_nmi, NULL);
|
||||
#ifndef CONFIG_ARM_MPU
|
||||
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault, NULL);
|
||||
irq_attach(EFM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
#endif
|
||||
irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault, NULL);
|
||||
irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault, NULL);
|
||||
|
|
@ -513,14 +513,14 @@ void up_enable_irq(int irq)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_ack_irq(int irq)
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
|||
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Reference in a new issue