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arch/arm/src/imxrt/imxrt_lpspi.c: Fix nxstyle issues

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Add braces to switch-case

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen 2026-09-14 09:39:11 +03:00 • committed by Alan C. Assis
parent 61b81b63a9
commit 2a3f06b7bd
1 changed files with 55 additions and 38 deletions
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93
arch/arm/src/imxrt/imxrt_lpspi.c
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@ -681,26 +681,32 @@ static inline void imxrt_lpspi_master_set_delay_scaler(
{
switch (type)
{
case LPSPI_PCS_TO_SCK:
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_PCSSCK_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_PCSSCK(scaler));
break;
case LPSPI_PCS_TO_SCK:
{
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_PCSSCK_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_PCSSCK(scaler));
break;
}
case LPSPI_LAST_SCK_TO_PCS:
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_SCKPCS_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_SCKPCS(scaler));
break;
case LPSPI_LAST_SCK_TO_PCS:
{
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_SCKPCS_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_SCKPCS(scaler));
break;
}
case LPSPI_BETWEEN_TRANSFER:
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_DBT_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_DBT(scaler));
break;
case LPSPI_BETWEEN_TRANSFER:
{
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
LPSPI_CCR_DBT_MASK, 0);
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0,
LPSPI_CCR_DBT(scaler));
break;
}
}
}
@ -1123,28 +1129,38 @@ static void imxrt_lpspi_setmode(struct spi_dev_s *dev,
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
setbits = 0;
clrbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA;
break;
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
{
setbits = 0;
clrbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA;
break;
}
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
setbits = LPSPI_TCR_CPHA;
clrbits = LPSPI_TCR_CPOL;
break;
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
{
setbits = LPSPI_TCR_CPHA;
clrbits = LPSPI_TCR_CPOL;
break;
}
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
setbits = LPSPI_TCR_CPOL;
clrbits = LPSPI_TCR_CPHA;
break;
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
{
setbits = LPSPI_TCR_CPOL;
clrbits = LPSPI_TCR_CPHA;
break;
}
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
setbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA;
clrbits = 0;
break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
{
setbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA;
clrbits = 0;
break;
}
default:
return;
default:
{
return;
}
}
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET,
@ -1361,6 +1377,7 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct imxrt_lpspidev_s *priv = (struct imxrt_lpspidev_s *)dev;
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@ -1581,8 +1598,8 @@ static void imxrt_lpspi_exchange(struct spi_dev_s *dev,
if (rxbuffer)
{
up_invalidate_dcache((uintptr_t)rxbuffer,
(uintptr_t)rxbuffer + nbytes);
up_invalidate_dcache((uintptr_t)rxbuffer,
(uintptr_t)rxbuffer + nbytes);
}
}