diff --git a/arch/hc/include/hc12/irq.h b/arch/hc/include/hc12/irq.h index da5310a80e3..c6030d6d56d 100644 --- a/arch/hc/include/hc12/irq.h +++ b/arch/hc/include/hc12/irq.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/include/hc12/irq.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* This file should never be included directly but, rather, * only indirectly through nuttx/irq.h @@ -25,20 +25,20 @@ #ifndef __ARCH_HC_INCLUDE_HC12_IRQ_H #define __ARCH_HC_INCLUDE_HC12_IRQ_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* This structure defines the way the registers are stored. */ @@ -76,14 +76,14 @@ static inline void up_irq_restore(irqstate_t flags) } static inline void system_call3(unsigned int nbr, uintptr_t parm1, - uintptr_t parm2, uintptr_t parm3) + uintptr_t parm2, uintptr_t parm3) { /* To be provided */ } -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifdef __cplusplus #define EXTERN extern "C" @@ -93,9 +93,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #undef EXTERN #ifdef __cplusplus diff --git a/arch/hc/include/m9s12/irq.h b/arch/hc/include/m9s12/irq.h index 751ae8ebfa0..fcd1471c63e 100644 --- a/arch/hc/include/m9s12/irq.h +++ b/arch/hc/include/m9s12/irq.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/include/m9s12/irq.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* This file should never be included directly but, rather, * only indirectly through nuttx/irq.h @@ -25,16 +25,16 @@ #ifndef __ARCH_HC_INCLUDE_M9S12_IRQ_H #define __ARCH_HC_INCLUDE_M9S12_IRQ_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* IRQ Numbers */ @@ -84,7 +84,8 @@ /* ff80-ff9f: Reserved */ #define HCS12_IRQ_NVECTORS 38 -/* GPIO interrupts. The m9s12x supports several interrupts on PIM ports G, H, +/* GPIO interrupts. + * The m9s12x supports several interrupts on PIM ports G, H, * and J. We go through some special efforts to keep the number of IRQs * to a minimum in this sparse interrupt case. * @@ -146,13 +147,13 @@ #define HCS12_IRQ_VILLEGAL HCS12_IRQ_NIRQS /* Any reserved vector */ #define NR_IRQS (HCS12_IRQ_NIRQS+1) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -163,9 +164,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #undef EXTERN #ifdef __cplusplus diff --git a/arch/hc/include/types.h b/arch/hc/include/types.h index b41a45352fa..967ceaf2fcc 100644 --- a/arch/hc/include/types.h +++ b/arch/hc/include/types.h @@ -29,10 +29,6 @@ * Included Files ****************************************************************************/ -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /* Include architecture-specific limits definitions */ #if defined(CONFIG_ARCH_HC12) @@ -41,6 +37,10 @@ # include #endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /**************************************************************************** * Type Declarations ****************************************************************************/ diff --git a/arch/hc/src/common/up_allocateheap.c b/arch/hc/src/common/up_allocateheap.c index 822c0d1d809..b9caab794e1 100644 --- a/arch/hc/src/common/up_allocateheap.c +++ b/arch/hc/src/common/up_allocateheap.c @@ -67,6 +67,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { board_autoled_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/hc/src/common/up_doirq.c b/arch/hc/src/common/up_doirq.c index 0df689f1fbb..725baa2bd1e 100644 --- a/arch/hc/src/common/up_doirq.c +++ b/arch/hc/src/common/up_doirq.c @@ -89,7 +89,7 @@ uint8_t *up_doirq(int irq, uint8_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - up_restorefpu((uint32_t*)g_current_regs); + up_restorefpu((uint32_t *)g_current_regs); #endif #ifdef CONFIG_ARCH_ADDRENV @@ -110,7 +110,7 @@ uint8_t *up_doirq(int irq, uint8_t *regs) * switch occurred during interrupt processing. */ - regs = (uint8_t*)g_current_regs; + regs = (uint8_t *)g_current_regs; /* Set g_current_regs to NULL to indicate that we are no longer in an * interrupt handler. diff --git a/arch/hc/src/common/up_internal.h b/arch/hc/src/common/up_internal.h index 46484aafea8..13eae27ec19 100644 --- a/arch/hc/src/common/up_internal.h +++ b/arch/hc/src/common/up_internal.h @@ -115,7 +115,7 @@ extern uint32_t g_intstackbase; ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /* Context switching functions */ diff --git a/arch/hc/src/common/up_interruptcontext.c b/arch/hc/src/common/up_interruptcontext.c index a748a227f9a..4dc2428e1e9 100644 --- a/arch/hc/src/common/up_interruptcontext.c +++ b/arch/hc/src/common/up_interruptcontext.c @@ -52,5 +52,5 @@ bool up_interrupt_context(void) { - return g_current_regs != NULL; + return g_current_regs != NULL; } diff --git a/arch/hc/src/common/up_mdelay.c b/arch/hc/src/common/up_mdelay.c index 99badcb1e0e..11b3edfc55a 100644 --- a/arch/hc/src/common/up_mdelay.c +++ b/arch/hc/src/common/up_mdelay.c @@ -68,8 +68,8 @@ void up_mdelay(unsigned int milliseconds) for (i = 0; i < milliseconds; i++) { - for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) - { - } + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } } } diff --git a/arch/hc/src/common/up_udelay.c b/arch/hc/src/common/up_udelay.c index ead7e53ed7b..3a5e204af76 100644 --- a/arch/hc/src/common/up_udelay.c +++ b/arch/hc/src/common/up_udelay.c @@ -85,6 +85,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) { } + microseconds -= 1000; } @@ -93,6 +94,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) { } + microseconds -= 100; } @@ -101,6 +103,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) { } + microseconds -= 10; } @@ -109,6 +112,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) { } + microseconds--; } } diff --git a/arch/hc/src/m9s12/chip.h b/arch/hc/src/m9s12/chip.h index a730d8fb544..70473e2cacb 100644 --- a/arch/hc/src/m9s12/chip.h +++ b/arch/hc/src/m9s12/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_HC_SRC_M9S12_CHIP_H #define __ARCH_HC_SRC_M9S12_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Memory Map. * @@ -72,16 +72,16 @@ #define HCS12_PIM_BASE 0x0240 /* 0x0240–0x026f: Port Integration Module (PIM) */ /* 0x0270–0x03ff: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_HC_SRC_M9S12_CHIP_H */ diff --git a/arch/hc/src/m9s12/m9s12.h b/arch/hc/src/m9s12/m9s12.h index 60984fe8e52..7b8588ac10a 100644 --- a/arch/hc/src/m9s12/m9s12.h +++ b/arch/hc/src/m9s12/m9s12.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_HC_SRC_M9S12_M9S12_H #define __ARCH_HC_SRC_M9S12_M9S12_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -36,13 +36,14 @@ #include "up_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* GPIO management macros: * - * The GPIO configuration is represented by a 16-bit value encoded as follows: + * The GPIO configuration is represented by a 16-bit value encoded as + * follows: * * xIIO UURV DMGG GPPP * ||| |||| ||| `-Pin number @@ -180,15 +181,15 @@ # define GPIO_PIN_6 (6 << GPIO_PORT_SHIFT) # define GPIO_PIN_7 (7 << GPIO_PORT_SHIFT) -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -199,57 +200,58 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: hcs12_gpioirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ void hcs12_gpioirqinitialize(void); -/************************************************************************************ +/**************************************************************************** * Name: hcs12_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int hcs12_configgpio(uint16_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: hcs12_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void hcs12_gpiowrite(uint16_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: hcs12_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool hcs12_gpioread(uint16_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: hcs12_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_HCS12_GPIOIRQ void hcs12_gpioirqenable(int irq); @@ -257,13 +259,13 @@ void hcs12_gpioirqenable(int irq); # define hcs12_gpioirqenable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: hcs12_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_HCS12_GPIOIRQ void hcs12_gpioirqdisable(int irq); @@ -271,13 +273,14 @@ void hcs12_gpioirqdisable(int irq); # define hcs12_gpioirqdisable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: hcs12_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int hcs12_dumpgpio(uint16_t pinset, const char *msg); @@ -285,7 +288,7 @@ int hcs12_dumpgpio(uint16_t pinset, const char *msg); # define hcs12_dumpgpio(p,m) #endif -/************************************************************************************ +/**************************************************************************** * Function: hcs12_ethinitialize * * Description: @@ -302,7 +305,7 @@ int hcs12_dumpgpio(uint16_t pinset, const char *msg); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #if STM32_NTHERNET > 1 int hcs12_ethinitialize(int intf); @@ -325,32 +328,34 @@ int hcs12_ethinitialize(int intf); struct spi_dev_s; /* Forward reference */ FAR struct spi_dev_s *hcs12_spibus_initialize(int port); -/************************************************************************************ +/**************************************************************************** * Name: hcs12_spiselect and hcs12_spistatus * * Description: * The external functions, hcs12_spiselect and hcs12_spistatus must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including mps12_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * provided by board-specific logic. They are implementations of the + * select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including mps12_spibus_initialize()) are provided by + * common STM32 logic. To use this common SPI logic on your board: * * 1. Provide logic in hcs12_boardinitialize() to configure SPI chip select * pins. * 2. Provide hcs12_spiselect() and hcs12_spistatus() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to mps12_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by mps12_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to mps12_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by mps12_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************************************/ -void hcs12_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void hcs12_spiselect(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t hcs12_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); #undef EXTERN diff --git a/arch/hc/src/m9s12/m9s12_atd.h b/arch/hc/src/m9s12/m9s12_atd.h index f0a71282161..0e42c2e3ffe 100644 --- a/arch/hc/src/m9s12/m9s12_atd.h +++ b/arch/hc/src/m9s12/m9s12_atd.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_atd.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_ATD_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_ATD_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_ATD_CTL0_OFFSET 0x0000 /* ATD control register 0 */ #define HCS12_ATD_CTL1_OFFSET 0x0001 /* ATD control register 1 */ @@ -85,7 +85,7 @@ #define HCS12_ATD_DR7H_OFFSET 0x002e /* ATD conversion result register 7 (high) */ #define HCS12_ATD_DR7L_OFFSET 0x002f /* ATD conversion result register 7 (low) */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_ATD_CTL0 (HCS12_ATD_BASE+HCS12_ATD_CTL0_OFFSET) #define HCS12_ATD_CTL1 (HCS12_ATD_BASE+HCS12_ATD_CTL1_OFFSET) @@ -136,7 +136,7 @@ #define HCS12_ATD_DR7H (HCS12_ATD_BASE+HCS12_ATD_DR7H_OFFSET) #define HCS12_ATD_DR7L (HCS12_ATD_BASE+HCS12_ATD_DR7L_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* ATD control register 0 */ @@ -211,17 +211,19 @@ #define ATD_CTL4_PRS_SHIFT (0) /* Bits 0-4: ATD Clock Prescaler */ #define ATD_CTL4_PRS_MASK (31 << ATD_CTL4_PRS_SHIFT) # define ATD_CTL4_PRS_DIV(n) ((((n)-2) >> 1) << ATD_CTL4_PRS_SHIFT) /* Divide by n={2,4,6,...,64} */ + #define ATD_CTL4_SMP_SHIFT (5) /* Bits 5-6: Sample Time Select */ #define ATD_CTL4_SMP_MASK (3 << ATD_CTL4_SMP_SHIFT) # define ATD_CTL4_SMP2 (0 << ATD_CTL4_SMP_SHIFT) /* 2 A/D conversion clock periods */ # define ATD_CTL4_SMP4 (1 << ATD_CTL4_SMP_SHIFT) /* 4 A/D conversion clock periods */ # define ATD_CTL4_SMP8 (2 << ATD_CTL4_SMP_SHIFT) /* 8 A/D conversion clock periods */ # define ATD_CTL4_SMP16 (3 << ATD_CTL4_SMP_SHIFT) /* 16 A/D conversion clock periods */ + #define ATD_CTL4_SRES8 (1 << 7) /* Bit 7: A/D Resolution Select */ /* ATD control register 5 */ -#define ATD_CTL5_C_SHIFT (0) /* Bits 0-2: Analog Input Channel Select Code */ +#define ATD_CTL5_C_SHIFT (0) /* Bits 0-2: Analog Input Channel Select Code */ #define ATD_CTL5_C_MASK (7 << ATD_CTL5_C_SHIFT) # define ATD_CTL5_C_AN(n) ((n) << ATD_CTL5_C_SHIFT) # define ATD_CTL5_C_AN0 (0 << ATD_CTL5_C_SHIFT) @@ -246,6 +248,7 @@ #define ATD_STAT0_SCF (1 << 7) /* Bit 7: Sequence Complete Flag */ /* ATD test register 0 -- 8 MS bits of data written in special mode */ + /* ATD test register 1 */ #define ATD_TEST1_SC (1 << 0) /* Bit 0: Enable special conversions */ @@ -254,6 +257,7 @@ /* ATD status register 1 */ #define ATD_STAT1_CCF(n) (1 << (n)) /* Bit n: Conversion complete flag channel n */ + #define ATD_STAT1_CCF0 (1 << 0) /* Bit 0: Conversion complete flag channel 0 */ #define ATD_STAT1_CCF1 (1 << 1) /* Bit 1: Conversion complete flag channel 1 */ #define ATD_STAT1_CCF2 (1 << 2) /* Bit 2: Conversion complete flag channel 2 */ @@ -266,6 +270,7 @@ /* ATD Input enable register */ #define ATD_IEN(n) (1 << (n)) /* Bit n: ATD Digital Input Enable on channel n */ + #define ATD_IEN0 (1 << 0) /* Bit 0: ATD Digital Input Enable on channel 0 */ #define ATD_IEN1 (1 << 1) /* Bit 1: ATD Digital Input Enable on channel 1 */ #define ATD_IEN2 (1 << 2) /* Bit 2: ATD Digital Input Enable on channel 2 */ @@ -278,6 +283,7 @@ /* Port data register */ #define ATD_PORTAD(n) (1 << (n)) /* Bit n: A/D Channel n (ANn) Digital Input */ + #define ATD_PORTAD0 (1 << 0) /* Bit 0: A/D Channel 0 (AN0) Digital Input */ #define ATD_PORTAD1 (1 << 1) /* Bit 1: A/D Channel 1 (AN1) Digital Input */ #define ATD_PORTAD2 (1 << 2) /* Bit 2: A/D Channel 2 (AN2) Digital Input */ @@ -292,16 +298,16 @@ #define ATD_DLL_MASK 0xc0 /* Bits 6-7: LS bits of left justified data */ #define ATD_DRH_MASK 0x03 /* Bits 0-1: MS bits of right justified data */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_ATD_H */ diff --git a/arch/hc/src/m9s12/m9s12_crg.h b/arch/hc/src/m9s12/m9s12_crg.h index 0c539e26b30..30a537874c8 100644 --- a/arch/hc/src/m9s12/m9s12_crg.h +++ b/arch/hc/src/m9s12/m9s12_crg.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_crg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* CRG Module Register Offsets */ @@ -110,16 +110,16 @@ #define CRG_COPCTL_RSBCK (1 << 6) /* Bit 6: COP and RTI stop in Active BDM mode B */ #define CRG_COPCTL_WCOP (1 << 7) /* Bit 7: Window COP Mode Bit */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H */ diff --git a/arch/hc/src/m9s12/m9s12_dumpgpio.c b/arch/hc/src/m9s12/m9s12_dumpgpio.c index 30b9b3ff379..1bd15975446 100644 --- a/arch/hc/src/m9s12/m9s12_dumpgpio.c +++ b/arch/hc/src/m9s12/m9s12_dumpgpio.c @@ -124,15 +124,15 @@ static const struct gpio_piminfo_s piminfo[HCS12_PIM_NPORTS] = {HCS12_PIM_PORTG_BASE, 'G', PIMPORT_FORM3}, /* Port G */ {HCS12_PIM_PORTH_BASE, 'H', PIMPORT_FORM3}, /* Port H */ {HCS12_PIM_PORTJ_BASE, 'J', PIMPORT_FORM3}, /* Port J */ - {HCS12_PIM_PORTL_BASE, 'L', PIMPORT_FORM2} /* Port L */ + {HCS12_PIM_PORTL_BASE, 'L', PIMPORT_FORM2}, /* Port L */ }; static const struct gpio_mebiinfo_s mebiinfo[HCS12_MEBI_NPORTS] = { - {HCS12_MEBI_PORTA, HCS12_MEBI_DDRA, 'A', MEBIPORT_AB}, /* Port A */ - {HCS12_MEBI_PORTB, HCS12_MEBI_DDRB, 'B', MEBIPORT_AB}, /* Port B */ - {HCS12_MEBI_PORTE, HCS12_MEBI_DDRE, 'E', MEBIPORT_E}, /* Port E */ - {HCS12_MEBI_PORTK, HCS12_MEBI_DDRK, 'K', MEBIPORT_K} /* Port K */ + {HCS12_MEBI_PORTA, HCS12_MEBI_DDRA, 'A', MEBIPORT_AB}, /* Port A */ + {HCS12_MEBI_PORTB, HCS12_MEBI_DDRB, 'B', MEBIPORT_AB}, /* Port B */ + {HCS12_MEBI_PORTE, HCS12_MEBI_DDRE, 'E', MEBIPORT_E}, /* Port E */ + {HCS12_MEBI_PORTK, HCS12_MEBI_DDRK, 'K', MEBIPORT_K}, /* Port K */ }; /**************************************************************************** @@ -164,32 +164,32 @@ static inline void hcs12_pimdump(uint8_t portndx) ptr = &piminfo[portndx]; gpioinfo(" PIM Port%c:\n", ptr->name); gpioinfo(" IO:%02x INP:%02x DDR:%02x RDR:%02x\n", - getreg8(ptr->base+HCS12_PIM_IO_OFFSET), - getreg8(ptr->base+HCS12_PIM_INPUT_OFFSET), - getreg8(ptr->base+HCS12_PIM_DDR_OFFSET), - getreg8(ptr->base+HCS12_PIM_RDR_OFFSET)); + getreg8(ptr->base + HCS12_PIM_IO_OFFSET), + getreg8(ptr->base + HCS12_PIM_INPUT_OFFSET), + getreg8(ptr->base + HCS12_PIM_DDR_OFFSET), + getreg8(ptr->base + HCS12_PIM_RDR_OFFSET)); switch (ptr->form) { case PIMPORT_FORM1: gpioinfo(" PER:%02x PS:%02x\n", - getreg8(ptr->base+HCS12_PIM_PER_OFFSET), - getreg8(ptr->base+HCS12_PIM_PS_OFFSET)); + getreg8(ptr->base + HCS12_PIM_PER_OFFSET), + getreg8(ptr->base + HCS12_PIM_PS_OFFSET)); break; case PIMPORT_FORM2: gpioinfo(" PER:%02x PS:%02x WOM:%02x\n", - getreg8(ptr->base+HCS12_PIM_PER_OFFSET), - getreg8(ptr->base+HCS12_PIM_PS_OFFSET), - getreg8(ptr->base+HCS12_PIM_WOM_OFFSET)); + getreg8(ptr->base + HCS12_PIM_PER_OFFSET), + getreg8(ptr->base + HCS12_PIM_PS_OFFSET), + getreg8(ptr->base + HCS12_PIM_WOM_OFFSET)); break; case PIMPORT_FORM3: gpioinfo(" PER:%02x PS:%02x IE:%02x IF:%02x\n", - getreg8(ptr->base+HCS12_PIM_PER_OFFSET), - getreg8(ptr->base+HCS12_PIM_PS_OFFSET), - getreg8(ptr->base+HCS12_PIM_IE_OFFSET), - getreg8(ptr->base+HCS12_PIM_IF_OFFSET)); + getreg8(ptr->base + HCS12_PIM_PER_OFFSET), + getreg8(ptr->base + HCS12_PIM_PS_OFFSET), + getreg8(ptr->base + HCS12_PIM_IE_OFFSET), + getreg8(ptr->base + HCS12_PIM_IF_OFFSET)); break; default: @@ -246,13 +246,14 @@ static inline void hcs12_mebidump(uint8_t portndx) * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Function: hcs12_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ int hcs12_dumpgpio(uint16_t pinset, const char *msg) { diff --git a/arch/hc/src/m9s12/m9s12_emac.h b/arch/hc/src/m9s12/m9s12_emac.h index 3e69bf3352c..b2541e40b7b 100644 --- a/arch/hc/src/m9s12/m9s12_emac.h +++ b/arch/hc/src/m9s12/m9s12_emac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_emac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_EMAC_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_EMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_EMAC_NETCTL_OFFSET 0x0000 /* Network Control (8-bit) */ #define HCS12_EMAC_RXCTS_OFFSET 0x0003 /* Receive Control and Status (8-bit) */ @@ -61,7 +61,7 @@ #define HCS12_EMAC_MACAD0_OFFSET 0x002c /* MAC Unicast AAddress 0-15 (16-bit) */ #define HCS12_EMAC_EMISC _OFFSET 0x002e /* Miscellaneous (16-bit) */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_EMAC_NETCTL (HCS12_EMAC_BASE+HCS12_EMAC_NETCTL_OFFSET) #define HCS12_EMAC_RXCTS (HCS12_EMAC_BASE+HCS12_EMAC_RXCTS_OFFSET) @@ -90,7 +90,7 @@ #define HCS12_EMAC_MACAD0 (HCS12_EMAC_BASE+HCS12_EMAC_MACAD0_OFFSET) #define HCS12_EMAC_EMISC (HCS12_EMAC_BASE+HCS12_EMAC_EMISC_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Network Control (8-bit) */ @@ -130,9 +130,11 @@ #define EMAC_ETCTL_FPET (1 << 7) /* Bit 7: Programmable Ethertype */ /* Programmable Ethertype (16-bit) -- 16-bit Ethernet type data */ + /* PAUSE Timer Value and Counter (16-bit) -- 16-bit PAUSER timer value */ /* Interrupt Event (16-bit) */ + /* Interrupt Mask (16-bit) */ #define EMAC_INT_TXCI (1 << 1) /* Bit 1: Frame Transmission Complete Interrupt */ @@ -160,6 +162,7 @@ #define EMAC_MRADR_MASK (0x1f) /* MII Management Write Data (16-bit) -- 16-bit write data */ + /* MII Management Read Data (16-bit) -- 16-bit read data */ /* MII Management Command and Status (8-bit) */ @@ -199,12 +202,17 @@ #define EMAC_TXEFP_MASK (0x07ff) /* Multicast Hash Table 48-63 (16-bit) -- 16-bits of MAC address */ + /* Multicast Hash Table 32-47 (16-bit) -- 16-bits of MAC address */ + /* Multicast Hash Table 16-31 (16-bit) -- 16-bits of MAC address */ + /* Multicast Hash Table 0:15 (16-bit) -- 16-bits of MAC address */ /* MAC Unicast Address 32-47 (16-bit) -- 16-bits of address */ + /* MAC Unicast AAddress 16-31 (16-bit) -- 16-bits of address */ + /* MAC Unicast AAddress 0-15 (16-bit) -- 16-bits of address */ /* Miscellaneous (16-bit) */ @@ -218,16 +226,16 @@ # define EMAC_EMISC_INDEX_RETX (5 << EMAC_EMISC_INDEX_SHIFT) /* Retransmission Counter */ # define EMAC_EMISC_INDEX_RANDOM (6 << EMAC_EMISC_INDEX_SHIFT) /* Backoff Random Number */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_EMAC_H */ diff --git a/arch/hc/src/m9s12/m9s12_flash.h b/arch/hc/src/m9s12/m9s12_flash.h index 9d67f116559..7a84abca2c4 100644 --- a/arch/hc/src/m9s12/m9s12_flash.h +++ b/arch/hc/src/m9s12/m9s12_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_flash.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_FLASH_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_FLASH_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Flash memory map ***************************************************************** +/* Flash memory map ********************************************************* * * 0x4000-0x7fff: 16Kb Fixed FLASH EEPROM (Page 3e) * 0x8000-0xbfff: 16Kb Page window @@ -65,8 +65,8 @@ * RxReady: ldaa SCI0DRL ;read character into A * rts ;return * EraseAllCmd - Use repeated page erase commands to erase all flash - * except bootloader in protected block at the end of flash, and mass - * erase all EEPROM locations + * except bootloader in protected block at the end of flash, + * and mass erase all EEPROM locations * DoOnStack - Copy to stack and execute from RAM * WriteD2IX - Write the data in D (word) to the address in IX * The location may be RAM, FLASH, EEPROM, or a register @@ -106,7 +106,7 @@ #define HCS12_VECTOR_BASE 0xff80 /* 0xff80–0xfffe: Actual vector base */ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_FLASH_FCLKDIV_OFFSET (HCS12_FLASH_BASE+0x00) /* Flash Clock Divider Register */ #define HCS12_FLASH_FSEC_OFFSET (HCS12_FLASH_BASE+0x03) /* Flash Security Register */ @@ -119,7 +119,7 @@ #define HCS12_FLASH_FDATAHI_OFFSET (HCS12_FLASH_BASE+0x0a) /* Flash High Data Register */ #define HCS12_FLASH_FDATALO_OFFSET (HCS12_FLASH_BASE+0x0b) /* Flash Low Data Register (*/ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_FLASH_FCLKDIV (HCS12_REG_BASE+HCS12_FLASH_FCLKDIV_OFFSET) #define HCS12_FLASH_FSEC (HCS12_REG_BASE+HCS12_FLASH_FSEC_OFFSET) @@ -132,7 +132,7 @@ #define HCS12_FLASH_FDATAHI (HCS12_REG_BASE+HCS12_FLASH_FDATAHI_OFFSET) #define HCS12_FLASH_FDATALO (HCS12_REG_BASE+HCS12_FLASH_FDATALO_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ #define FLASH_FCLKDIV_FDIV_SHIFT (0) /* Bits 0-5: Clock Divider Bits */ #define FLASH_FCLKDIV_FDIV_MASK (0x3f << FLASH_FCLKDIV_FDIV_SHIFT) @@ -179,16 +179,16 @@ #define FLASH_FADDRHI_MASK 0x7f -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_FLASH_H */ diff --git a/arch/hc/src/m9s12/m9s12_gpio.c b/arch/hc/src/m9s12/m9s12_gpio.c index 567a62cea26..8d9a83e802b 100644 --- a/arch/hc/src/m9s12/m9s12_gpio.c +++ b/arch/hc/src/m9s12/m9s12_gpio.c @@ -40,9 +40,11 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* GPIO management macros: * - * The GPIO configuration is represented by a 16-bit value encoded as follows: + * The GPIO configuration is represented by a 16-bit value encoded as + * follows: * * xIIO UURV DMGG GPPP * ||| |||| ||| `-Pin number @@ -136,7 +138,7 @@ static const struct mebi_portaddr_s mebi_portaddr[HCS12_MEBI_NPORTS] = {HCS12_MEBI_PORTA, HCS12_MEBI_DDRA}, /* Port A */ {HCS12_MEBI_PORTB, HCS12_MEBI_DDRB}, /* Port B */ {HCS12_MEBI_PORTE, HCS12_MEBI_DDRE}, /* Port E */ - {HCS12_MEBI_PORTK, HCS12_MEBI_DDRK} /* Port K */ + {HCS12_MEBI_PORTK, HCS12_MEBI_DDRK}, /* Port K */ }; static uint8_t mebi_bits[HCS12_MEBI_NPORTS] = @@ -165,6 +167,7 @@ static inline void gpio_writebit(uint16_t regaddr, uint8_t pin, bool set) { regval &= ~(1 << pin); } + putreg8(regval, regaddr); } @@ -192,7 +195,8 @@ static inline void mebi_direction(uint8_t portndx, uint8_t pin, bool output) /* Write to the Wired-OR register of a PIM port */ -static inline void pim_opendrain(uint8_t portndx, uint8_t pin, bool opendrain) +static inline void pim_opendrain(uint8_t portndx, + uint8_t pin, bool opendrain) { DEBUGASSERT(!opendrain || (HCS12_WOM_PORTS & (1 << pin)) != 0); gpio_writebit(HCS12_PIM_PORT_WOM(portndx), pin, opendrain); @@ -231,6 +235,7 @@ static inline void mebi_pullport(uint8_t portndx, uint8_t pull) { regval &= ~mebi_bits[portndx]; } + putreg8(regval, HCS12_MEBI_PUCR); } @@ -254,6 +259,7 @@ static inline void mebi_rdport(uint8_t portndx, bool rdenable) { regval &= ~mebi_bits[portndx]; } + putreg8(regval, HCS12_MEBI_RDRIV); } @@ -265,7 +271,8 @@ static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type) { DEBUGASSERT((HCS12_IE_PORTS & (1 << pin)) != 0); gpio_writebit(HCS12_PIM_PORT_IE(portndx), pin, false); - gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, ((type & GPIO_INT_POLARITY) != 0)); + gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, + ((type & GPIO_INT_POLARITY) != 0)); } else if ((HCS12_IE_PORTS & (1 << pin)) != 0) { @@ -281,7 +288,8 @@ static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type) * ****************************************************************************/ -static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) +static inline void pim_configgpio(uint16_t cfgset, + uint8_t portndx, uint8_t pin) { /* Sanity checking -- Check if the pin will be enabled as an interrupt * (later) @@ -329,7 +337,8 @@ static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) * ****************************************************************************/ -static inline void mebi_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) +static inline void mebi_configgpio(uint16_t cfgset, + uint8_t portndx, uint8_t pin) { DEBUGASSERT(portndx < HCS12_MEBI_NPORTS); mebi_direction(portndx, pin, ((cfgset & GPIO_DIRECTION) == GPIO_OUTPUT)); @@ -413,8 +422,10 @@ int hcs12_configgpio(uint16_t cfgset) if (HCS12_OUTPUT(cfgset)) { - hcs12_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_VALUE) == GPIO_OUTPUT_HIGH); + hcs12_gpiowrite(cfgset, + (cfgset & GPIO_OUTPUT_VALUE) == GPIO_OUTPUT_HIGH); } + return OK; } diff --git a/arch/hc/src/m9s12/m9s12_gpioirq.c b/arch/hc/src/m9s12/m9s12_gpioirq.c index 3a111bb2dd6..4bcf33ba489 100644 --- a/arch/hc/src/m9s12/m9s12_gpioirq.c +++ b/arch/hc/src/m9s12/m9s12_gpioirq.c @@ -103,6 +103,7 @@ static int hcs12_mapirq(int irq, uint16_t *regaddr, uint8_t *pin) } #endif } + return -EINVAL; } #endif /* CONFIG_HCS12_GPIOIRQ */ @@ -116,7 +117,8 @@ static int hcs12_mapirq(int irq, uint16_t *regaddr, uint8_t *pin) ****************************************************************************/ #ifdef CONFIG_HCS12_GPIOIRQ -static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context) +static int hcs12_interrupt(uint16_t base, + int irq0, uint8_t valid, void *context) { uint8_t pending; uint8_t bit; @@ -124,14 +126,15 @@ static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context /* Get the set of enabled (unmasked) interrupts pending on this port */ - pending = getreg8(base+HCS12_PIM_IF_OFFSET) && getreg8(base+HCS12_PIM_IE_OFFSET); + pending = getreg8(base + HCS12_PIM_IF_OFFSET) && + getreg8(base + HCS12_PIM_IE_OFFSET); /* Then check each bit in the set of interrupts */ for (bit = 1, irq = irq0; pending != 0; bit <<= 1) { - /* We may need to skip over some bits in the interrupt register (without - * incrementing the irq value. + /* We may need to skip over some bits in the interrupt register + * (without incrementing the irq value. */ if ((valid & bit) != 0) @@ -146,9 +149,11 @@ static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context * flags registers. */ - putreg8(bit, base+HCS12_PIM_IF_OFFSET); + putreg8(bit, base + HCS12_PIM_IF_OFFSET); - /* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */ + /* Re-deliver the IRQ + * (recurses! We got here from irq_dispatch!) + */ irq_dispatch(irq, context); @@ -162,6 +167,7 @@ static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context irq++; } } + return OK; } diff --git a/arch/hc/src/m9s12/m9s12_iic.h b/arch/hc/src/m9s12/m9s12_iic.h index 09f9652b356..1688fcce0ba 100644 --- a/arch/hc/src/m9s12/m9s12_iic.h +++ b/arch/hc/src/m9s12/m9s12_iic.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_iic.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S124_M9S124_IIC_H #define __ARCH_ARM_HC_SRC_M9S124_M9S124_IIC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_IIC_IBAD_OFFSET 0x0000 /* IIC Address Register */ #define HCS12_IIC_IBFD_OFFSET 0x0001 /* IIC Frequency Divider Register */ @@ -40,7 +40,7 @@ #define HCS12_IIC_IBSR_OFFSET 0x0003 /* IIC Status Register */ #define HCS12_IIC_IBDR_OFFSET 0x0004 /* IIC Data I/O Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_IIC_IBAD (HCS12_IIC_BASE+HCS12_IIC_IBAD_OFFSET) #define HCS12_IIC_IBFD (HCS12_IIC_BASE+HCS12_IIC_IBFD_OFFSET) @@ -48,7 +48,7 @@ #define HCS12_IIC_IBSR (HCS12_IIC_BASE+HCS12_IIC_IBSR_OFFSET) #define HCS12_IIC_IBDR (HCS12_IIC_BASE+HCS12_IIC_IBDR_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* IIC Address Register */ @@ -78,16 +78,16 @@ /* IIC Data I/O Register -- 8-Bit data value */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S124_M9S124_IIC_H */ diff --git a/arch/hc/src/m9s12/m9s12_int.h b/arch/hc/src/m9s12/m9s12_int.h index 698b6724277..af65691ef0e 100644 --- a/arch/hc/src/m9s12/m9s12_int.h +++ b/arch/hc/src/m9s12/m9s12_int.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_int.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_INT_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_INT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Register Offsets *********************************************************/ -/* Register Offsets *****************************************************************/ /* Offsets relative to CORE1 */ #define HCS12_INT_ITCR_OFFSET 0x0015 /* Interrupt Test Control Register */ @@ -42,13 +43,13 @@ #define HCS12_INT_HPRIO_OFFSET 0x0003 /* Highest Priority Interrupt */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_INT_ITCR (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_INT_ITCR_OFFSET) #define HCS12_INT_ITEST (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_INT_ITEST_OFFSET) #define HCS12_INT_HPRIO (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_INT_HPRIO_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Interrupt Test Control Register Bit-Field Definitions */ @@ -69,20 +70,21 @@ #define INT_ITEST_INTE (1 << 7) /* Bit 7: Test vector 0xffxe */ /* Highest Priority Interrupt Bit-Field Definitions */ + /* Holds the least of the highest priority interrupt vector address */ #define INT_HPRIO_MASK (0xfe) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_INT_H */ diff --git a/arch/hc/src/m9s12/m9s12_mebi.h b/arch/hc/src/m9s12/m9s12_mebi.h index 278319efb04..141455a14d4 100644 --- a/arch/hc/src/m9s12/m9s12_mebi.h +++ b/arch/hc/src/m9s12/m9s12_mebi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_mebi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_MEBI_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_MEBI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Register Offsets *********************************************************/ -/* Register Offsets *****************************************************************/ /* Offsets relative to CORE1 */ #define HCS12_MEBI_PORTA_OFFSET 0x0000 /* Port A Data Register */ @@ -56,7 +57,7 @@ #define HCS12_MEBI_PORTK_OFFSET 0x0002 /* Port K Data Register */ #define HCS12_MEBI_DDRK_OFFSET 0x0003 /* Data Direction Register K */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_MEBI_PORTA (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PORTA_OFFSET) #define HCS12_MEBI_PORTB (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PORTB_OFFSET) @@ -73,15 +74,22 @@ #define HCS12_MEBI_PORTK (HCS12_REG_BASE+HCS12_CORE4_BASE+HCS12_MEBI_PORTK_OFFSET) #define HCS12_MEBI_DDRK (HCS12_REG_BASE+HCS12_CORE4_BASE+HCS12_MEBI_DDRK_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Port A Data Register Bit-Field Definitions */ + /* Port B Data Register Bit-Field Definitions */ + /* Data Direction Register A Bit-Field Definitions */ + /* Data Direction Register B Bit-Field Definitions */ + /* Port E Data Register Bit-Field Definitions */ + /* Data Direction Register E Bit-Field Definitions */ + /* Port K Data Register Bit-Field Definitions */ + /* Data Direction Register K Bit-Field Definitions */ #define MEBI_PIN(n) (1 << (n)) @@ -136,16 +144,16 @@ #define MEBI_IRQCR_IRQEN (1 << 6) /* Bit 6: External IRQ Enable */ #define MEBI_IRQCR_IRQE (1 << 7) /* Bit 7: IRQ Select Edge Sensitive Only */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_MEBI_H */ diff --git a/arch/hc/src/m9s12/m9s12_mmc.h b/arch/hc/src/m9s12/m9s12_mmc.h index a7838da11b3..ddef25bf9d8 100644 --- a/arch/hc/src/m9s12/m9s12_mmc.h +++ b/arch/hc/src/m9s12/m9s12_mmc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_mmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_MMC_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_MMC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Register Offsets *********************************************************/ -/* Register Offsets *****************************************************************/ /* Offsets relative to CORE1 */ #define HCS12_MMC_INITRM_OFFSET 0x0010 /* Internal RAM Position Register */ @@ -51,7 +52,7 @@ #define HCS12_MMC_PPAGE_OFFSET 0x0000 /* Program Page Index Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_MMC_INITRM (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_INITRM_OFFSET) #define HCS12_MMC_INITRG (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_INITRG_OFFSET) @@ -63,7 +64,7 @@ #define HCS12_MMC_MEMSIZ1 (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_MMC_MEMSIZ1_OFFSET) #define HCS12_MMC_PPAGE (HCS12_REG_BASE+HCS12_CORE4_BASE+HCS12_MMC_PPAGE_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Internal RAM Position Register Bit-Field Definitions */ @@ -138,16 +139,16 @@ #define MMC_PPAGE_PIX_SHIFT (0) /* Bits 0-5 Program Page Index Bits 5–0 */ #define MMC_PPAGE_PIX_MASK (0x3f << MMC_PPAGE_PIX_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_MMC_H */ diff --git a/arch/hc/src/m9s12/m9s12_phy.h b/arch/hc/src/m9s12/m9s12_phy.h index 4480cbd70fd..28cdd6e59d5 100644 --- a/arch/hc/src/m9s12/m9s12_phy.h +++ b/arch/hc/src/m9s12/m9s12_phy.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_phy.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,35 +16,35 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_PHY_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_PHY_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_PHY_EPHYCTL0_OFFSET 0x0000 /* Ethernet Physical Transceiver Control Register 0 */ #define HCS12_PHY_EPHYCTL1_OFFSET 0x0001 /* Ethernet Physical Transceiver Control Register 1 */ #define HCS12_PHY_EPHYSR_OFFSET 0x0002 /* Ethernet Physical Transceiver Status Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_PHY_EPHYCTL0 (HCS12_EPHY_BASE+HCS12_PHY_EPHYCTL0_OFFSET) #define HCS12_PHY_EPHYCTL1 (HCS12_EPHY_BASE+HCS12_PHY_EPHYCTL1_OFFSET) #define HCS12_PHY_EPHYSR (HCS12_EPHY_BASE+HCS12_PHY_EPHYSR_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Ethernet Physical Transceiver Control Register 0 */ @@ -67,16 +67,16 @@ #define PHY_EPHYSR_10DIS (1 << 4) /* Bit 4: EPHY Port 10BASE-T mode status */ #define PHY_EPHYSR_100DIS (1 << 5) /* Bit 5: EPHY Port 100BASE-TX mode status */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_PHY_H */ diff --git a/arch/hc/src/m9s12/m9s12_pim.h b/arch/hc/src/m9s12/m9s12_pim.h index c22a5da3cd9..685829869d1 100644 --- a/arch/hc/src/m9s12/m9s12_pim.h +++ b/arch/hc/src/m9s12/m9s12_pim.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_pim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_PIM_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_PIM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Register Offsets *********************************************************/ -/* Register Offsets *****************************************************************/ /* Friendly names for ports */ #define PIM_PORTT (0) @@ -64,7 +65,8 @@ #define HCS12_PIM_IE_OFFSET (0x0006) /* Interrupt Enable Register (PORT G, H, and J) */ #define HCS12_PIM_IF_OFFSET (0x0007) /* Interrupt Flag Register (PORT G, H, and J) */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ + /* Port register block addresses */ #define HCS12_PIM_PORT_BASE(n) (HCS12_PIM_BASE + HCS12_PIM_PORT_OFFSET(n)) @@ -149,7 +151,7 @@ #define HCS12_PIM_PORTL_PS (HCS12_PIM_PORTL_BASE + HCS12_PIM_PS_OFFSET) #define HCS12_PIM_PORTL_WOM (HCS12_PIM_PORTL_BASE + HCS12_PIM_WOM_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Port register bits (all ports) */ @@ -218,16 +220,16 @@ #define PHY_DUPLED PIM_PIN3 #define PHY_COLLED PIM_PIN4 -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_PIM_H */ diff --git a/arch/hc/src/m9s12/m9s12_sci.h b/arch/hc/src/m9s12/m9s12_sci.h index c7efe90d890..4e59b829ab5 100644 --- a/arch/hc/src/m9s12/m9s12_sci.h +++ b/arch/hc/src/m9s12/m9s12_sci.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_sci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_SCI_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_SCI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_SCI_BDH_OFFSET 0x00 /* SCI Baud Rate Register High */ #define HCS12_SCI_BDL_OFFSET 0x01 /* SCI Baud Rate Register Low */ @@ -43,7 +43,7 @@ #define HCS12_SCI_DRH_OFFSET 0x06 /* SCI Data Register High */ #define HCS12_SCI_DRL_OFFSET 0x07 /* SCI Data Register Low */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_SCI0_BDH (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_BDH_OFFSET) #define HCS12_SCI0_BDL (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_BDL_OFFSET) @@ -63,7 +63,7 @@ #define HCS12_SCI1_DRH (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_DRH_OFFSET) #define HCS12_SCI1_DRL (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_DRL_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* SCI Baud Rate Register High Bit-Field Definitions */ @@ -74,9 +74,11 @@ # define SCI_BDH_TNP_132 (0 << SCI_BDH_TNP_SHIFT) /* 1/32 */ # define SCI_BDH_TNP_116 (1 << SCI_BDH_TNP_SHIFT) /* 1/16 */ # define SCI_BDH_TNP_316 (2 << SCI_BDH_TNP_SHIFT) /* 3/16 */ + #define SCI_BDH_IREN (1 << 7) /* Bit 7: Infrared Enable */ /* SCI Baud Rate Register Low Bit-Field Definitions */ + /* This register holds the low 7 bits of the baud bits SBR[7:0] */ /* SCI Control Register 1 Bit-Field Definitions */ @@ -125,18 +127,19 @@ #define SCI_DRH_R8 (1 << 7) /* Bit 7: Received Bit 8 */ /* SCI Data Register Low Bit-Field Definitions */ + /* Receive/Transmit bits 0-7 */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_SCI_H */ diff --git a/arch/hc/src/m9s12/m9s12_serial.h b/arch/hc/src/m9s12/m9s12_serial.h index 36aa4779b98..efdc8aae9aa 100644 --- a/arch/hc/src/m9s12/m9s12_serial.h +++ b/arch/hc/src/m9s12/m9s12_serial.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_serial.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_HC_SRC_M9S12_CHIP_H #define __ARCH_HC_SRC_M9S12_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ /* Is there a SCI enabled? */ @@ -95,7 +96,8 @@ # endif #endif -/* BAUD *****************************************************************************/ +/* BAUD *********************************************************************/ + /* Baud calculations. The SCI module is driven by the BUSCLK. The SCIBR * register value divides down the BUSCLK to accomplish the required BAUD. * @@ -105,16 +107,16 @@ #define SCIBR_VALUE(b) ((HCS12_BUSCLK * (b) + ((b) << 3))/((b) << 4)) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_HC_SRC_M9S12_CHIP_H */ diff --git a/arch/hc/src/m9s12/m9s12_spi.h b/arch/hc/src/m9s12/m9s12_spi.h index f8cd7b6f392..dc6d76ce26c 100644 --- a/arch/hc/src/m9s12/m9s12_spi.h +++ b/arch/hc/src/m9s12/m9s12_spi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_SPI_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_SPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_SPI_CR1_OFFSET 0x00 /* SPI Control Register 1 */ #define HCS12_SPI_CR2_OFFSET 0x01 /* SPI Control Register 2 */ @@ -40,7 +40,7 @@ #define HCS12_SPI_SR_OFFSET 0x03 /* SPI Status Register */ #define HCS12_SPI_DR_OFFSET 0x05 /* SPI Data Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_SPI_CR1 (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_CR1_OFFSET) #define HCS12_SPI_CR2 (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_CR2_OFFSET) @@ -48,7 +48,7 @@ #define HCS12_SPI_SR (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_SR_OFFSET) #define HCS12_SPI_DR (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_DR_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* SPI Control Register 1 Bit-Field Definitions */ @@ -82,18 +82,19 @@ #define SPI_SR_SPIF (1 << 7) /* Bit 7: SPIF Interrupt */ /* SPI Data Register Bit-Field Definitions */ + /* 8-bit SPI data register */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_SPI_H */ diff --git a/arch/hc/src/m9s12/m9s12_tim.h b/arch/hc/src/m9s12/m9s12_tim.h index ae23424cdd7..f879886c778 100644 --- a/arch/hc/src/m9s12/m9s12_tim.h +++ b/arch/hc/src/m9s12/m9s12_tim.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/hc/src/m9s12/m9s12_tim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_TIM_H #define __ARCH_ARM_HC_SRC_M9S12_M9S12_TIM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define HCS12_TIM_TIOS_OFFSET 0x0000 /* Timer Input Capture/Output Compare Select */ #define HCS12_TIM_CFORC_OFFSET 0x0001 /* Timer Compare Force Register */ @@ -62,7 +62,7 @@ #define HCS12_TIM_PACNTLO_OFFSET 0x0023 /* Pulse Accumulator Count Register */ #define HCS12_TIM_TIMTST2_OFFSET 0x002d /* Timer Test Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define HCS12_TIM_TIOS (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIOS_OFFSET) #define HCS12_TIM_CFORC (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_CFORC_OFFSET) @@ -92,7 +92,7 @@ #define HCS12_TIM_PACNTLO (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET) #define HCS12_TIM_TIMTST2 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ /* Timer Input Capture/Output Compare Select Bit-Field Definitions */ @@ -111,7 +111,10 @@ #define TIM_OC7D(n) (1 << (n)) /* Output Compare 7 Data */ /* Timer Count HI/LO Register Bit-Field Definitions */ -/* These two registers form a 16-bit timer up counter and have no internal bit-fields */ + +/* These two registers form a 16-bit timer up counter and have no internal + * bit-fields + */ /* Timer System Control Register 1 Bit-Field Definitions */ @@ -169,6 +172,7 @@ # define TIM_TSCR2_PR_DIV32 (5 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/32 */ # define TIM_TSCR2_PR_DIV64 (6 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/64 */ # define TIM_TSCR2_PR_DIV128 (7 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/128 */ + #define TIM_TSCR2_TCRE (1 << 3) /* Timer Counter Reset Enable */ #define TIM_TSCR2_TOI (1 << 7) /* Timer Overflow Interrupt Enable */ @@ -180,8 +184,13 @@ #define TIM_TFLG2_TOF (1 << 7) /* Timer Overflow Flag */ -/* Timer Input Capture/Output Compare HI/LO Register 4-7 Bit-Field Definitions */ -/* These register pairs form a 16-bit timer compare values and have no internal bit-fields */ +/* Timer Input Capture/Output Compare HI/LO Register 4-7 Bit-Field + * Definitions + */ + +/* These register pairs form a 16-bit timer compare values and have no + * internal bit-fields + */ /* 16-Bit Pulse Accumulator Control Register Bit-Field Definitions */ @@ -195,6 +204,7 @@ # define TIM_PACTL_PACLK (1 << TIM_PACTL_CLK_SHIFT) /* Use PACLK as input to timer counter clock */ # define TIM_PACTL_DIV256 (2 << TIM_PACTL_CLK_SHIFT) /* Use PACLK/256 as timer counter clock frequency */ # define TIM_PACTL_DIV64K (3 << TIM_PACTL_CLK_SHIFT) /* Use PACLK/65536 as timer counter clock frequency */ + #define TIM_PACTL_PIN_SHIFT (4) /* Pin action */ #define TIM_PACTL_PIN_MASK (3 << TIM_PACTL_PIN_SHIFT) # define TIM_PACTL_PEDGE (1 << TIM_PACTL_PIN_SHIFT) /* Pulse Accumulator Edge Control */ @@ -203,6 +213,7 @@ # define TIM_PACTL_RISING (1 << TIM_PACTL_PIN_SHIFT) /* Rising edge */ # define TIM_PACTL_DIV64HI (2 << TIM_PACTL_PIN_SHIFT) /* Div. by 64 clock enabled with pin high level */ # define TIM_PACTL_DIV64LO (3 << TIM_PACTL_PIN_SHIFT) /* Div. by 64 clock enabled with pin low level */ + #define TIM_PACTL_PAEN (1 << 6) /* Pulse Accumulator System Enable */ /* Pulse Accumulator Flag Register Bit-Field Definitions */ @@ -211,21 +222,25 @@ #define TIM_PAFLG_PAOVF (1 << 1) /* Pulse Accumulator Overflow Flag */ /* Pulse Accumulator Count HI/LO Register Bit-Field Definitions */ -/* This register pair forms a 16-bit pulse accumulator value with no internal bit-fields */ + +/* This register pair forms a 16-bit pulse accumulator value with no internal + * bit-fields + */ /* Timer Test Register Bit-Field Definitions */ + /* Not documented */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_TIM_H */ diff --git a/arch/hc/src/m9s12/m9s12_timerisr.c b/arch/hc/src/m9s12/m9s12_timerisr.c index 01f1efa883b..1d289db9dcc 100644 --- a/arch/hc/src/m9s12/m9s12_timerisr.c +++ b/arch/hc/src/m9s12/m9s12_timerisr.c @@ -66,7 +66,8 @@ /* Pick the smallest value of B for which: * - * OSCCLK/(MAX_MODCNT*(2**(B+9))) >= CLK_TCK >= OSCCLK/(MIN_MODCNT*(2**(B+9))) + * OSCCLK/(MAX_MODCNT*(2**(B+9))) >= CLK_TCK >= + * OSCCLK/(MIN_MODCNT*(2**(B+9))) */ #if CLK_TCK >= HCS12_OSCCLK/(MAX_MODCNT*1024) && HCS12_OSCCLK/(MIN_MODCNT*1024) @@ -151,7 +152,8 @@ void up_timer_initialize(void) * uint32_t operations). */ - tmp = MODCNT_VALUE << CRG_RTICTL_MODCNT_SHIFT | PRER_VALUE << CRG_RTICTL_PRER_SHIFT; + tmp = MODCNT_VALUE << CRG_RTICTL_MODCNT_SHIFT | + PRER_VALUE << CRG_RTICTL_PRER_SHIFT; putreg8((uint8_t)tmp, HCS12_CRG_RTICTL); /* Attach the timer interrupt vector */