From 27d5a1b4b76010472aaa5d43bd1dda1700fa2a84 Mon Sep 17 00:00:00 2001 From: chao an Date: Mon, 17 Feb 2025 11:00:29 +0800 Subject: [PATCH] arm/memory_barrier: fix build warning on GCC14 nuttx/include/arch/spinlock.h:66:9: warning: "UP_DSB" redefined 66 | #define UP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory") | ^~~~~~ In file included from nuttx/include/arch/barriers.h:37, from nuttx/include/arch/spinlock.h:34: nuttx/include/arch/armv8-m/barriers.h:42:9: note: this is the location of the previous definition 42 | #define UP_DSB() arm_dsb(15) | ^~~~~~ nuttx/include/arch/spinlock.h:67:9: warning: "UP_DMB" redefined 67 | #define UP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory") | ^~~~~~ nuttx/include/arch/armv8-m/barriers.h:41:9: note: this is the location of the previous definition 41 | #define UP_DMB() arm_dmb() | ^~~~~~ Signed-off-by: chao an --- arch/arm/include/spinlock.h | 32 ++++++-------------------------- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 4aa024bee8c..a2ca0006137 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -42,33 +42,13 @@ #define SP_UNLOCKED 0 /* The Un-locked state */ #define SP_LOCKED 1 /* The Locked state */ -/* Memory barriers for use with NuttX spinlock logic - * - * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all - * explicit memory accesses that appear in program order before the DMB - * instruction are observed before any explicit memory accesses that appear - * in program order after the DMB instruction. It does not affect the - * ordering of any other instructions executing on the processor - * - * dmb st - Data memory barrier. Wait for stores to complete. - * - * Data Synchronization Barrier (DSB) acts as a special kind of memory - * barrier. No instruction in program order after this instruction executes - * until this instruction completes. This instruction completes when: (1) All - * explicit memory accesses before this instruction complete, and (2) all - * Cache, Branch predictor and TLB maintenance operations before this - * instruction complete. - * - * dsb sy - Data syncrhonization barrier. Assures that the CPU waits until - * all memory accesses are complete - */ - -#define UP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory") -#define UP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory") - #ifdef CONFIG_ARM_HAVE_WFE_SEV -#define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory") -#define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory") +# ifndef UP_WFE +# define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory") +# endif +# ifndef UP_SEV +# define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory") +# endif #endif /****************************************************************************