From 26923b39de3fe5c5e0589d09a836f748e0918772 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 17 Mar 2015 11:19:46 -0600 Subject: [PATCH] SAMV7 EMAC: Fix range of MCK dividers --- arch/arm/src/samv7/sam_emac.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 12e3801152c..53df6733d31 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -3850,15 +3850,23 @@ static int sam_phyinit(struct sam_emac_s *priv) regval &= ~EMAC_NCFGR_CLK_MASK; mck = BOARD_MCK_FREQUENCY; - if (mck > (160*1000*1000)) + if (mck > (240*1000*1000)) { ndbg("ERROR: Cannot realize PHY clock\n"); return -EINVAL; } - else if (mck > (80*1000*1000)) + else if (mck > (160*1000*1000)) + { + regval |= EMAC_NCFGR_CLK_DIV96; /* MCK divided by 64 (MCK up to 240 MHz) */ + } + else if (mck > (120*1000*1000)) { regval |= EMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */ } + else if (mck > (80*1000*1000)) + { + regval |= EMAC_NCFGR_CLK_DIV48; /* MCK divided by 64 (MCK up to 120 MHz) */ + } else if (mck > (40*1000*1000)) { regval |= EMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */