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arch/arm/src/stm32: CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW option applies only to F2 and F4.

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This commit is contained in:
Gregory Nutt 2018-06-05 10:20:50 -06:00
parent 1a03201600
commit 1f2e7f4b52
3 changed files with 2 additions and 45 deletions
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3
arch/arm/src/stm32/Kconfig
View file

@ -2927,9 +2927,9 @@ endmenu
config STM32_FLASH_PREFETCH
bool "Enable FLASH Pre-fetch"
depends on STM32_STM32F207 || STM32_STM32F4XXX
default y if STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446
default n
depends on STM32_STM32F207 || STM32_STM32F4XXX
---help---
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
@ -2938,6 +2938,7 @@ config STM32_FLASH_PREFETCH
config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
bool "Workaround for FLASH data cache corruption"
default n
depends on STM32_STM32F20XX || STM32_STM32F4XXX
---help---
Enable the workaround to fix flash data cache corruption when reading
from one flash bank while writing on other flash bank. See your STM32

26
arch/arm/src/stm32/stm32f10xxf30xx_flash.c
View file

@ -128,24 +128,6 @@ static void flash_lock(void)
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
}
#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
static void data_cache_disable(void)
{
modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0);
}
static void data_cache_enable(void)
{
/* Reset data cache */
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST);
/* Enable data cache */
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN);
}
#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
/************************************************************************************
* Public Functions
************************************************************************************/
@ -321,10 +303,6 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
flash_unlock();
#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
data_cache_disable();
#endif
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2)
@ -354,10 +332,6 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
data_cache_enable();
#endif
sem_unlock();
return written;
}

18
arch/arm/src/stm32/stm32l15xx_flash.c
View file

@ -121,24 +121,6 @@ static inline void sem_unlock(void)
nxsem_post(&g_sem);
}
#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
static void data_cache_disable(void)
{
modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0);
}
static void data_cache_enable(void)
{
/* Reset data cache */
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST);
/* Enable data cache */
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN);
}
#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
static void stm32_eeprom_unlock(void)
{
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)