AmebaZ2: Add soc src code

Add soc src code for rtl8720c

Signed-off-by: Jerry_tang <jerry_tang@realsil.com.cn>

arch/arm/src/rtl8720c/Kconfig

@@ -0,0 +1,395 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_CUSTOM
+
+comment "AMEBA Configuration Options"
+
+choice
+	prompt "AMEBA Chip Selection"
+	default ARCH_CHIP_AMEBAZ
+
+config ARCH_CHIP_AMEBAZ
+	bool "AmebaZ"
+	select ARCH_CORTEXM33
+
+endchoice
+
+choice
+	prompt "AMEBAZ Chip Type Selection"
+	default ARCH_CHIP_AMEBAZ_C_CUT
+	depends on ARCH_CHIP_AMEBAZ
+
+config ARCH_CHIP_AMEBAZ_C_CUT
+	bool "AmebaZ_C_CUT"
+
+config ARCH_CHIP_AMEBAZ_D_CUT
+	bool "AmebaZ_D_CUT"
+
+endchoice
+
+config AMEBA_NR_IRQS
+	int "Interrupt Number"
+
+menuconfig AMEBA_UART
+	bool "AMEBA UART Chip support"
+	select ARCH_HAVE_SERIAL_TERMIOS
+	default n
+
+if AMEBA_UART
+
+config AMEBA_UART0
+	bool "AMEBA UART0"
+	default n
+
+if AMEBA_UART0
+
+config AMEBA_UART0_TX_PIN
+	int "AMEBA UART0 tx pin"
+
+config AMEBA_UART0_RX_PIN
+	int "AMEBA UART0 rx pin"
+
+config AMEBA_UART0_BAUD
+	int "AMEBA UART0 BAUD"
+	default 115200
+
+config AMEBA_UART0_PARITY
+	int "AMEBA UART0 parity"
+	default 0
+	range 0 2
+	---help---
+		AMEBA UART0 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config AMEBA_UART0_BITS
+	int "AMEBA UART0 number of bits"
+	default 8
+	---help---
+		AMEBA UART0 number of bits.  Default: 8
+
+config AMEBA_UART0_2STOP
+	int "AMEBA UART0 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config AMEBA_UART0_RXBUFSIZE
+	int "AMEBA UART0 Rx buffer size"
+	default 256
+	---help---
+		AMEBA UART0 Rx buffer size.  Default: 256
+
+config AMEBA_UART0_TXBUFSIZE
+	int "AMEBA UART0 Tx buffer size"
+	default 256
+	---help---
+		AMEBA UART0 Tx buffer size.  Default: 256
+
+config AMEBA_UART0_IFLOWCONTROL
+	bool "AMEBA UART0 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable AMEBA UART0 RTS flow control
+
+config AMEBA_UART0_OFLOWCONTROL
+	bool "AMEBA UART0 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable AMEBA UART0 CTS flow control
+
+endif # AMEBA_UART0
+
+config AMEBA_UART1
+	bool "AMEBA UART1"
+	default n
+
+if AMEBA_UART1
+
+config AMEBA_UART1_TX_PIN
+	int "AMEBA UART1 tx pin"
+
+config AMEBA_UART1_RX_PIN
+	int "AMEBA UART1 rx pin"
+
+config AMEBA_UART1_BAUD
+	int "AMEBA UART1 BAUD"
+	default 115200
+
+config AMEBA_UART1_PARITY
+	int "AMEBA UART1 parity"
+	default 0
+	range 0 2
+	---help---
+		AMEBA UART1 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config AMEBA_UART1_BITS
+	int "AMEBA UART1 number of bits"
+	default 8
+	---help---
+		AMEBA UART1 number of bits.  Default: 8
+
+config AMEBA_UART1_2STOP
+	int "AMEBA UART1 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config AMEBA_UART1_RXBUFSIZE
+	int "AMEBA UART1 Rx buffer size"
+	default 256
+	---help---
+		AMEBA UART1 Rx buffer size.  Default: 256
+
+config AMEBA_UART1_TXBUFSIZE
+	int "AMEBA UART1 Tx buffer size"
+	default 256
+	---help---
+		AMEBA UART1 Tx buffer size.  Default: 256
+
+config AMEBA_UART1_IFLOWCONTROL
+	bool "AMEBA UART1 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable AMEBA UART1 RTS flow control
+
+config AMEBA_UART1_OFLOWCONTROL
+	bool "AMEBA UART1 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable AMEBA UART1 CTS flow control
+
+endif # AMEBA_UART1
+
+config AMEBA_UART2
+	bool "AMEBA UART2"
+	default n
+
+if AMEBA_UART2
+
+config AMEBA_UART2_TX_PIN
+	int "AMEBA UART2 tx pin"
+
+config AMEBA_UART2_RX_PIN
+	int "AMEBA UART2 rx pin"
+
+config AMEBA_UART2_BAUD
+	int "AMEBA UART2 BAUD"
+	default 115200
+
+config AMEBA_UART2_PARITY
+	int "AMEBA UART2 parity"
+	default 0
+	range 0 2
+	---help---
+		AMEBA UART2 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config AMEBA_UART2_BITS
+	int "AMEBA UART2 number of bits"
+	default 8
+	---help---
+		AMEBA UART2 number of bits.  Default: 8
+
+config AMEBA_UART2_2STOP
+	int "AMEBA UART2 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config AMEBA_UART2_RXBUFSIZE
+	int "AMEBA UART2 Rx buffer size"
+	default 256
+	---help---
+		AMEBA UART2 Rx buffer size.  Default: 256
+
+config AMEBA_UART2_TXBUFSIZE
+	int "AMEBA UART2 Tx buffer size"
+	default 256
+	---help---
+		AMEBA UART2 Tx buffer size.  Default: 256
+
+config AMEBA_UART2_IFLOWCONTROL
+	bool "AMEBA UART2 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable AMEBA UART2 RTS flow control
+
+config AMEBA_UART2_OFLOWCONTROL
+	bool "AMEBA UART2 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable AMEBA UART2 CTS flow control
+
+endif # AMEBA_UART2
+
+config AMEBA_UART3
+	bool "AMEBA UART3"
+	default n
+
+if AMEBA_UART3
+
+config AMEBA_UART3_TX_PIN
+	int "AMEBA UART3 tx pin"
+
+config AMEBA_UART3_RX_PIN
+	int "AMEBA UART3 rx pin"
+
+config AMEBA_UART3_BAUD
+	int "AMEBA UART3 BAUD"
+	default 115200
+
+config AMEBA_UART3_PARITY
+	int "AMEBA UART3 parity"
+	default 0
+	range 0 2
+	---help---
+		AMEBA UART3 parity.  0=None, 1=Odd, 2=Even.  Default: None
+
+config AMEBA_UART3_BITS
+	int "AMEBA UART3 number of bits"
+	default 8
+	---help---
+		AMEBA UART3 number of bits.  Default: 8
+
+config AMEBA_UART3_2STOP
+	int "AMEBA UART3 two stop bits"
+	default 0
+	---help---
+		0=1 stop bit, 1=Two stop bits.  Default: 1 stop bit
+
+config AMEBA_UART3_RXBUFSIZE
+	int "AMEBA UART3 Rx buffer size"
+	default 256
+	---help---
+		AMEBA UART3 Rx buffer size.  Default: 256
+
+config AMEBA_UART3_TXBUFSIZE
+	int "AMEBA UART3 Tx buffer size"
+	default 256
+	---help---
+		AMEBA UART3 Tx buffer size.  Default: 256
+
+config AMEBA_UART3_IFLOWCONTROL
+	bool "AMEBA UART3 RTS flow control"
+	default n
+	select SERIAL_IFLOWCONTROL
+	---help---
+		Enable AMEBA UART3 RTS flow control
+
+config AMEBA_UART3_OFLOWCONTROL
+	bool "AMEBA UART3 CTS flow control"
+	default n
+	select SERIAL_OFLOWCONTROL
+	---help---
+		Enable AMEBA UART3 CTS flow control
+
+endif # AMEBA_UART3
+
+choice
+	prompt "AMEBA Serial Console"
+	default AMEBA_NO_SERIAL_CONSOLE
+	depends on DEV_CONSOLE
+
+config AMEBA_UART0_SERIAL_CONSOLE
+	bool "AMEBA UART0 serial console"
+	depends on AMEBA_UART0
+	select SERIAL_CONSOLE
+
+config AMEBA_UART1_SERIAL_CONSOLE
+	bool "AMEBA UART1 serial console"
+	depends on AMEBA_UART1
+	select SERIAL_CONSOLE
+
+config AMEBA_UART2_SERIAL_CONSOLE
+	bool "AMEBA UART2 serial console"
+	depends on AMEBA_UART2
+	select SERIAL_CONSOLE
+
+config AMEBA_UART3_SERIAL_CONSOLE
+	bool "AMEBA UART3 serial console"
+	depends on AMEBA_UART3
+	select SERIAL_CONSOLE
+
+config AMEBA_NO_SERIAL_CONSOLE
+	bool "No AMEBA serial console"
+
+endchoice # AMEBA Serial Console
+
+config AMEBA_SUPRESS_CONFIG
+	bool "Suppress AMEBA configuration"
+	default n
+
+config AMEBA_SUPRESS_INITIAL_CONFIG
+	bool "Suppress initial AMEBA configuration"
+	depends on !AMEBA_SUPRESS_CONFIG
+	default n
+	---help---
+		This option is useful, for example, if you are using a bootloader
+		that configures the AMEBA_UART.  In that case, you may want to
+		just leave the existing console configuration in place.  Default: n
+
+config SERIAL_UART_ARCH_MMIO
+	bool "Platform access register through the memory mapping"
+	default n
+
+config SERIAL_UART_ARCH_IOCTL
+	bool "Platform has own custom IOCTL"
+	default n
+
+config AMEBA_REGINCR
+	int "Address increment between AMEBA registers"
+	default 1
+	---help---
+		The address increment between AMEBA registers.  Options are 1, 2, or 4.
+		Default: 1
+
+config AMEBA_REGWIDTH
+	int "Bit width of AMEBA registers"
+	default 8
+	---help---
+		The bit width of registers.  Options are 8, 16, or 32. Default: 8
+
+config AMEBA_ADDRWIDTH
+	int "Address width of AMEBA registers"
+	default 8
+	---help---
+		The bit width of registers.  Options are 8, 16, or 32. Default: 8
+
+config AMEBA_HCI_DEV_NAME
+	string "Device Name of UART Device for Bluetooth"
+	default "/dev/ttyS2"
+	---help---
+		This option specifies the name of UART device to be used
+		for Bluetooth.
+
+config AMEBA_HCI_PROXY_DEV_NAME
+	string "Device Name of UART Device for Bluetooth"
+	default "/dev/ttyBT"
+	---help---
+		This option specifies the name of UART device to be used
+		for Bluetooth.
+
+endif # AMEBA_UART
+
+config IEEE80211_REALTEK_AMEBAZ
+	bool "Realtek amebaZ chip support"
+	default n
+
+if IEEE80211_REALTEK_AMEBAZ
+
+config IEEE80211_REALTEK_AMEBAZ_RECV_STACKSIZE
+  int "Realtek amebaZ recv stack size"
+  default 4096
+  ---help---
+    Default recv stack size
+
+endif
+
+endif # ARCH_CHIP_CUSTOM

arch/arm/src/rtl8720c/Make.defs

@@ -0,0 +1,76 @@
+############################################################################
+# arch/arm/src/rtl8720c/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# arch/arm/src/common
+#
+CMN_CSRCS += arm_checkstack.c arm_createstack.c arm_exit.c arm_hostfs.c
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_modifyreg8.c
+CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_pthread_start.c
+CMN_CSRCS += arm_puts.c arm_releasestack.c arm_semi_syslog.c
+CMN_CSRCS += arm_stackframe.c arm_task_start.c arm_usestack.c arm_vfork.c
+
+CMN_ASRCS += arm_exception.S
+
+# arch/arm/src/armv8-m
+#
+CMN_ASRCS += arm_fetchadd.S arm_fpu.S arm_setjmp.S
+CMN_ASRCS += arm_fullcontextrestore.S arm_saveusercontext.S
+CMN_ASRCS += arm_switchcontext.S arm_testset.S vfork.S
+
+CMN_UASRCS += arm_signal_handler.S
+
+CMN_CSRCS += arm_assert.c arm_blocktask.c arm_cache.c arm_copyarmstate.c
+CMN_CSRCS += arm_copyfullstate.c arm_doirq.c arm_hardfault.c arm_initialstate.c
+CMN_CSRCS += arm_itm_syslog.c arm_memfault.c arm_mpu.c arm_ramvec_attach.c
+CMN_CSRCS += arm_ramvec_initialize.c arm_releasepending.c arm_reprioritizertr.c
+CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_signal_dispatch.c
+CMN_CSRCS += arm_stackcheck.c arm_svcall.c arm_systick.c arm_unblocktask.c
+
+# arch/arm/src/rtl8720c
+#
+CHIP_CSRCS += ameba_nvic.c ameba_heap.c ameba_idle.c ameba_uart.c ameba_start.c ameba_vectors.c
+CHIP_CSRCS += ameba_efuse.c ameba_flash.c ameba_wdt.c ameba_hci.c
+
+CHIP_ASRCS += ameba_lto.S
+
+# arch/arm/src/rtl8720c/8710c/fwlib/source
+#
+CHIP_CSRCS += hal_efuse.c hal_flash.c hal_misc.c hal_spic.c hal_ssi.c hal_uart.c
+
+CFLAGS += -I$(TOPDIR)/arch/arm/include/rtl8720c
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/cmsis/cmsis-core/include
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/cmsis/rtl8710c/include
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/app/rtl_printf/include
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/app/stdio_port
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/misc/utilities/include
+CFLAGS += -I$(TOPDIR)/arch/arm/src/rtl8720c/8710c/fwlib/include
+
+CFLAGS += -Wno-attributes
+
+ifeq ($(CONFIG_IEEE80211_REALTEK_AMEBAZ),y)
+CHIP_CSRCS += amebaZ.c amebaz_driver.c amebaz_netdev.c amebaz_depend.c amebaz_wlan.c ameba_func.c
+CHIP_CSRCS += amebaz_hci_board.c amebaz_coex.c amebaz_firmware.c
+endif # CONFIG_IEEE80211_REALTEK_AMEBAZ
+
+VPATH += chip/8710c
+VPATH += chip/8710c/fwlib/source/ram
+VPATH += chip/8710c/fwlib/source/ram_s
+VPATH += chip/8710c/fwlib/source/ram_ns

arch/arm/src/rtl8720c/Toolchain.defs

@@ -0,0 +1,101 @@
+############################################################################
+# arch/arm/src/rtl8720c/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
+  ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT)}"
+else
+  ARCHSCRIPT = -T$(LDSCRIPT)
+endif
+
+include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs
+
+LD = $(CROSSDEV)gcc
+
+ARCHOPTIMIZATION =
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+# enable precise stack overflow tracking
+ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
+  INSTRUMENTATIONDEFINES += -finstrument-functions -ffixed-r10
+endif
+
+ifeq ($(CONFIG_STACK_CANARIES),y)
+  ARCHOPTIMIZATION += -fstack-protector-all
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+  ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
+ifneq ($(CONFIG_ARMV8M_STACKCHECK),y)
+  #ARCHOPTIMIZATION += -flto -fuse-linker-plugin
+endif
+endif
+
+ARCHCFLAGS = -fno-builtin -march=armv8-m.main+dsp -mthumb -mfloat-abi=soft -D__thumb2__ -g -gdwarf-3 -Os  -fno-tree-scev-cprop
+ARCHCXXFLAGS = -fno-builtin -nostdinc++ -std=c++11
+ifneq ($(CONFIG_CXX_EXCEPTION),y)
+  ARCHCXXFLAGS += -fno-exceptions -fcheck-new -fno-rtti
+endif
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CFLAGS += -I$(TOPDIR)/arch/$(CONFIG_ARCH)/src/rtl8720c
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+# ELF module definitions
+
+CELFFLAGS = $(CFLAGS) -mlong-calls -fno-common
+CXXELFFLAGS = $(CXXFLAGS) -mlong-calls -fno-common
+AELFFLAGS = $(AFLAGS)
+LDELFFLAGS = -r -e main -Bstatic $(LDFLAGS)
+LDELFFLAGS += -T $(TOPDIR)/binfmt/libelf/gnu-elf.ld
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS) -mlong-calls -fno-common
+
+LDMODULEFLAGS = -r -e module_initialize $(LDFLAGS)
+ifeq ($(WINTOOL),y)
+  LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
+else
+  LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
+endif
+
+LDSTARTGROUP = -Wl,--start-group
+LDENDGROUP   = -Wl,--end-group
+
+ifeq ($(filter -nuttx-, $(CROSSDEV)),)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  LDFLAGS += -Wl,--gc-sections
+endif
+
+EXTRA_LIBS += -l_soc_is
+EXTRA_LIBS += -l_wlan

arch/arm/src/rtl8720c/amebaZ.c

@@ -0,0 +1,47 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaZ.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/timers/arch_timer.h>
+#include "systick.h"
+#include "hal_syson.h"
+#include "hal_wdt.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_AMEBAZ
+void up_timer_initialize(void)
+{
+  up_timer_set_lowerhalf(systick_initialize(true, 100000000, -1));
+}
+
+void ameba_reset(int status)
+{
+  hal_sys_set_fast_boot(0, 0);
+  hal_misc_rst_by_wdt();
+}
+
+#endif /* CONFIG_ARCH_CHIP_AMEBAZ */

arch/arm/src/rtl8720c/ameba_efuse.c

@@ -0,0 +1,224 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_efuse.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hal_api.h"
+#include "hal_efuse.h"
+#include "hal_efuse_nsc.h"
+#include "platform_conf.h"
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if CONFIG_EFUSE_EN
+/* #define EFUSE_LOGICAL_SIM */
+
+#define EFUSE_LOGICAL_MAP_SIZE 512
+#define EFUSE_LOGICAL_MAP_HW_SIZE 0xd0 /* sync with EFUSE_OOB_PROTECT_BYTES */
+#define EFUSE_LOGICAL_SBLOCK_OFFSET 0x19
+#ifdef EFUSE_LOGICAL_SIM
+uint8_t ameba_efuse_sim_map[256];
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int ameba_efuse_logical_read(uint16_t laddr, uint16_t size, uint8_t *pbuf)
+{
+  uint8_t offset;
+  uint8_t wden;
+  uint8_t header;
+  uint8_t extheader;
+  uint8_t data;
+  uint16_t phy_addr = 0;
+  uint16_t i;
+  uint32_t ret;
+  if (!pbuf)
+    {
+      return -EIO;
+    }
+
+  rtw_memset(pbuf, 0xff, size);
+  while (phy_addr < EFUSE_LOGICAL_MAP_HW_SIZE)
+    {
+      /* First two bytes are reserved for physical */
+
+      if (phy_addr == 0 || phy_addr == 1)
+        {
+          phy_addr++;
+          continue;
+        }
+
+#ifdef EFUSE_LOGICAL_SIM
+      static int map_inited = 0;
+      if (!map_inited)
+        {
+          map_inited = 1;
+          for (i = 0; i < EFUSE_LOGICAL_MAP_HW_SIZE; i++)
+            {
+              hal_efuse_read(i, &ameba_efuse_sim_map[i],
+                             LDO_OUT_DEFAULT_VOLT);
+            }
+        }
+
+      ret = _TRUE;
+      header = ameba_efuse_sim_map[phy_addr++];
+#else
+      ret = hal_efuse_read(phy_addr++, &header, LDO_OUT_DEFAULT_VOLT);
+#endif
+      if (ret != _TRUE)
+        {
+          return -EIO;
+        }
+
+      if (header == 0xff)
+        {
+          break;
+        }
+
+      /* Check PG header for section num. */
+
+      if ((header & 0x1f) == 0x0f)
+        {
+          /* extended header */
+
+          offset = (header & 0xe0) >> 5;
+#ifdef EFUSE_LOGICAL_SIM
+          ret = _TRUE;
+          extheader = ameba_efuse_sim_map[phy_addr++];
+#else
+          ret = hal_efuse_read(phy_addr++, &extheader, LDO_OUT_DEFAULT_VOLT);
+#endif
+          if (ret != _TRUE)
+            {
+              return -EIO;
+            }
+
+          if (((extheader & 0x0f) == 0x0f))
+            {
+              continue;
+            }
+
+          offset |= ((extheader & 0xf0) >> 1);
+          wden = (extheader & 0x0f);
+        }
+
+      else
+        {
+          offset = ((header >> 4) & 0x0f);
+          wden = (header & 0x0f);
+        }
+
+      /* One section has 8 bytes data, logical map has 512/8 = 64 sections */
+
+      if (offset < (EFUSE_LOGICAL_MAP_SIZE >> 3))
+        {
+          uint16_t addr = 0;
+
+          /* Get word enable value from PG header */
+
+          addr = offset * 8;
+
+          /* Each section has 4 words data */
+
+          for (i = 0; i < 4; i++)
+            {
+              /* Check word enable condition in the section */
+
+              if (!(wden & (0x01 << i)))
+                {
+#ifdef EFUSE_LOGICAL_SIM
+                  ret = _TRUE;
+                  data = ameba_efuse_sim_map[phy_addr++];
+#else
+                  ret = hal_efuse_read(phy_addr++, &data,
+                                       LDO_OUT_DEFAULT_VOLT);
+#endif
+                  if (ret != _TRUE)
+                    {
+                      return -EIO;
+                    }
+
+                  if (addr >= laddr && addr < (laddr + size))
+                    {
+                      pbuf[addr - laddr] = data;
+                    }
+
+#ifdef EFUSE_LOGICAL_SIM
+                  ret = _TRUE;
+                  data = ameba_efuse_sim_map[phy_addr++];
+#else
+                  ret = hal_efuse_read(phy_addr++, &data,
+                                       LDO_OUT_DEFAULT_VOLT);
+#endif
+                  if (ret != _TRUE)
+                    {
+                      return -EIO;
+                    }
+
+                  if ((addr + 1) >= laddr && (addr + 1) < (laddr + size))
+                    {
+                      pbuf[addr + 1 - laddr] = data;
+                    }
+                }
+
+              addr += 2;
+            }
+        }
+
+      else
+        {
+          uint8_t word_cnts = 0;
+          if (!(wden & BIT(0)))
+            {
+              word_cnts++;  /* 0 : write enable */
+            }
+
+          if (!(wden & BIT(1)))
+            {
+              word_cnts++;
+            }
+
+          if (!(wden & BIT(2)))
+            {
+              word_cnts++;
+            }
+
+          if (!(wden & BIT(3)))
+            {
+              word_cnts++;
+            }
+
+          phy_addr += word_cnts * 2;
+        }
+    }
+
+  /* return used bytes */
+
+  return phy_addr - EIO;
+}
+
+#endif

arch/arm/src/rtl8720c/ameba_efuse.h

@@ -0,0 +1,48 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_efuse.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_AMEBA_HCI_EFUSE_H
+#define __INCLUDE_AMEBA_HCI_EFUSE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* #include "device.h" */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+int ameba_efuse_logical_read(uint16_t laddr, uint16_t size, uint8_t *pbuf);
+int ameba_efuse_logical_write(uint16_t addr, uint16_t cnts, uint8_t *data);
+int ameba_efuse_fw_verify_enable(void);
+int ameba_efuse_fw_verify_check(void);
+int ameba_efuse_boot_message_disable(void);
+int ameba_efuse_boot_message_enable(void);
+#endif /* __INCLUDE_AMEBA_FLASH_H */

arch/arm/src/rtl8720c/ameba_flash.c

@@ -0,0 +1,335 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_flash.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/mtd/mtd.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/fs/partition.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "ameba_flash.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Identifies the flash sector and block size */
+
+#define AMEBA_SECTOR_SHIFT           (12)
+#define AMEBA_SECTOR_SIZE            (1 << 12)     /* Sector size 1 << 12 = 4KB */
+#define AMEBA_PAGE_SHIFT             (8)
+#define AMEBA_PAGE_SIZE              (1 << 8)      /* Block size 1 << 8 = 256B */
+
+/* Flash Layout */
+
+#define AMEBA_SECTOR_TOTAL_SIZE      (2048 * 1024) /* Total flash size */
+#define AMEBA_SECTOR_SYSTEM_SIZE     (16   * 1024)
+#define AMEBA_SECTOR_BOOT_SIZE       (32   * 1024)
+#define AMEBA_SECTOR_FIRMWARE1_SIZE  (864  * 1024)
+#define AMEBA_SECTOR_FIRMWARE2_SIZE  (864  * 1024)
+#define AMEBA_SECTOR_OTA_SIZE        (236  * 1024)
+#define AMEBA_SECTOR_DATA_SIZE       (24   * 1024)
+#define AMEBA_SECTOR_BLUETOOTH_SIZE  (12   * 1024)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum
+{
+  SPICONEIOMODE = 0,       /* !< Define One IO mode, 1-1-1 */
+  SPICDUALOUTPUTMODE = 1,  /* !< Define Dual Output mode, 1-1-2 */
+  SPICDUALIOMODE = 2,      /* !< Define Dual IO mode, 1-2-2 */
+  SPICQUADOUTPUTMODE = 3,  /* !< Define Quad Output mode, 1-1-4 */
+  SPICQUADIOMODE = 4,      /* !< Define Quad IO mode, 1-4-4 */
+  SPICQPIMODE = 5,         /* !< Define QPI mode, 4-4-4 */
+};
+
+struct ameba_flash_dev_s
+{
+  struct mtd_dev_s  mtd;
+  void              *adaptor;
+  uint32_t baseaddr;
+  uint16_t nsectors;
+};
+
+extern const hal_flash_func_stubs_t hal_flash_stubs;
+extern hal_spic_adaptor_t           hal_spic_adaptor;
+extern hal_spic_adaptor_t           *pglob_spic_adaptor;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct partition_s ptable[5] =
+{
+  {
+    .name       = "fw1",
+    .firstblock = AMEBA_SECTOR_SYSTEM_SIZE +
+    AMEBA_SECTOR_BOOT_SIZE,
+    .nblocks    = AMEBA_SECTOR_FIRMWARE1_SIZE,
+  },
+  {
+    .name       = "fw2",
+    .firstblock = AMEBA_SECTOR_SYSTEM_SIZE +
+    AMEBA_SECTOR_BOOT_SIZE +
+    AMEBA_SECTOR_FIRMWARE1_SIZE,
+    .nblocks    = AMEBA_SECTOR_FIRMWARE2_SIZE,
+  },
+  {
+    .name       = "ota",
+    .firstblock = AMEBA_SECTOR_SYSTEM_SIZE +
+    AMEBA_SECTOR_BOOT_SIZE +
+    AMEBA_SECTOR_FIRMWARE1_SIZE +
+    AMEBA_SECTOR_FIRMWARE2_SIZE,
+    .nblocks    = AMEBA_SECTOR_OTA_SIZE,
+  },
+  {
+    .name       = "data",
+    .firstblock = AMEBA_SECTOR_SYSTEM_SIZE +
+    AMEBA_SECTOR_BOOT_SIZE +
+    AMEBA_SECTOR_FIRMWARE1_SIZE +
+    AMEBA_SECTOR_FIRMWARE2_SIZE +
+    AMEBA_SECTOR_OTA_SIZE,
+    .nblocks    = AMEBA_SECTOR_DATA_SIZE,
+  },
+  {
+    .name       = "bt",
+    .firstblock = AMEBA_SECTOR_SYSTEM_SIZE +
+    AMEBA_SECTOR_BOOT_SIZE +
+    AMEBA_SECTOR_FIRMWARE1_SIZE +
+    AMEBA_SECTOR_FIRMWARE2_SIZE +
+    AMEBA_SECTOR_OTA_SIZE +
+    AMEBA_SECTOR_DATA_SIZE,
+    .nblocks    = AMEBA_SECTOR_BLUETOOTH_SIZE,
+  },
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static irqstate_t flash_resource_lock(void)
+{
+  irqstate_t state;
+  state = enter_critical_section();
+  icache_disable();
+  dcache_disable();
+  return state;
+}
+
+static void flash_resource_unlock(irqstate_t state)
+{
+  dcache_enable();
+  icache_enable();
+  icache_invalidate();
+  leave_critical_section(state);
+}
+
+static int ameba_flash_erase(FAR struct mtd_dev_s *dev,
+                             off_t startblock, size_t nblocks)
+{
+  FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev;
+  uint32_t address = priv->baseaddr + (startblock << AMEBA_SECTOR_SHIFT);
+  irqstate_t state;
+  state = flash_resource_lock();
+  hal_flash_stubs.hal_flash_sector_erase(priv->adaptor, address);
+  flash_resource_unlock(state);
+  return nblocks;
+}
+
+static ssize_t ameba_flash_bread(FAR struct mtd_dev_s *dev,
+                                      off_t startblock,
+                                      size_t nblocks,
+                                      FAR uint8_t *buf)
+{
+  FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev;
+  uint32_t address = priv->baseaddr + (startblock << AMEBA_PAGE_SHIFT);
+  uint32_t length = nblocks << AMEBA_PAGE_SHIFT;
+  irqstate_t state;
+  state = flash_resource_lock();
+  dcache_invalidate_by_addr((uint32_t *)(SPI_FLASH_BASE + address), length);
+  hal_flash_stubs.hal_flash_stream_read(priv->adaptor, length, address, buf);
+  flash_resource_unlock(state);
+  return nblocks;
+}
+
+static ssize_t ameba_flash_bwrite(FAR struct mtd_dev_s *dev,
+                                  off_t startblock,
+                                  size_t nblocks, FAR const uint8_t *buf)
+{
+  FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev;
+  uint32_t address = priv->baseaddr + (startblock << AMEBA_PAGE_SHIFT);
+  uint32_t length = nblocks << AMEBA_PAGE_SHIFT;
+  irqstate_t state;
+  state = flash_resource_lock();
+  hal_flash_stubs.hal_flash_burst_write(priv->adaptor,
+                                        length, address, (uint8_t *)buf);
+  flash_resource_unlock(state);
+  return nblocks;
+}
+
+static int ameba_flash_spic_init(struct ameba_flash_dev_s *priv)
+{
+  hal_status_t status;
+  irqstate_t state;
+  if (pglob_spic_adaptor == NULL)
+    {
+      status = spic_init(&hal_spic_adaptor, SPICDUALIOMODE,
+                         &(hal_spic_adaptor.flash_pin_sel));
+      if (status != HAL_OK)
+        {
+          DBG_SPIF_ERR("flash_init err(%d)\r\n", status);
+        }
+
+      return status;
+    }
+
+  priv->adaptor = pglob_spic_adaptor;
+  state = flash_resource_lock();
+  hal_flash_stubs.hal_flash_read_id(pglob_spic_adaptor);
+  flash_resource_unlock(state);
+  if ((pglob_spic_adaptor->flash_id[0] == 0x0)
+      || (pglob_spic_adaptor->flash_id[0] == 0xff))
+    {
+      return -EPERM;
+    }
+
+  return 0;
+}
+
+static int ameba_flash_ioctl(FAR struct mtd_dev_s *dev,
+                             int cmd, unsigned long arg)
+{
+  FAR struct ameba_flash_dev_s *priv = (FAR struct ameba_flash_dev_s *)dev;
+  irqstate_t state;
+  int ret = OK;
+  switch (cmd)
+    {
+    case MTDIOC_GEOMETRY:
+    {
+      FAR struct mtd_geometry_s *geo =
+        (FAR struct mtd_geometry_s *)((uintptr_t)arg);
+      if (geo)
+        {
+          geo->blocksize    = AMEBA_PAGE_SIZE;
+          geo->erasesize    = AMEBA_SECTOR_SIZE;
+          geo->neraseblocks = priv->nsectors;
+          finfo("blocksize: %d erasesize: %d neraseblocks: %d\n",
+                geo->blocksize, geo->erasesize, geo->neraseblocks);
+        }
+    }
+
+    break;
+    case MTDIOC_BULKERASE:
+    {
+      state = flash_resource_lock();
+      hal_flash_stubs.hal_flash_64k_block_erase(priv->adaptor,
+                                                priv->baseaddr);
+      flash_resource_unlock(state);
+    }
+
+    break;
+    default:
+    {
+      ret = -ENOTTY;
+    }
+
+    break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ameba_flash_initialize
+ *
+ * Description:
+ *  Create and initialize an ameba spic flash MTD device instance
+ *  that can be used to access the userdata memory.
+ *
+ ****************************************************************************/
+
+static FAR struct mtd_dev_s *ameba_flash_initialize(void)
+{
+  struct ameba_flash_dev_s *priv;
+  priv = kmm_zalloc(sizeof(struct ameba_flash_dev_s));
+  if (priv == NULL)
+    {
+      return NULL;
+    }
+
+  priv->mtd.erase    = ameba_flash_erase;
+  priv->mtd.bread    = ameba_flash_bread;
+  priv->mtd.bwrite   = ameba_flash_bwrite;
+  priv->mtd.ioctl    = ameba_flash_ioctl;
+  priv->mtd.name     = "ameba_flash";
+  priv->baseaddr     = 0;
+  priv->nsectors     = AMEBA_SECTOR_TOTAL_SIZE /
+                       AMEBA_SECTOR_SIZE;
+  if (ameba_flash_spic_init(priv) < 0)
+    {
+      ferr("ERROR: Flash Type Unrecognized\n");
+      kmm_free(priv);
+      priv = NULL;
+    }
+
+  return (FAR struct mtd_dev_s *)priv;
+}
+
+static void ameba_partition_init(FAR const struct partition_s *part,
+                                       FAR const void *path)
+{
+  char dev[32];
+  snprintf(dev, sizeof(dev), "/dev/%s", part->name);
+  register_mtdpartition(dev, 0, path,
+                        part->firstblock / AMEBA_PAGE_SIZE,
+                        part->nblocks / AMEBA_PAGE_SIZE);
+}
+
+void ameba_flash_init(void)
+{
+  const struct partition_s *table;
+  char *path = "/dev/ameba_flash";
+  FAR struct mtd_dev_s *mtd;
+  mtd = ameba_flash_initialize();
+  if (mtd == NULL)
+    {
+      return;
+    }
+
+  register_mtddriver(path, mtd, 0, mtd);
+  for (table = &ptable[0]; table->nblocks; table++)
+    {
+      ameba_partition_init(table, path);
+    }
+}
+

arch/arm/src/rtl8720c/ameba_flash.h

@@ -0,0 +1,46 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_flash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_AMEBA_FLASH_H
+#define __INCLUDE_AMEBA_FLASH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/mtd/mtd.h>
+#include <hal_flash.h>
+#include <hal_spic.h>
+#include <hal_cache.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __INCLUDE_AMEBA_FLASH_H */

arch/arm/src/rtl8720c/ameba_hci.c

@@ -0,0 +1,509 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_hci.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <fcntl.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/net/netdev.h>
+#include <../../../../net/netdev/netdev.h>
+#include "amebaz_hci_board.h"
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define AMEBAZ_WIRELESS_NAME            "wlan0"
+#define H4_CMD                          0x01
+#define H4_EVT                          0x04
+#define HCI_H4_HDR_SIZE                 1
+#define HCI_CMD_HDR_SIZE                3
+typedef struct
+{
+  struct file_operations  i_ops;
+  struct file             filep;
+} hci_dev_t;
+struct bt_hci_evt_hdr
+{
+  uint8_t evt;
+  uint8_t len;
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+static int hci_recv(FAR struct file *filep, FAR uint8_t *buf, size_t count)
+{
+  ssize_t ret;
+  ssize_t nread = 0;
+  while (count != nread)
+    {
+      ret = file_read(filep, buf + nread, count - nread);
+      if (ret < 0)
+        {
+          if (ret == -EAGAIN)
+            {
+              continue;
+            }
+          else
+            {
+              return ret;
+            }
+        }
+
+      nread += ret;
+    }
+
+  return nread;
+}
+
+static int hci_send(FAR struct file *filep, FAR uint8_t *buf, size_t count)
+{
+  ssize_t ret;
+  ssize_t nwritten = 0;
+  while (nwritten != count)
+    {
+      ret = file_write(filep, buf + nwritten, count - nwritten);
+      if (ret < 0)
+        {
+          if (ret == -EAGAIN)
+            {
+              continue;
+            }
+          else
+            {
+              return ret;
+            }
+        }
+
+      nwritten += ret;
+    }
+
+  return nwritten;
+}
+
+#ifdef HCI_START_IQK
+static int hci_do_iqk(FAR struct file *filep)
+{
+  /* OpCode: 0xfd4a, h4 data_len: Cmd(8), Event(7) */
+
+  unsigned char command[8];
+  struct t_data
+  {
+    uint8_t offset;
+    uint16_t value;
+  };
+
+  struct t_data data[4] =
+  {
+    {0x00, 0x4000},
+    {0x01, 0x0f88},
+    {0x02, 0x3400},
+    {0x3f, 0x0700}
+  };
+
+  if (0 == hci_check_iqk())
+    {
+      return 0;
+    }
+
+  for (unsigned char i = 0; i < 4; i++)
+    {
+      command[0] = H4_CMD;
+      command[1] = 0x4a;
+      command[2] = 0xfd;
+      command[3] = 4;
+      command[4] = data[i].offset;
+      command[5] = (uint8_t)(data[i].value >> 0);
+      command[6] = (uint8_t)(data[i].value >> 8);
+      command[7] = 0;
+      if (hci_send(filep, command, 8) != 8)
+        {
+          return -EIO;
+        }
+
+      hci_recv(filep, command, 1);
+      if (command[0] != H4_EVT)
+        {
+          return -EIO;
+        }
+
+      hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr));
+      hci_recv(filep, command + 3, command[2]);
+
+      /* Check OpCode and Status */
+
+      if (!(command[4] == 0x4a && command[5] == 0xfd) || command[6] != 0x00)
+        {
+          return -EIO;
+        }
+    }
+
+  if (hci_start_iqk())
+    {
+      return -EIO;
+    }
+
+  return 0;
+}
+
+#endif
+static int hci_check_local_ver(FAR struct file *filep)
+{
+  /* OpCode: 0x1001, h4 buf_len: Cmd(1+3=4), Event(1+14=15) */
+
+  unsigned char command[15];
+  command[0] = H4_CMD;
+  command[1] = 0x01;
+  command[2] = 0x10;
+  command[3] = 0;
+  if (hci_send(filep, command, 4) != 4)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command, 1);
+  if (command[0] != H4_EVT)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr));
+  hci_recv(filep, command + 3, command[2]);
+
+  /* Check OpCode and Status */
+
+  if (!(command[4] == 0x01 && command[5] == 0x10) || command[6] != 0x00)
+    {
+      return -EIO;
+    }
+
+  /* Only Check LMP Subversion */
+
+  uint16_t lmp_sbuver =
+    ((uint16_t)command[13]) | (((uint16_t)command[14]) << 8);
+  if (BT_DEFAUT_LMP_SUBVER != lmp_sbuver)
+    {
+      return -EALREADY;
+    }
+
+  return 0;
+}
+
+static int hci_check_local_rom_ver(FAR struct file *filep)
+{
+  /* OpCode: 0xfc6d, h4 buf_len: Cmd(1+3=4), Event(1+7=8) */
+
+  unsigned char command[8];
+  command[0] = H4_CMD;
+  command[1] = 0x6d;
+  command[2] = 0xfc;
+  command[3] = 0;
+  if (hci_send(filep, command, 4) != 4)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command, 1);
+  if (command[0] != H4_EVT)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr));
+  hci_recv(filep, command + 3, command[2]);
+
+  /* Check OpCode and Status */
+
+  if (!(command[4] == 0x6d && command[5] == 0xfc) || command[6] != 0x00)
+    {
+      return -EIO;
+    }
+
+  /* Get Chip Id (Rom_Ver+1) and Find Patch */
+
+  if (hci_find_fw_patch(command[7] + 1))
+    {
+      return -EIO;
+    }
+
+  return 0;
+}
+
+static int hci_update_baudrate(FAR struct file *filep)
+{
+  /* OpCode: 0xfc17, h4 buf_len: Cmd(1+7=8), Event(1+6=7) */
+
+  unsigned char command[8];
+  struct termios toptions;
+  uint32_t bt_baudrate;
+  uint32_t uart_baudrate;
+  command[0] = H4_CMD;
+  command[1] = 0x17;
+  command[2] = 0xfc;
+  command[3] = sizeof(uint32_t);
+  if (hci_get_baudrate(&bt_baudrate, &uart_baudrate))
+    {
+      return -EIO;
+    }
+
+  memcpy(&command[4], &bt_baudrate, sizeof(uint32_t));
+  if (hci_send(filep, command, 8) != 8)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command, 1);
+  if (command[0] != H4_EVT)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr));
+  hci_recv(filep, command + 3, command[2]);
+
+  /* Check OpCode and Status */
+
+  if (!(command[4] == 0x17 && command[5] == 0xfc) || command[6] != 0x00)
+    {
+      return -EIO;
+    }
+
+  file_ioctl(filep, TCGETS, (unsigned long)&toptions);
+  cfsetispeed(&toptions, uart_baudrate);
+  cfsetospeed(&toptions, uart_baudrate);
+  return file_ioctl(filep, TCSETS, (unsigned long)&toptions);
+}
+
+static int hci_load_firmware(FAR struct file *filep)
+{
+  int header_size = HCI_H4_HDR_SIZE + HCI_CMD_HDR_SIZE;
+  uint8_t command[AMEBAZ_COMMAND_FRAGMENT_SIZE + header_size];
+  FAR struct net_driver_s *drv;
+  int buffer_size;
+  uint8_t *addr;
+  int i;
+  int ret;
+  drv = netdev_findbyname(AMEBAZ_WIRELESS_NAME);
+  if (drv == NULL)
+    {
+      return -EINVAL;
+    }
+
+  addr = drv->d_mac.ether.ether_addr_octet;
+  if (hci_set_init_config_mac(addr, 1))
+    {
+      return -EIO;
+    }
+
+  while (hci_fetch_command(command) != AMEBAZ_COMMAND_DONE)
+    {
+      command[0] = H4_CMD;
+      command[1] = 0x20;
+      command[2] = 0xfc;
+      buffer_size = header_size + command[3];
+      usleep(10);
+      ret = hci_send(filep, command, buffer_size);
+      if (ret != buffer_size)
+        {
+          return ret;
+        }
+
+      hci_recv(filep, command, 1);
+      if (H4_EVT != command[0])
+        {
+          return -EIO;
+        }
+
+      hci_recv(filep, command + 1, 2);
+      hci_recv(filep, command + 3, command[2]);
+
+      /* Check OpCode and Status */
+
+      if (!(command[4] == 0x20 && command[5] == 0xfc) || command[6] != 0x00)
+        {
+          return -EIO;
+        }
+    }
+
+  return OK;
+}
+
+static int hci_update_efuse_iqk(FAR struct file *filep)
+{
+  /* OpCode: 0xfd91, h4 buf_len: Cmd(1+15=16), Event(1+6=7) */
+
+  unsigned char command[16];
+  command[0] = H4_CMD;
+  command[1] = 0x91;
+  command[2] = 0xfd;
+  if (hci_get_efuse_iqk_data(command + 3))
+    {
+      return -EIO;
+    }
+
+  if (hci_send(filep, command, sizeof(command)) != sizeof(command))
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command, 1);
+  if (command[0] != H4_EVT)
+    {
+      return -EIO;
+    }
+
+  hci_recv(filep, command + 1, sizeof(struct bt_hci_evt_hdr));
+  hci_recv(filep, command + 3, command[2]);
+  return 0;
+}
+
+static int hci_open(FAR struct file *filep)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR hci_dev_t *dev = inode->i_private;
+  int ret;
+  ret = file_open(&dev->filep,
+                  CONFIG_AMEBA_HCI_DEV_NAME, O_RDWR | O_BINARY);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  if (hci_board_init())
+    {
+      goto bail;
+    }
+
+#ifdef HCI_START_IQK
+  ret = hci_do_iqk(&dev->filep);
+  if (ret < 0)
+    {
+      goto bail;
+    }
+
+#endif
+  ret = hci_check_local_ver(&dev->filep);
+  if (ret < 0)
+    {
+      if (-EALREADY == ret)
+        {
+          ret = 0;
+        }
+
+      goto bail;
+    }
+
+  ret = hci_check_local_rom_ver(&dev->filep);
+  if (ret < 0)
+    {
+      goto bail;
+    }
+
+  ret = hci_update_baudrate(&dev->filep);
+  if (ret < 0)
+    {
+      goto bail;
+    }
+
+  ret = hci_load_firmware(&dev->filep);
+  if (ret < 0)
+    {
+      goto bail;
+    }
+
+  ret = hci_update_efuse_iqk(&dev->filep);
+bail:
+  ret = hci_board_init_done();
+  if (ret < 0)
+    {
+      file_close(&dev->filep);
+    }
+
+  return ret;
+}
+
+static int hci_close(FAR struct file *filep)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR hci_dev_t *dev = inode->i_private;
+
+  /* FIXME: BT PowerOff */
+
+  return file_close(&dev->filep);
+}
+
+static ssize_t hci_read(FAR struct file *filep,
+                        FAR char *buffer, size_t buflen)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR hci_dev_t *dev = inode->i_private;
+  return file_read(&dev->filep, buffer, buflen);
+}
+
+static ssize_t hci_write(FAR struct file *filep, FAR const char *buffer,
+                         size_t buflen)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR hci_dev_t *dev = inode->i_private;
+  return file_write(&dev->filep, buffer, buflen);
+}
+
+static int hci_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR hci_dev_t *dev = inode->i_private;
+  return file_ioctl(&dev->filep, cmd, arg);
+}
+
+static int hci_poll(FAR struct file *filep,
+                    FAR struct pollfd *fds, bool setup)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR hci_dev_t *dev = inode->i_private;
+  return file_poll(&dev->filep, fds, setup);
+}
+
+static hci_dev_t g_hcidev =
+{
+  .i_ops =
+    {
+      .open   = hci_open,
+      .close  = hci_close,
+      .read   = hci_read,
+      .write  = hci_write,
+      .ioctl  = hci_ioctl,
+      .poll   = hci_poll
+    },
+};
+
+int amebaz_bt_hci_uart_register(FAR const char *path)
+{
+  return register_driver(path, &g_hcidev.i_ops, 0666, &g_hcidev);
+}
+

arch/arm/src/rtl8720c/ameba_heap.c

@@ -0,0 +1,114 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_heap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <assert.h>
+#include <string.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include "chip.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define _START_HEAP                     ((uintptr_t)&__bss_end__)
+#define _END_HEAP                       ((uintptr_t)&__sram_end__)
+#ifdef CONFIG_HEAP_COLORATION
+#  define song_heap_color(start, size)  memset(start, HEAP_COLOR, size)
+#else
+#  define song_heap_color(start, size)
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern uint32_t __stack;
+extern uint32_t __bss_end__;
+extern uint32_t __sram_end__;
+/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
+ * linker script. _ebss lies at the end of the BSS region. The idle task
+ * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
+ * The IDLE thread is the thread that the system boots on and, eventually,
+ * becomes the IDLE, do nothing task that runs only when there is nothing
+ * else to run.  The heap continues from there until the end of memory.
+ * g_idle_topstack is a read-only variable the provides this computed
+ * address.
+ */
+
+const uintptr_t __attribute__((weak)) g_idle_topstack =
+  ((uintptr_t)&__stack);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ *   size of the unprotected, user-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ *   The following memory map is assumed for the flat build:
+ *
+ *     .data region.  Size determined at link time.
+ *     .bss  region  Size determined at link time.
+ *     IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ *     Heap.  Extends to the end of SRAM.
+ *
+ *   The following memory map is assumed for the kernel build:
+ *
+ *     Kernel .data region.  Size determined at link time.
+ *     Kernel .bss  region  Size determined at link time.
+ *     Kernel IDLE thread stack. Size determined by
+ *                               CONFIG_IDLETHREAD_STACKSIZE.
+ *     Kernel heap.  Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ *     Padding for alignment
+ *     User .data region.  Size determined at link time.
+ *     User .bss region  Size determined at link time.
+ *     User heap.  Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  /* Return the heap settings */
+
+  *heap_start = (FAR void *)_START_HEAP;
+  *heap_size  = _END_HEAP - _START_HEAP;
+
+  /* Colorize the heap for debug */
+
+  song_heap_color(*heap_start, *heap_size);
+}
+

arch/arm/src/rtl8720c/ameba_idle.c

@@ -0,0 +1,66 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_idle.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idlepm
+ *
+ * Description:
+ *   Perform IDLE state power management.
+ *
+ ****************************************************************************/
+
+#  define up_idlepm() up_cpu_idle()
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed
+ *   when their is no other ready-to-run task.  This is processor
+ *   idle time and will continue until some interrupt occurs to
+ *   cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g.,
+ *   this is where power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+}
+

arch/arm/src/rtl8720c/ameba_lto.S

@@ -0,0 +1,70 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_lto.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+  .syntax	unified
+  .arch armv8-m.main
+  .thumb
+  .file	"ameba_lto.S"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+  .text
+  .thumb_func
+  .globl ameba_lto
+  .globl __aeabi_d2iz
+  .globl __aeabi_d2lz
+  .globl __aeabi_d2ulz
+  .globl __aeabi_dcmpeq
+  .globl __aeabi_dcmpge
+  .globl __aeabi_dcmplt
+  .globl __aeabi_ddiv
+  .globl __aeabi_fadd
+  .globl __aeabi_fcmpge
+  .globl __aeabi_fcmpgt
+  .globl __aeabi_fdiv
+  .globl __aeabi_fmul
+  .globl __aeabi_i2f
+  .globl __aeabi_idivmod
+  .globl __aeabi_ldivmod
+  .globl __aeabi_llsl
+  .globl __aeabi_llsr
+  .globl __aeabi_lmul
+  .globl __aeabi_uidiv
+  .globl __aeabi_uldivmod
+  .globl __bswapsi2
+  .globl __clzsi2
+  .globl __ctzsi2
+  .globl __gnu_thumb1_case_shi
+  .globl __gnu_thumb1_case_si
+  .globl __gnu_thumb1_case_sqi
+  .globl __gnu_thumb1_case_uhi
+  .globl __gnu_thumb1_case_uqi
+  .globl __gnu_thumb1_case_uqi
+  .globl __popcountsi2
+  .type	ameba_lto, function
+ameba_lto:
+  .size	ameba_lto, .-ameba_lto
+  .end

arch/arm/src/rtl8720c/ameba_nvic.c

@@ -0,0 +1,458 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_nvic.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#ifdef CONFIG_ARCH_CORTEXM33
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <string.h>
+#include "sched/sched.h"
+#include "chip.h"
+#include "nvic.h"
+#include "ram_vectors.h"
+#include "arm_arch.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ROUND_DOWN(v, q)          (((v) / (q)) * (q))
+
+/* Get a 32-bit version of the default priority */
+
+#define NVIC_PRIORITY_DEFAULT32   (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
+                                   NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
+                                   NVIC_SYSH_PRIORITY_DEFAULT << 8  | \
+                                   NVIC_SYSH_PRIORITY_DEFAULT)
+/* Given the address of a NVIC ENABLE register, this is the offset to
+ * the corresponding NVIC CLEAR register.
+ */
+#define NVIC_ENABLE_OFFSET        (NVIC_IRQ0_31_ENABLE - NVIC_IRQ0_31_ENABLE)
+#define NVIC_CLEAR_OFFSET         (NVIC_IRQ0_31_CLEAR  - NVIC_IRQ0_31_ENABLE)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure.  If is non-NULL only during interrupt
+ * processing.  Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+#ifdef CONFIG_SMP
+volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+#else
+volatile uint32_t *g_current_regs[1];
+#endif
+
+/* extern int32_t    __StackLimit; */
+
+extern uint32_t   _vectors[];
+
+/****************************************************************************
+ * Private Function Declarations
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static int (* __vectors[NR_IRQS - NVIC_IRQ_FIRST])(void);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+static inline uint32_t up_getsp(void)
+{
+  uint32_t sp;
+  __asm__
+  (
+    "\tmov %0, sp\n\t"
+    : "=r"(sp)
+  );
+  return sp;
+}
+
+/****************************************************************************
+ * Name: nvic_irqinfo
+ *
+ * Description:
+ *   Given an IRQ number, provide the register and bit setting to enable or
+ *   disable the irq.
+ *
+ ****************************************************************************/
+
+static int nvic_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
+                        uintptr_t offset)
+{
+  DEBUGASSERT(irq >= NVIC_IRQ_MEMFAULT && irq < NR_IRQS);
+
+  /* Check for external interrupt */
+
+  if (irq >= NVIC_IRQ_FIRST)
+    {
+      irq      = irq - NVIC_IRQ_FIRST;
+      *regaddr = NVIC_IRQ_ENABLE(irq) + offset;
+      *bit     = (uint32_t)1 << (irq & 0x1f);
+    }
+
+  /* Handle processor exceptions.  Only a few can be disabled */
+
+  else
+    {
+      *regaddr = NVIC_SYSHCON;
+      if (irq == NVIC_IRQ_MEMFAULT)
+        {
+          *bit = NVIC_SYSHCON_MEMFAULTENA;
+        }
+
+      else if (irq == NVIC_IRQ_BUSFAULT)
+        {
+          *bit = NVIC_SYSHCON_BUSFAULTENA;
+        }
+
+      else if (irq == NVIC_IRQ_USAGEFAULT)
+        {
+          *bit = NVIC_SYSHCON_USGFAULTENA;
+        }
+
+      else if (irq == NVIC_IRQ_DBGMONITOR)
+        {
+          *regaddr = NVIC_DEMCR;
+          *bit = NVIC_DEMCR_MONEN;
+        }
+
+      else if (irq == NVIC_IRQ_SYSTICK)
+        {
+          *regaddr = NVIC_SYSTICK_CTRL;
+          *bit = NVIC_SYSTICK_CTRL_TICKINT;
+        }
+
+      else
+        {
+          return ERROR; /* Invalid or unsupported exception */
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void weak_function up_wic_initialize(void)
+{
+}
+
+void weak_function up_wic_enable_irq(int irq)
+{
+}
+
+void weak_function up_wic_disable_irq(int irq)
+{
+}
+
+/****************************************************************************
+ * Name: arm_ack_irq
+ *
+ * Description:
+ *   Acknowledge the IRQ
+ *
+ ****************************************************************************/
+
+void arm_ack_irq(int irq)
+{
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   This function implements disabling of the device specified by 'irq'
+ *   at the interrupt controller level if supported by the architecture
+ *   (up_irq_save() supports the global level, the device level is hardware
+ *   specific).
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  uintptr_t regaddr;
+  uint32_t bit;
+  if (nvic_irqinfo(irq, &regaddr, &bit, NVIC_CLEAR_OFFSET) == 0)
+    {
+      /* Modify the appropriate bit in the register to disable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Clear Enable register.  For other exceptions, we need to
+       * clear the bit in the System Handler Control and State Register.
+       */
+
+      if (irq >= NVIC_IRQ_FIRST)
+        {
+          putreg32(bit, regaddr);
+        }
+
+      else
+        {
+          modifyreg32(regaddr, bit, 0);
+        }
+
+      up_wic_disable_irq(irq);
+    }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   On many architectures, there are three levels of interrupt enabling: (1)
+ *   at the global level, (2) at the level of the interrupt controller,
+ *   and (3) at the device level.  In order to receive interrupts, they
+ *   must be enabled at all three levels.
+ *
+ *   This function implements enabling of the device specified by 'irq'
+ *   at the interrupt controller level if supported by the architecture
+ *   (up_irq_restore() supports the global level, the device level is
+ *   hardware specific).
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  uintptr_t regaddr;
+  uint32_t bit;
+  if (nvic_irqinfo(irq, &regaddr, &bit, NVIC_ENABLE_OFFSET) == 0)
+    {
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
+
+      if (irq >= NVIC_IRQ_FIRST)
+        {
+          putreg32(bit, regaddr);
+        }
+
+      else
+        {
+          modifyreg32(regaddr, 0, bit);
+        }
+
+      up_wic_enable_irq(irq);
+    }
+}
+
+/****************************************************************************
+ * Name: up_trigger_irq
+ *
+ * Description:
+ *   Trigger an IRQ by software.
+ *
+ ****************************************************************************/
+
+void up_trigger_irq(int irq)
+{
+  uint32_t pend_bit = 0;
+  DEBUGASSERT(irq >= NVIC_IRQ_NMI && irq < NR_IRQS);
+  if (irq >= NVIC_IRQ_FIRST)
+    {
+      putreg32(irq - NVIC_IRQ_FIRST, NVIC_STIR);
+    }
+
+  else
+    {
+      switch (irq)
+        {
+        case NVIC_IRQ_PENDSV:
+          pend_bit = NVIC_INTCTRL_PENDSVSET;
+          break;
+        case NVIC_IRQ_NMI:
+          pend_bit = NVIC_INTCTRL_NMIPENDSET;
+          break;
+        case NVIC_IRQ_SYSTICK:
+          pend_bit = NVIC_INTCTRL_PENDSTSET;
+          break;
+        }
+
+      if (pend_bit)
+        {
+          modifyreg32(NVIC_INTCTRL, 0, pend_bit);
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32_t regaddr;
+  int shift;
+  DEBUGASSERT(irq >= NVIC_IRQ_MEMFAULT && irq < NR_IRQS &&
+              priority >= NVIC_SYSH_PRIORITY_MAX &&
+              priority <= NVIC_SYSH_PRIORITY_MIN);
+  if (irq < NVIC_IRQ_FIRST)
+    {
+      /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
+       * registers (0-3 are invalid)
+       */
+
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+      irq    -= NVIC_IRQ_MEMFAULT;
+    }
+
+  else
+    {
+      /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
+
+      irq    -= NVIC_IRQ_FIRST;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  shift = (irq & 3) << 3;
+  modifyreg32(regaddr, 0xff << shift, priority << shift);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: _up_doirq
+ ****************************************************************************/
+
+int _up_doirq(int irq, FAR void *context, FAR void *arg)
+{
+  if (irq < NVIC_IRQ_FIRST)
+    {
+      return ERROR;
+    }
+
+  __vectors[irq - NVIC_IRQ_FIRST]();
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  int i;
+
+  /* Disable all interrupts */
+
+  for (i = 0; i < NR_IRQS - NVIC_IRQ_FIRST; i += 32)
+    {
+      putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
+    }
+
+  /* Restore the NVIC vector location to local */
+
+  memcpy(&__vectors, (void *) * (volatile uint32_t *)(NVIC_VECTAB)
+         + NVIC_IRQ_FIRST * sizeof(uint32_t), sizeof(__vectors));
+
+  /* Set the NVIC vector location in case _vectors not equal zero. */
+
+  putreg32((uint32_t)_vectors, NVIC_VECTAB);
+  /* Now bits[7-5] are available in each 8bits,
+   * Take bits[7-6] as group priority, take bit[5] as subpriorities.
+   */
+
+  modifyreg32(NVIC_AIRCR, NVIC_AIRCR_VECTKEY_MASK | NVIC_AIRCR_PRIGROUP_MASK,
+  (0x5fa << NVIC_AIRCR_VECTKEY_SHIFT) | (0x5 << NVIC_AIRCR_PRIGROUP_SHIFT));
+
+  /* Set all interrupts (and exceptions) to the default priority */
+
+  putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_SYSH4_7_PRIORITY);
+  putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_SYSH8_11_PRIORITY);
+  putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_SYSH12_15_PRIORITY);
+  for (i = 0; i < NR_IRQS - NVIC_IRQ_FIRST; i += 4)
+    {
+      putreg32(NVIC_PRIORITY_DEFAULT32, NVIC_IRQ_PRIORITY(i));
+    }
+
+  up_wic_initialize();
+  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
+   * exception is used for performing context switches; The Hard Fault
+   * must also be caught because a SVCall may show up as a Hard Fault
+   * under certain conditions.
+   */
+
+  irq_attach(NVIC_IRQ_SVCALL, arm_svcall, NULL);
+  up_prioritize_irq(NVIC_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
+  irq_attach(NVIC_IRQ_HARDFAULT, arm_hardfault, NULL);
+
+  /* Attach and enable the Memory Management Fault handler */
+
+  irq_attach(NVIC_IRQ_MEMFAULT, arm_memfault, NULL);
+  up_enable_irq(NVIC_IRQ_MEMFAULT);
+
+  /* Attach and enable the external interrupts */
+
+  for (i = NVIC_IRQ_FIRST; i < NR_IRQS; i++)
+    {
+      irq_attach(i, _up_doirq, NULL);
+    }
+
+  up_disable_irq(NVIC_IRQ_BUSFAULT);
+  up_disable_irq(NVIC_IRQ_USAGEFAULT);
+
+  /* And finally, enable interrupts */
+
+  up_irq_enable();
+}
+
+void up_irq_attach_workaround(void)
+{
+  extern void exception_common(void);
+  __vectors[NVIC_IRQ_WLAN - NVIC_IRQ_FIRST] =
+    (void *) *((uint32_t *) *(volatile uint32_t *)NVIC_VECTAB +
+    NVIC_IRQ_WLAN);
+  *((uint32_t *) * (volatile uint32_t *)NVIC_VECTAB + NVIC_IRQ_WLAN) =
+    (unsigned)exception_common;
+  up_prioritize_irq(NVIC_IRQ_WLAN, NVIC_SYSH_PRIORITY_DEFAULT);
+}
+
+#endif

arch/arm/src/rtl8720c/ameba_start.c

@@ -0,0 +1,93 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_start.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/init.h>
+#include "arm_internal.h"
+#include "rtl8710c_irq.h"
+#include <stdlib.h>
+
+extern void ram_start(void);
+extern void ameba_lto(void);
+const hal_irq_api_t sys_irq_api =
+{
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV8M_STACKCHECK
+
+/* We need to get r10 set before we can allow instrumentation calls */
+
+void __start(void) __attribute__((no_instrument_function));
+#endif
+void __start(void)
+{
+#ifdef CONFIG_ARMV8M_STACKCHECK
+
+  /* Set the stack limit before we attempt to call any functions */
+
+  #define STACKSIZE_TEMP CONFIG_IDLETHREAD_STACKSIZE
+  __asm__ volatile("sub r10, sp, %0" : : "r" (STACKSIZE_TEMP - 64) :);
+#endif
+  ram_start();
+}
+
+void mpu_init(void)
+{
+}
+
+void promisc_deinit(void *padapter)
+{
+}
+
+int promisc_recv_func(void *padapter, void *rframe)
+{
+  return 0;
+}
+
+int promisc_recv_lens_func(void *padapter, uint8_t *payload, uint8_t plen)
+{
+  return 0;
+}
+
+void app_start(void)
+{
+  __asm volatile("MSR msplim, %0" : : "r"(0));
+  arm_earlyserialinit();
+#ifdef CONFIG_MBEDTLS240_AMEBAZ_HARDWARE_CRYPTO
+  extern int mbedtls_platform_set_calloc_free(
+    void *(*calloc_func)(size_t, size_t), void (*free_func)(void *));
+  extern int chip_platform_set_malloc_free(
+    void *(*ssl_calloc)(unsigned int, unsigned int),
+    void (*ssl_free)(void *));
+  mbedtls_platform_set_calloc_free(calloc, free);
+  chip_platform_set_malloc_free(calloc, free);
+#endif
+  nx_start();
+  ameba_lto();
+}
+

arch/arm/src/rtl8720c/ameba_uart.h

@@ -0,0 +1,178 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_NUTTX_SERIAL_UART_AMEBA_H
+#define __INCLUDE_NUTTX_SERIAL_UART_AMEBA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hal_uart.h>
+#include <hal_pinmux.h>
+#ifdef CONFIG_AMEBA_UART
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* CONFIGURATION */
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART
+#if defined(CONFIG_AMEBA_UART0) || defined(CONFIG_AMEBA_UART1) || \
+    defined(CONFIG_AMEBA_UART2) || defined(CONFIG_AMEBA_UART3)
+#  define HAVE_UART 1
+#endif
+/* We need to be told the address increment between registers and
+ * the register bit width.
+ */
+#ifndef CONFIG_AMEBA_REGINCR
+#  error "CONFIG_AMEBA_REGINCR not defined"
+#endif
+
+#if CONFIG_AMEBA_REGINCR != 1 && CONFIG_AMEBA_REGINCR != 2 && CONFIG_AMEBA_REGINCR != 4
+#  error "CONFIG_AMEBA_REGINCR not supported"
+#endif
+#ifndef CONFIG_AMEBA_REGWIDTH
+#  error "CONFIG_AMEBA_REGWIDTH not defined"
+#endif
+
+#if CONFIG_AMEBA_REGWIDTH != 8 && CONFIG_AMEBA_REGWIDTH != 16 && CONFIG_AMEBA_REGWIDTH != 32
+#  error "CONFIG_AMEBA_REGWIDTH not supported"
+#endif
+#ifndef CONFIG_AMEBA_ADDRWIDTH
+#  error "CONFIG_AMEBA_ADDRWIDTH not defined"
+#endif
+
+#if CONFIG_AMEBA_ADDRWIDTH != 8 && CONFIG_AMEBA_ADDRWIDTH != 16 && CONFIG_AMEBA_ADDRWIDTH != 32
+#  error "CONFIG_AMEBA_ADDRWIDTH not supported"
+#endif
+
+/* If a UART is enabled, then its base address,
+ * clock, and IRQ must also be provided
+ */
+
+#ifdef CONFIG_AMEBA_UART0
+#  ifndef CONFIG_AMEBA_UART0_TX_PIN
+#    error "CONFIG_AMEBA_UART0_TX_PIN not provided"
+#    undef CONFIG_AMEBA_UART0
+#  endif
+#  ifndef CONFIG_AMEBA_UART0_RX_PIN
+#    error "CONFIG_AMEBA_UART0_RX_PIN not provided"
+#    undef CONFIG_AMEBA_UART0
+#  endif
+#endif
+#ifdef CONFIG_AMEBA_UART1
+#  ifndef CONFIG_AMEBA_UART1_TX_PIN
+#    error "CONFIG_AMEBA_UART1_TX_PIN not provided"
+#    undef CONFIG_AMEBA_UART1
+#  endif
+#  ifndef CONFIG_AMEBA_UART1_RX_PIN
+#    error "CONFIG_AMEBA_UART1_RX_PIN not provided"
+#    undef CONFIG_AMEBA_UART1
+#  endif
+#endif
+#ifdef CONFIG_AMEBA_UART2
+#  ifndef CONFIG_AMEBA_UART2_TX_PIN
+#    error "CONFIG_AMEBA_UART2_TX_PIN not provided"
+#    undef CONFIG_AMEBA_UART2
+#  endif
+#  ifndef CONFIG_AMEBA_UART2_RX_PIN
+#    error "CONFIG_AMEBA_UART2_RX_PIN not provided"
+#    undef CONFIG_AMEBA_UART2
+#  endif
+#endif
+#ifdef CONFIG_AMEBA_UART3
+#  ifndef CONFIG_AMEBA_UART3_TX_PIN
+#    error "CONFIG_AMEBA_UART3_TX_PIN not provided"
+#    undef CONFIG_AMEBA_UART3
+#  endif
+#  ifndef CONFIG_AMEBA_UART3_RX_PIN
+#    error "CONFIG_AMEBA_UART3_RX_PIN not provided"
+#    undef CONFIG_AMEBA_UART3
+#  endif
+#endif
+/* Is there a serial console? There should be at most one defined.
+ * It could be on any UARTn, n=0,1,2,3
+ */
+
+#if defined(CONFIG_AMEBA_UART0_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART0)
+#  undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE
+#  define HAVE_AMEBA_CONSOLE 1
+#elif defined(CONFIG_AMEBA_UART1_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART1)
+#  undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE
+#  define HAVE_AMEBA_CONSOLE 1
+#elif defined(CONFIG_AMEBA_UART2_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART2)
+#  undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE
+#  define HAVE_AMEBA_CONSOLE 1
+#elif defined(CONFIG_AMEBA_UART3_SERIAL_CONSOLE) && defined(CONFIG_AMEBA_UART3)
+#  undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE
+#  define HAVE_AMEBA_CONSOLE 1
+#else
+#  undef CONFIG_AMEBA_UART0_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART1_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART2_SERIAL_CONSOLE
+#  undef CONFIG_AMEBA_UART3_SERIAL_CONSOLE
+#  undef HAVE_AMEBA_CONSOLE
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#if CONFIG_AMEBA_REGWIDTH == 8
+typedef uint8_t uart_datawidth_t;
+#elif CONFIG_AMEBA_REGWIDTH == 16
+typedef uint16_t uart_datawidth_t;
+#elif CONFIG_AMEBA_REGWIDTH == 32
+typedef uint32_t uart_datawidth_t;
+#endif
+#if CONFIG_AMEBA_ADDRWIDTH == 8
+typedef uint8_t uart_addrwidth_t;
+#elif CONFIG_AMEBA_ADDRWIDTH == 16
+typedef uint16_t uart_addrwidth_t;
+#elif CONFIG_AMEBA_ADDRWIDTH == 32
+typedef uint32_t uart_addrwidth_t;
+#endif
+
+/****************************************************************************
+ * Name: uart_getreg(), uart_putreg(), uart_ioctl()
+ *
+ * Description:
+ *   These functions must be provided by the processor-specific code in order
+ *   to correctly access AMEBA registers
+ *   uart_ioctl() is optional to provide custom IOCTLs
+ *
+ ****************************************************************************/
+
+struct file;  /* Forward reference */
+int uart_ioctl(struct file *filep, int cmd, unsigned long arg);
+#endif /* CONFIG_AMEBA_UART */
+#endif /* __INCLUDE_NUTTX_SERIAL_UART_AMEBA_H */

arch/arm/src/rtl8720c/ameba_vectors.c

@@ -0,0 +1,81 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_vectors.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+extern uint32_t __stack;
+#define IDLE_STACK      ((unsigned)&__stack - 4)
+#ifndef ARMV8M_PERIPHERAL_INTERRUPTS
+#  error ARMV8M_PERIPHERAL_INTERRUPTS must be defined to the number of I/O interrupts to be supported
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/* Chip-specific entrypoint */
+
+extern void ram_start(void);
+
+/* Common exception entrypoint */
+
+extern void exception_common(void);
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+/* The v7m vector table consists of an array of function pointers,
+ * with the first
+ * slot (vector zero) used to hold the initial stack pointer.
+ *
+ * As all exceptions (interrupts) are routed via exception_common,
+ * we just need to
+ * fill this array with pointers to it.
+ *
+ * Note that the [ ... ] designated initialiser is a GCC extension.
+ */
+
+unsigned _vectors[] __attribute__((section(".vectors"))) \
+                    __attribute__((aligned(0x100))) =
+{
+  /* Initial stack */
+
+  IDLE_STACK,
+
+  /* Reset exception handler */
+
+  (unsigned) &ram_start,
+
+  /* Vectors 2 - n point directly at the generic handler */
+
+  [2 ...(15 + ARMV8M_PERIPHERAL_INTERRUPTS)] = (unsigned) &exception_common
+};
+

arch/arm/src/rtl8720c/ameba_wdt.c

@@ -0,0 +1,293 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/ameba_wdt.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/timers/watchdog.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include "hal_wdt.h"
+#if defined(CONFIG_WATCHDOG)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/**
+ * This structure provides the private representation of the "lower-half"
+ * driver state structure.  This structure must be cast-compatible with the
+ * well-known watchdog_lowerhalf_s structure.
+ */
+
+struct ameba_lowerhalf_s
+{
+  FAR const struct watchdog_ops_s  *ops;  /* Lower half operations */
+  uint32_t timeout;                       /* The (actual) selected timeout */
+  uint32_t lastreset;                     /* The last reset time */
+  bool     started;                       /* true: The watchdog timer has
+                                           * been started
+                                           */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* "Lower half" driver methods */
+
+static int      ameba_start(FAR struct watchdog_lowerhalf_s *lower);
+static int      ameba_stop(FAR struct watchdog_lowerhalf_s *lower);
+static int      ameba_keepalive(FAR struct watchdog_lowerhalf_s *lower);
+static int      ameba_getstatus(FAR struct watchdog_lowerhalf_s *lower,
+                                FAR struct watchdog_status_s *status);
+static int      ameba_settimeout(FAR struct watchdog_lowerhalf_s *lower,
+                                 uint32_t timeout);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* "Lower half" driver methods */
+
+static const struct watchdog_ops_s g_wdgops =
+{
+  .start      = ameba_start,
+  .stop       = ameba_stop,
+  .keepalive  = ameba_keepalive,
+  .getstatus  = ameba_getstatus,
+  .settimeout = ameba_settimeout,
+  .capture    = NULL,
+  .ioctl      = NULL,
+};
+
+/* "Lower half" driver state */
+
+static struct ameba_lowerhalf_s g_wdgdev;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ameba_start
+ *
+ * Description:
+ *   Start the watchdog timer, resetting the time to the current timeout,
+ *
+ * Input Parameters:
+ *  lower - A pointer the publicly visible representation
+ *  of the "lower-half" driver state structure.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int ameba_start(FAR struct watchdog_lowerhalf_s *lower)
+{
+  FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower;
+  irqstate_t flags;
+  flags = enter_critical_section();
+  priv->started = true;
+  priv->lastreset = clock_systime_ticks();
+  hal_misc_wdt_enable();
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: ameba_stop
+ *
+ * Description:
+ *   Stop the watchdog timer
+ *
+ * Input Parameters:
+ *   lower - A pointer the publicly visible representation of
+ *           the "lower-half" driver state structure.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int ameba_stop(FAR struct watchdog_lowerhalf_s *lower)
+{
+  FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower;
+  irqstate_t flags;
+  flags = enter_critical_section();
+  hal_misc_wdt_disable();
+  priv->started = false;
+  priv->timeout = 0;
+  priv->lastreset = 0;
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: ameba_keepalive
+ *
+ * Description:
+ *   Reset the watchdog timer to the current timeout value, prevent any
+ *   imminent watchdog timeouts.  This is sometimes referred as "pinging"
+ *   the watchdog timer or "petting the dog".
+ *
+ *   The application program must write in the SAM_WDT_CLEAR register
+ *   at regular intervals during normal operation to prevent an MCU reset.
+ *
+ * Input Parameters:
+ *   lower - A pointer the publicly visible representation
+ *           of the "lower-half" driver state structure.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int ameba_keepalive(FAR struct watchdog_lowerhalf_s *lower)
+{
+  FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower;
+  irqstate_t flags;
+
+  /* Reload the WDT timer */
+
+  flags = enter_critical_section();
+  priv->lastreset = clock_systime_ticks();
+  hal_misc_wdt_refresh();
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: ameba_getstatus
+ *
+ * Description:
+ *   Get the current watchdog timer status
+ *
+ * Input Parameters:
+ *   lower  - A pointer the publicly visible representation of
+ *            the "lower-half" driver state structure.
+ *   status - The location to return the watchdog status information.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int ameba_getstatus(FAR struct watchdog_lowerhalf_s *lower,
+                           FAR struct watchdog_status_s *status)
+{
+  FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower;
+  uint32_t elapsed;
+  uint32_t ticks;
+
+  /* Return the status bit */
+
+  status->flags = WDFLAGS_RESET;
+  if (priv->started)
+    {
+      status->flags |= WDFLAGS_ACTIVE;
+    }
+
+  /* Return the actual timeout in milliseconds */
+
+  status->timeout = priv->timeout;
+
+  /* Get the elapsed time since the last ping */
+
+  ticks   = clock_systime_ticks() - priv->lastreset;
+  elapsed = (int32_t)TICK2MSEC(ticks);
+  if (elapsed > priv->timeout)
+    {
+      elapsed = priv->timeout;
+    }
+
+  /* Return the approximate time until the watchdog timer expiration */
+
+  status->timeleft = priv->timeout - elapsed;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: ameba_settimeout
+ *
+ * Description:
+ *   Set a new timeout value (and reset the watchdog timer)
+ *
+ * Input Parameters:
+ *   lower   - A pointer the publicly visible representation of
+ *             the "lower-half" driver state structure.
+ *   timeout - The new timeout value in millisecnds.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int ameba_settimeout(FAR struct watchdog_lowerhalf_s *lower,
+                            uint32_t timeout)
+{
+  FAR struct ameba_lowerhalf_s *priv = (FAR struct ameba_lowerhalf_s *)lower;
+  irqstate_t flags;
+  flags = enter_critical_section();
+  priv->timeout = timeout;
+  hal_misc_wdt_init(timeout * 1000);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ameba_wdt_initialize
+ *
+ * Description:
+ *   Initialize the WDT watchdog timer.  The watchdog timer
+ *   is initialized and registers as 'devpath'.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the watchdog.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void ameba_wdt_initialize(void)
+{
+  FAR struct ameba_lowerhalf_s *priv = &g_wdgdev;
+
+  /* Initialize the driver state structure. */
+
+  priv->ops = &g_wdgops;
+  (void)watchdog_register(CONFIG_WATCHDOG_DEVPATH,
+                          (FAR struct watchdog_lowerhalf_s *)priv);
+}
+
+#endif /* CONFIG_WATCHDOG */

arch/arm/src/rtl8720c/amebaz_coex.c

@@ -0,0 +1,220 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_coex.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include "amebaz_coex.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define HCI_VENDOR_MAILBOX_CMD 0xfc8f
+
+/* static net_buf_simple *Xiaomi_buf; */
+
+struct rtl_btinfo
+{
+  uint8_t cmd;
+  uint8_t len;
+  uint8_t data[6];
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+unsigned int send_coex_mailbox_to_wifi_from_btapp(uint8_t state)
+{
+  uint8_t para[8];
+  para[0] = 0x45; /* Mailbox ID */
+
+  para[1] = state; /* Data0 */
+
+  para[2] = 0; /* Data1 */
+
+  para[3] = 0; /* Data2 */
+
+  para[4] = 0; /* Data3 */
+
+  para[5] = 0; /* Data4 */
+
+  para[6] = 0; /* Data5 */
+
+  para[7] = 0; /* Data6 */
+
+  rltk_coex_mailbox_to_wifi(para, 8);
+  return 1;
+}
+
+static void rtk_notify_info_to_wifi(uint8_t length, uint8_t *report_info)
+{
+  struct rtl_btinfo *report = (struct rtl_btinfo *)(report_info);
+  if (length)
+    {
+      printf("bt info: cmd %2.2X", report->cmd);
+      printf("bt info: len %2.2X", report->len);
+      printf("bt info: data %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X",
+             report->data[0], report->data[1], report->data[2],
+             report->data[3], report->data[4], report->data[5]);
+    }
+
+  rltk_coex_mailbox_to_wifi(report_info, report->len + 2);
+
+  /* send BT INFO to Wi-Fi driver */
+}
+
+void bt_coex_handle_cmd_complete_evt(uint16_t opcode, uint16_t cause,
+                                              uint8_t total_len, uint8_t *p)
+{
+  (void)cause;
+  if (opcode == HCI_VENDOR_MAILBOX_CMD)
+    {
+      uint8_t status;
+      status = *p++; /* jump the double subcmd */
+
+      total_len--;
+      if (total_len <= 1)
+        {
+          printf("bt_coex_handle_cmd_complete_evt: not reprot to wifi");
+          return ;
+        }
+
+      (void)status;
+      rltk_coex_mailbox_to_wifi(p, total_len);
+
+      /* rtk_parse_vendor_mailbox_cmd_evt(p, total_len, status); */
+    }
+}
+
+void bt_coex_handle_specific_evt(uint8_t *p, uint8_t len)
+{
+  rltk_coex_mailbox_to_wifi(p, len);
+}
+
+#ifndef MIN
+#  define MIN(a,b) (a < b ? a : b)
+#endif
+static const char *bt_hex_real(const void *buf, size_t len)
+{
+  static const char hex[] = "0123456789abcdef";
+  static char str[129];
+  const uint8_t *b = buf;
+  size_t i;
+  len = MIN(len, (sizeof(str) - 1) / 2);
+  for (i = 0; i < len; i++)
+    {
+      str[i * 2]     = hex[b[i] >> 4];
+      str[i * 2 + 1] = hex[b[i] & 0xf];
+    }
+
+  str[i * 2] = '\0';
+  return str;
+}
+
+static inline char *log_strdup(const char *str)
+{
+  return (char *)str;
+}
+
+#define bt_hex(buf, len) log_strdup(bt_hex_real(buf, len))
+static void bt_coex_dump_buf(net_buf_simple *tmp_buf)
+{
+  printf("\n\r[%s] len=%d, buf = % s\n\r", __func__,
+                                           tmp_buf->len,
+                                           bt_hex(tmp_buf->data,
+                                           tmp_buf->len));
+}
+
+static int bt_coex_unpack_xiaomi_vendor_cmd(net_buf_simple *tmp_buf)
+{
+  if (tmp_buf-> data[0] == 0x25 && tmp_buf-> data[1] == 0x00)
+    {
+      tmp_buf -> data += 2;
+      tmp_buf -> len -= 2;
+      return 1;
+    }
+
+  else
+    {
+      printf("[rtk_coex]Xiaomi vendor header not match.\n\r");
+      return -1;
+    }
+}
+
+bool bt_coex_handle_xiaomi_evt(net_buf_simple *xiaomi_buf)
+{
+  /* bt_coex_dump_buf(xiaomi_buf); */
+
+  bt_coex_unpack_xiaomi_vendor_cmd(xiaomi_buf);
+
+  /* bt_coex_dump_buf(xiaomi_buf); */
+
+  rltk_coex_mailbox_to_wifi(xiaomi_buf->data, xiaomi_buf->len);
+  return true;
+}
+
+typedef struct bt_sw_mailbox_info_s
+{
+  uint8_t data[8];
+}bt_sw_mailbox_info_t;
+
+static bt_sw_mailbox_info_t scan_enable;
+
+unsigned int bt_coex_sw_mailbox_set(unsigned int mailbox_control)
+{
+#if 0 /* This function need to be removed */
+
+  uint8_t mailbox_len = 8;
+  memset(&scan_enable, 0, sizeof(scan_enable));
+  switch (mailbox_control)
+    {
+    case BT_SW_MAILBOX_SCAN_OFF:
+      scan_enable.data[0] = 0x27;
+      scan_enable.data[1] = 6;
+      rtk_notify_info_to_wifi(mailbox_len, scan_enable.data);
+      break;
+    case BT_SW_MAILBOX_SCAN_ON:
+      scan_enable.data[0] = 0x27;
+      scan_enable.data[1] = 6;
+      scan_enable.data[5] = (0x0 | 0x1 << 5); /* BT scan EN bit */
+
+      rtk_notify_info_to_wifi(mailbox_len, scan_enable.data);
+      break;
+    default:
+      printf("[Err %s]No such sw mailbox command.\n\r", __func__);
+      break;
+    }
+
+  return true;
+#else
+  return true;
+#endif
+}
+
+void bt_coex_init(void)
+{
+  vendor_cmd_init(NULL);
+}
+

arch/arm/src/rtl8720c/amebaz_coex.h

@@ -0,0 +1,75 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_coex.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+/*  READ_ME
+ * <b>Example usage</b>
+ * \code{ble_app_main.c}
+ *
+ * void app_le_gap_init(void)
+ * {
+ *    ....
+ *    bt_coex_init();
+ * }
+ *
+ */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BT_SW_MAILBOX_SCAN_OFF  0x00
+#define BT_SW_MAILBOX_SCAN_ON   0x01
+
+typedef struct net_buf_simple_s
+{
+  /* * Pointer to the start of data in the buffer. */
+
+  uint8_t *data;
+
+  /* * Length of the data behind the data pointer. */
+
+  uint16_t len;
+
+  /* * Amount of data that this buffer can store. */
+
+  uint16_t size;
+  /** Start of the data storage. Not to be accessed directly
+   *  (the data pointer should be used instead).
+   */
+
+  uint8_t *__buf;
+} net_buf_simple;
+
+void bt_coex_handle_cmd_complete_evt(uint16_t opcode,
+                                              uint16_t cause,
+                                              uint8_t total_len,
+                                              uint8_t *p);
+void bt_coex_handle_specific_evt(uint8_t *p, uint8_t len);
+bool bt_coex_handle_xiaomi_evt(net_buf_simple *xiaomi_buf);
+unsigned int bt_coex_sw_mailbox_set(unsigned int mailbox_control);
+void bt_coex_init(void);
+unsigned int send_coex_mailbox_to_wifi_from_btapp(uint8_t state);
+

arch/arm/src/rtl8720c/amebaz_depend.h

@@ -0,0 +1,181 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_depend.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DEPEND_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DEPEND_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <arpa/inet.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/kthread.h>
+typedef struct  __queue         _queue;
+typedef void (*thread_func_t)(void *context);
+typedef struct
+{
+  volatile int counter;
+} atomic_t;
+struct list_head
+{
+  struct list_head    *next;
+  struct list_head    *prev;
+};
+struct  __queue
+{
+  struct  list_head   queue;
+  void                *lock;
+};
+struct task_struct
+{
+  const char          *name;
+  void                *priv;
+  void                *wsema;
+  void                *tsema;
+  uint32_t blocked;
+  uint32_t running;
+};
+struct nthread_wrapper
+{
+  int pid;
+  thread_func_t       func;
+  void                *thctx;
+};
+struct ntimer_wrapper
+{
+  struct work_s       work;
+  void (*callback)(void *context);
+};
+struct osdep_service_ops
+{
+  uint8_t   *(*rtw_vmalloc)(uint32_t n);
+  uint8_t   *(*rtw_zvmalloc)(uint32_t n);
+  void (*rtw_vmfree)(uint8_t *pbuf, uint32_t n);
+  uint8_t   *(*rtw_malloc)(uint32_t n);
+  uint8_t   *(*rtw_zmalloc)(uint32_t n);
+  void (*rtw_mfree)(uint8_t *pbuf, uint32_t n);
+  void (*rtw_memcpy)(void *dst, void *src, uint32_t n);
+  int (*rtw_memcmp)(void *dst, void *src, uint32_t n);
+  void (*rtw_memset)(void *pbuf, int c, uint32_t n);
+  void (*rtw_init_sema)(void **sema, int init_val);
+  void (*rtw_free_sema)(void **sema);
+  void (*rtw_up_sema)(void **sema);
+  void (*rtw_up_sema_from_isr)(void **sema);
+  uint32_t (*rtw_down_timeout_sema)(void **sema, uint32_t timeout);
+  void (*rtw_mutex_init)(void **pmutex);
+  void (*rtw_mutex_free)(void **pmutex);
+  void (*rtw_mutex_get)(void **pmutex);
+  int (*rtw_mutex_get_timeout)(void **pmutex, uint32_t timeout_ms);
+  void (*rtw_mutex_put)(void **pmutex);
+  void (*rtw_enter_critical)(void **plock, unsigned long *pirql);
+  void (*rtw_exit_critical)(void **plock, unsigned long *pirql);
+  void (*rtw_enter_critical_from_isr)(void **plock, unsigned long *pirql);
+  void (*rtw_exit_critical_from_isr)(void **plock, unsigned long *pirql);
+  void (*rtw_enter_critical_bh)(void **plock, unsigned long *pirql);
+  void (*rtw_exit_critical_bh)(void **plock, unsigned long *pirql);
+  int (*rtw_enter_critical_mutex)(void **pmutex, unsigned long *pirql);
+  void (*rtw_exit_critical_mutex)(void **pmutex, unsigned long *pirql);
+  void (*rtw_cpu_lock)(void);
+  void (*rtw_cpu_unlock)(void);
+  void (*rtw_spinlock_init)(void **plock);
+  void (*rtw_spinlock_free)(void **plock);
+  void (*rtw_spin_lock)(void **plock);
+  void (*rtw_spin_unlock)(void **plock);
+  void (*rtw_spinlock_irqsave)(void **plock, unsigned long *pirql);
+  void (*rtw_spinunlock_irqsave)(void **plock, unsigned long *pirql);
+  int (*rtw_init_xqueue)(void **queue, const char *name, uint32_t size,
+                         uint32_t len);
+  int (*rtw_push_to_xqueue)(void **queue, void *message,
+                            uint32_t timeout_ms);
+  int (*rtw_pop_from_xqueue)(void **queue, void *message,
+                             uint32_t timeout_ms);
+  int (*rtw_deinit_xqueue)(void **queue);
+  uint32_t (*rtw_get_current_time)(void);
+  uint32_t (*rtw_systime_to_ms)(uint32_t systime);
+  uint32_t (*rtw_systime_to_sec)(uint32_t systime);
+  uint32_t (*rtw_ms_to_systime)(uint32_t ms);
+  uint32_t (*rtw_sec_to_systime)(uint32_t sec);
+  void (*rtw_msleep_os)(int ms);
+  void (*rtw_usleep_os)(int us);
+  void (*rtw_mdelay_os)(int ms);
+  void (*rtw_udelay_os)(int us);
+  void (*rtw_yield_os)(void);
+  void (*ATOMIC_SET)(atomic_t *v, int i);
+  int (*ATOMIC_READ)(atomic_t *v);
+  void (*ATOMIC_ADD)(atomic_t *v, int i);
+  void (*ATOMIC_SUB)(atomic_t *v, int i);
+  void (*ATOMIC_INC)(atomic_t *v);
+  void (*ATOMIC_DEC)(atomic_t *v);
+  int (*ATOMIC_ADD_RETURN)(atomic_t *v, int i);
+  int (*ATOMIC_SUB_RETURN)(atomic_t *v, int i);
+  int (*ATOMIC_INC_RETURN)(atomic_t *v);
+  int (*ATOMIC_DEC_RETURN)(atomic_t *v);
+  uint64_t (*rtw_modular64)(uint64_t x, uint64_t y);
+  int (*rtw_get_random_bytes)(void *dst, uint32_t size);
+  uint32_t (*rtw_get_free_heap_size)(void);
+  int (*rtw_create_task)(struct task_struct *task, const char *name,
+                         uint32_t stack_size,
+                         uint32_t priority, thread_func_t func, void *thctx);
+  void (*rtw_delete_task)(struct task_struct *task);
+  void (*rtw_wakeup_task)(struct task_struct *task);
+  void (*rtw_thread_enter)(char *name);
+  void (*rtw_thread_exit)(void);
+  void      *(*rtw_timer_create)(const signed char *pctimername,
+                                unsigned long xtimerperiodinticks,
+                                uint32_t uxautoreload,
+                                void *pvtimerid,
+                                thread_func_t pxcallbackfunction);
+  uint32_t (*rtw_timer_delete)(void *xtimer, unsigned long xblocktime);
+  uint32_t (*rtw_timer_is_timer_active)(void *xtimer);
+  uint32_t (*rtw_timer_stop)(void *xtimer, unsigned long xblocktime);
+  uint32_t (*rtw_timer_change_period)(void *xtimer, unsigned long xnewperiod,
+                                    unsigned long xblocktime);
+  void      *(*rtw_timer_get_id)(void *xtimer);
+  uint32_t (*rtw_timer_start)(void *xtimer, unsigned long xblocktime);
+  uint32_t (*rtw_timer_start_from_isr)(void *xtimer,
+                                    long *pxhigherprioritytaskwoken);
+  uint32_t (*rtw_timer_stop_from_isr)(void *xtimer,
+                                   long *pxhigherprioritytaskwoken);
+  uint32_t (*rtw_timer_reset_from_isr) (void *xtimer,
+                                      long *pxhigherprioritytaskwoken);
+  uint32_t (*rtw_timer_change_period_from_isr) (void *xtimer,
+                                            unsigned long xnewperiod,
+                                            long *pxhigherprioritytaskwoken);
+  uint32_t (*rtw_timer_reset)(void *xtimer, unsigned long xblocktime);
+  void (*rtw_acquire_wakelock)(void);
+  void (*rtw_release_wakelock)(void);
+  void (*rtw_wakelock_timeout)(uint32_t ms);
+  uint8_t (*rtw_get_scheduler_state)(void);
+  void (*rtw_create_secure_context)(uint32_t n);
+};
+#endif

arch/arm/src/rtl8720c/amebaz_driver.h

@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_driver.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DRIVER_H
+#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DRIVER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <semaphore.h>
+#include <nuttx/wdog.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/net/netdev.h>
+#include "amebaz_wlan.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define AMEBAZ_SCAN_AP_COUNT        (10)
+enum
+{
+  AMEBAZ_STATUS_DONE = 0,
+  AMEBAZ_STATUS_DISABLED,
+  AMEBAZ_STATUS_RUN,
+  AMEBAZ_STATUS_TIMEOUT,
+};
+
+enum
+{
+  AMEBAZ_ASSOCIATE_SSID    = 0x1,
+  AMEBAZ_ASSOCIATE_BSSID   = 0x2,
+  AMEBAZ_ASSOCIATE_ALG     = 0x4,
+  AMEBAZ_ASSOCIATE_CHANNEL = 0x8,
+  AMEBAZ_ASSOCIATE_MASK    = 0xf,
+};
+
+struct amebaz_state_s
+{
+  sem_t                   mutex;
+  struct wdog_s           timeout;
+  int status;
+};
+
+struct amebaz_associate_s
+{
+  rtw_ssid_t              ssid;
+  rtw_mac_t               mac;
+  uint8_t alg;
+  unsigned int channel;
+  uint8_t mask;
+};
+
+struct amebaz_dev_s
+{
+  struct net_driver_s       dev;
+  int devnum;
+  struct amebaz_state_s     scan;
+  struct amebaz_state_s     conn;
+  struct work_s             pollwork;
+  struct wdog_s             txpoll;
+  struct sk_buff            *curr;
+  int mode;
+  struct amebaz_associate_s assoc;
+  rtw_scan_result_t         scan_data[AMEBAZ_SCAN_AP_COUNT];
+  unsigned int scan_count;
+  unsigned char             country[2];
+};
+
+int amebaz_wl_start_scan(FAR struct amebaz_dev_s *priv,
+                         struct iwreq *iwr);
+int amebaz_wl_get_scan_results(FAR struct amebaz_dev_s *priv,
+                               struct iwreq *iwr);
+int amebaz_wl_set_encode_ext(FAR struct amebaz_dev_s *priv,
+                             struct iwreq *iwr);
+int amebaz_wl_get_encode_ext(FAR struct amebaz_dev_s *priv,
+                             struct iwreq *iwr);
+int amebaz_wl_set_ssid(FAR struct amebaz_dev_s *priv,
+                       struct iwreq *iwr);
+int amebaz_wl_set_bssid(FAR struct amebaz_dev_s *priv,
+                        struct iwreq *iwr);
+int amebaz_wl_set_mode(FAR struct amebaz_dev_s *priv,
+                       struct iwreq *iwr);
+int amebaz_wl_set_country(FAR struct amebaz_dev_s *priv,
+                          struct iwreq *iwr);
+int amebaz_wl_get_freq(FAR struct amebaz_dev_s *priv,
+                       struct iwreq *iwr);
+int amebaz_wl_set_freq(FAR struct amebaz_dev_s *priv,
+                       struct iwreq *iwr);
+int amebaz_wl_process_command(FAR struct amebaz_dev_s *priv,
+                              int cmd, void *req);
+void amebaz_wl_connection_handler(int index,
+                                  union iwreq_data *wrqu, char *extra);
+void amebaz_wl_scan_handler(int index,
+                            union iwreq_data *wrqu, char *extra);
+void amebaz_wl_netif_info_handler(int index, void *dev,
+                                  unsigned char *addr);
+void amebaz_wl_notify_rx_handler(int index, unsigned int len);
+
+#endif /* __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_DRIVER_H */

arch/arm/src/rtl8720c/amebaz_hci_board.c

@@ -0,0 +1,832 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_hci_board.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include <hal_api.h>
+#include <hal_efuse.h>
+#include <hal_sys_ctrl.h>
+#include <nuttx/config.h>
+#include "amebaz_hci_board.h"
+#include "ameba_efuse.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BT_LGC_EFUSE_LEN           0x20
+#define BT_PHY_EFUSE_LEN           0x12
+#define BT_PHY_EFUSE_BASE          0x100
+#define BT_LGC_EFUSE_OFFSET        0x190
+#define BT_MAC_ADDR_LEN            6
+#define BT_CONFIG_SIGNATURE        0x8723ab55
+#define BT_CONFIG_HEADER_LEN       6
+#define EFUSE_SW_USE_FLASH_PATCH   BIT0
+#define EFUSE_SW_BT_FW_LOG         BIT1
+#define EFUSE_SW_RSVD              BIT2
+#define EFUSE_SW_IQK_HCI_OUT       BIT3
+#define EFUSE_SW_UPPERSTACK_SWITCH BIT4
+#define EFUSE_SW_TRACE_SWITCH      BIT5
+#define EFUSE_SW_DRIVER_DEBUG_LOG  BIT6
+#define EFUSE_SW_RSVD2             BIT7
+#define LEFUSE(x)                 (x-0x190)
+#define FLASH_BT_PARA_ADDR        (SYS_DATA_FLASH_BASE + 0xff0)
+#define CHECK_SW(x)               (HAL_READ32(SPI_FLASH_BASE, FLASH_BT_PARA_ADDR) &x)
+#define MERGE_PATCH_ADDRESS       0x110000
+#define LE_ARRAY_TO_UINT16(u16, a)  {     \
+  u16 = ((uint16_t)(*(a + 0)) << 0) +   \
+        ((uint16_t)(*(a + 1)) << 8);      \
+  }
+
+#define LE_ARRAY_TO_UINT32(u32, a) {    \
+  u32 = ((uint32_t)(*(a + 0)) <<  0)+ \
+        ((uint32_t)(*(a + 1)) <<   8)+  \
+        ((uint32_t)(*(a + 2)) << 16)+ \
+        ((uint32_t)(*(a + 3)) << 24);   \
+  }
+
+#define LE_UINT32_TO_ARRAY(a, u32) {                 \
+    *((uint8_t *)(a) + 0) = (uint8_t)((u32) >>  0); \
+    *((uint8_t *)(a) + 1) = (uint8_t)((u32) >>  8); \
+    *((uint8_t *)(a) + 2) = (uint8_t)((u32) >> 16); \
+    *((uint8_t *)(a) + 3) = (uint8_t)((u32) >> 24); \
+  }
+
+#define LE_STREAM_TO_UINT8(u8, s) {     \
+  u8 = (uint8_t)(*s);                   \
+  s += 1;                               \
+}
+
+#define LE_STREAM_TO_UINT16(u16, s) {   \
+  u16 = ((uint16_t)(*(s + 0)) << 0) + \
+        ((uint16_t)(*(s + 1)) << 8);    \
+  s += 2;                               \
+}
+
+#define LE_UINT16_TO_STREAM(s, u16) {   \
+  *s++ = (uint8_t)((u16) >> 0);         \
+  *s++ = (uint8_t)((u16) >> 8);         \
+}
+
+#define LE_STREAM_TO_UINT32(u32, s) {    \
+  u32 = ((uint32_t)(*(s + 0)) <<  0) + \
+        ((uint32_t)(*(s + 1)) <<   8)  + \
+        ((uint32_t)(*(s + 2)) << 16) + \
+        ((uint32_t)(*(s + 3)) << 24);    \
+  s += 4;                                \
+}
+
+enum _RT_DEV_LOCK_E
+{
+  RT_DEV_LOCK_EFUSE  = 0,
+  RT_DEV_LOCK_FLASH  = 1,
+  RT_DEV_LOCK_CRYPTO = 2,
+  RT_DEV_LOCK_PTA    = 3,
+  RT_DEV_LOCK_WLAN   = 4,
+  RT_DEV_LOCK_MAX    = 5
+};
+
+typedef struct
+{
+  uint32_t IQK_XX;
+  uint32_t IQK_YY;
+  uint16_t IDAC;
+  uint16_t QDAC;
+  uint16_t IDAC2;
+  uint16_t QDAC2;
+} IQK_T;
+
+extern void     rtw_msleep_os(int ms);
+extern void     rtw_mfree(uint8_t *pbuf, uint32_t n);
+extern void     device_mutex_lock(uint32_t device);
+extern void     device_mutex_unlock(uint32_t device);
+extern uint32_t bt_lok_write(uint16_t idac,
+                             uint16_t qdac, uint16_t idac2, uint16_t qdac2);
+extern uint32_t bt_dck_write(uint8_t q_dck, uint8_t i_dck);
+extern uint32_t bt_iqk_8710c(IQK_T *cal_data, uint8_t store);
+extern uint32_t bt_flatk_8710c(uint16_t txgain_flatk);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint8_t        hci_phy_efuse[BT_PHY_EFUSE_LEN] =
+{
+  0
+};
+
+static uint8_t        hci_lgc_efuse[BT_LGC_EFUSE_LEN] =
+{
+  0
+};
+
+static IQK_T          hci_iqk_data =
+{
+  0x100,
+  0x00,
+  0x20,
+  0x20,
+  0x20,
+  0x20
+};
+
+static uint8_t        *rtl_actual_command = NULL;
+static uint32_t rtl_actual_command_size;
+extern const uint8_t  rtl_vendor_command[];
+extern uint32_t rtl_vendor_command_size;
+static uint32_t hci_cfg_baudrate;
+static uint8_t rtl_vendor_init_config[] =
+{
+  0x55, 0xab, 0x23, 0x87,                                 /* header */
+
+  0x32, 0x00,                                             /* Config length: header + len + preload */
+
+  0x30, 0x00, 0x06, 0x99, 0x88, 0x77, 0x44, 0x55, 0x66,   /* BT MAC address */
+
+  0x0c, 0x00, 0x04, 0x04, 0x50, 0xf7, 0x05,               /* Baudrate 921600 */
+
+  0x18, 0x00, 0x01, 0x5c,                                 /* flow control */
+
+  0x94, 0x01, 0x06, 0x0a, 0x08, 0x00, 0x00, 0x2e, 0x07,   /* phy flatk */
+
+  0x9f, 0x01, 0x05, 0x2a, 0x2a, 0x2a, 0x2a, 0x1c,         /* unknow 1 */
+
+  0xa4, 0x01, 0x04, 0xfe, 0xfe, 0xfe, 0xfe,               /* unknow 2 */
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+static uint32_t cal_bit_shift(uint32_t mask)
+{
+  uint32_t i;
+  for (i = 0; i < 31; i++)
+    {
+      if ((mask >> i) & 0x1)
+        {
+          break;
+        }
+    }
+
+  return i;
+}
+
+static void set_reg_val(uint32_t reg, uint32_t mask, uint32_t val)
+{
+  if (reg % 4)
+    {
+      return;
+    }
+
+  uint32_t data = HAL_READ32(reg, 0);
+  data = ((data & (~mask)) | (val << cal_bit_shift(mask)));
+  HAL_WRITE32(reg, 0, data);
+}
+
+static int hci_iqk_phy_efuse_valid(FAR IQK_T           *iqk_data)
+{
+  if ((hci_phy_efuse[3] == 0xff) &&
+      (hci_phy_efuse[4] == 0xff) &&
+      (hci_phy_efuse[5] == 0xff) &&
+      (hci_phy_efuse[6] == 0xff))
+    {
+      /* No Phy Efuse Data */
+
+      return -EIO;
+    }
+
+  else
+    {
+      /* Phy Efuse Has Data */
+
+      iqk_data->IQK_XX = hci_phy_efuse[3] | hci_phy_efuse[4] << 8;
+      iqk_data->IQK_YY = hci_phy_efuse[5] | hci_phy_efuse[6] << 8;
+      iqk_data->QDAC   = hci_phy_efuse[0x0c];
+      iqk_data->IDAC   = hci_phy_efuse[0x0d];
+      iqk_data->QDAC2  = hci_phy_efuse[0x0e];
+      iqk_data->IDAC2  = hci_phy_efuse[0x0f];
+      return 0;
+    }
+}
+
+static int hci_iqk_lgc_efuse_valid(FAR IQK_T *iqk_data)
+{
+  if ((hci_lgc_efuse[0x16] == 0xff) &&
+      (hci_lgc_efuse[0x17] == 0xff) &&
+      (hci_lgc_efuse[0x18] == 0xff) &&
+      (hci_lgc_efuse[0x19] == 0xff))
+    {
+      /* No Lgc Efuse Data */
+
+      return -EIO;
+    }
+  else
+    {
+      /* Lgc Efuse Has Data */
+
+      iqk_data->IQK_XX = (uint32_t)(((uint32_t)hci_lgc_efuse[0x17]) << 8) |
+                         hci_lgc_efuse[0x16];
+      iqk_data->IQK_YY = (uint32_t)(((uint32_t)hci_lgc_efuse[0x19]) << 8) |
+                         hci_lgc_efuse[0x18];
+      iqk_data->QDAC   = hci_lgc_efuse[0x1a];
+      iqk_data->IDAC   = hci_lgc_efuse[0x1b];
+      iqk_data->QDAC2  = hci_lgc_efuse[0x1c];
+      iqk_data->IDAC2  = hci_lgc_efuse[0x1d];
+      return 0;
+    }
+}
+
+int hci_check_iqk(void)
+{
+  IQK_T iqk_data;
+
+  if (!hci_lgc_efuse[LEFUSE(0x1a1)] & BIT0)
+    {
+      /* Use Fix Logic Efuse */
+
+      if (0 == hci_iqk_lgc_efuse_valid(&iqk_data))
+        {
+          bt_lok_write(iqk_data.IDAC, iqk_data.QDAC, iqk_data.IDAC2,
+                       iqk_data.QDAC2);
+          hci_phy_efuse[0] = 0;
+          hci_phy_efuse[1] = hci_phy_efuse[1] & (~BIT0);
+          hci_phy_efuse[3] = iqk_data.IQK_XX & 0xff;
+          hci_phy_efuse[4] = (iqk_data.IQK_XX >> 8) & 0xff;
+          hci_phy_efuse[5] = iqk_data.IQK_YY & 0xff;
+          hci_phy_efuse[6] = (iqk_data.IQK_YY >> 8) & 0xff;
+          return 0;
+        }
+
+      /* No Logic Efuse Data */
+
+      return -EIO;
+    }
+
+  if (0 == hci_iqk_phy_efuse_valid(&iqk_data))
+    {
+      if (hci_phy_efuse[0] != 0)
+        {
+          bt_dck_write(hci_phy_efuse[0x0e], hci_phy_efuse[0x0f]);
+        }
+
+      bt_lok_write(iqk_data.IDAC, iqk_data.QDAC, iqk_data.IDAC2,
+                   iqk_data.QDAC2);
+      return 0;
+    }
+
+  else if (0 == hci_iqk_lgc_efuse_valid(&iqk_data))
+    {
+      bt_lok_write(iqk_data.IDAC, iqk_data.QDAC, iqk_data.IDAC2,
+                   iqk_data.QDAC2);
+      hci_phy_efuse[0]    = 0;
+      hci_phy_efuse[1]    = hci_phy_efuse[1] & (~BIT0);
+      hci_phy_efuse[3]    = iqk_data.IQK_XX & 0xff;
+      hci_phy_efuse[4]    = (iqk_data.IQK_XX >> 8) & 0xff;
+      hci_phy_efuse[5]    = iqk_data.IQK_YY & 0xff;
+      hci_phy_efuse[6]    = (iqk_data.IQK_YY >> 8) & 0xff;
+      hci_phy_efuse[0x0e] = hci_lgc_efuse[0x1e];
+      hci_phy_efuse[0x0f] = hci_lgc_efuse[0x1f];
+      bt_dck_write(hci_phy_efuse[0x0e], hci_phy_efuse[0x0f]);
+      return 0;
+    }
+
+  else
+    {
+      /* No IQK LOK Data, Need Start LOK */
+
+      return -EIO;
+    }
+}
+
+int hci_start_iqk(void)
+{
+  if (_FAIL == bt_iqk_8710c(&hci_iqk_data, 0))
+    {
+      /* IQK Fail, Ensure Connected */
+
+      return -EIO;
+    }
+
+  bt_lok_write(hci_iqk_data.IDAC, hci_iqk_data.QDAC, hci_iqk_data.IDAC2,
+               hci_iqk_data.QDAC2);
+  hci_phy_efuse[0] = 0;
+  hci_phy_efuse[1] = hci_phy_efuse[1] & (~BIT0);
+  hci_phy_efuse[3] = hci_iqk_data.IQK_XX & 0xff;
+  hci_phy_efuse[4] = (hci_iqk_data.IQK_XX >> 8) & 0xff;
+  hci_phy_efuse[5] = hci_iqk_data.IQK_YY & 0xff;
+  hci_phy_efuse[6] = (hci_iqk_data.IQK_YY >> 8) & 0xff;
+  return 0;
+}
+
+int hci_set_init_config_mac(FAR uint8_t *addr, uint8_t diffvalue)
+{
+  for (uint8_t i = 0; i < BT_MAC_ADDR_LEN; i++)
+    {
+      rtl_vendor_init_config[9 + i] = addr[(BT_MAC_ADDR_LEN - 1) - i];
+    }
+
+  rtl_vendor_init_config[9] -= diffvalue;
+  return 0;
+}
+
+int hci_get_baudrate(FAR uint32_t *bt_baudrate, FAR uint32_t *uart_baudrate)
+{
+  typedef struct
+  {
+    uint32_t bt_baudrate;
+    uint32_t uart_baudrate;
+  }baudrate_map;
+
+  const baudrate_map maps[] =
+  {
+    {0x0000701d, 115200},
+    {0x0252c00a, 230400},
+    {0x05f75004, 921600},
+    {0x00005004, 1000000},
+    {0x04928002, 1500000},
+    {0x00005002, 2000000},
+    {0x0000b001, 2500000},
+    {0x04928001, 3000000},
+    {0x052a6001, 3500000},
+    {0x00005001, 4000000},
+  };
+
+  uint32_t i;
+  *bt_baudrate = hci_cfg_baudrate;
+  for (i = 0; i < sizeof(maps); i++)
+    {
+      if (*bt_baudrate  == maps[i].bt_baudrate)
+        {
+          break;
+        }
+    }
+
+  if (i == sizeof(maps))
+    {
+      return -EINVAL;
+    }
+
+  *uart_baudrate = maps[i].uart_baudrate;
+  return 0;
+}
+
+int hci_find_fw_patch(uint8_t chipid)
+{
+#if 0
+  const uint8_t single_patch_signature[4] =
+  {
+    0xfd,
+    0x63,
+    0x05,
+    0x62
+  };
+
+  const uint8_t merged_patch_signature[8] =
+  {
+    0x52,
+    0x65,
+    0x61,
+    0x6c,
+    0x74,
+    0x65,
+    0x63,
+    0x68
+  };
+
+  phal_spic_adaptor_t flash;
+
+  /* FIXME: Distiguish Normal and MP Ptach (rltk_bt_get_patch_code) */
+
+  const uint8_t *fw_patch        = rtl_vendor_command;
+  uint32_t fw_patch_len    = rtl_vendor_command_size;
+  uint32_t fw_patch_offset = 0;
+  uint32_t lmp_subversion  = 0;
+  uint16_t num_of_patch    = 0;
+  uint16_t chipid_in_fw    = 0;
+  uint8_t i;
+  if (!CHECK_SW(EFUSE_SW_USE_FLASH_PATCH))
+    {
+      /* Check flash img */
+
+      uint8_t tmp_patch_head[8];
+      hal_flash_stream_read(&flash, MERGE_PATCH_ADDRESS, 8, tmp_patch_head);
+      if (!memcmp(tmp_patch_head, merged_patch_signature,
+                  sizeof(merged_patch_signature)))
+        {
+          /* use the changed patch */
+
+          hal_flash_stream_read(&flash, MERGE_PATCH_ADDRESS + 8, 4,
+                                (uint8_t *)&lmp_subversion);
+          hal_flash_stream_read(&flash, MERGE_PATCH_ADDRESS + 12, 2,
+                                (uint8_t *)&num_of_patch);
+          for (i = 0 ; i < num_of_patch; i++)
+            {
+              hal_flash_stream_read(&flash,
+                                    MERGE_PATCH_ADDRESS + 0x0e + 2 * i, 2,
+                                    (uint8_t *)&chipid_in_fw);
+              if (chipid_in_fw == chipid)
+                {
+                  hal_flash_stream_read(&flash,
+                                        MERGE_PATCH_ADDRESS + 0x0e \
+                                        + 2 * num_of_patch + 2 * i,
+                                        2, (uint8_t *)&fw_patch_len);
+                  hal_flash_stream_read(&flash,
+                                        MERGE_PATCH_ADDRESS + 0x0e \
+                                        + 4 * num_of_patch + 4 * i,
+                                        4, (uint8_t *)&fw_patch_offset);
+                  break;
+                }
+            }
+
+          rtl_actual_command = (uint8_t *)rtw_zmalloc(fw_patch_len);
+          if (!rtl_actual_command)
+            {
+              return -EIO;
+            }
+
+          hal_flash_stream_read(&flash,
+                                MERGE_PATCH_ADDRESS + fw_patch_offset,
+                                fw_patch_len, rtl_actual_command);
+          LE_UINT32_TO_ARRAY(rtl_actual_command + fw_patch_len - 4,
+                             lmp_subversion);
+          return 0;
+        }
+    }
+
+  if (!memcmp(fw_patch, single_patch_signature,
+              sizeof(single_patch_signature)))
+    {
+      /* Use Single Patch, Do Nothing */
+
+      rtl_actual_command      = fw_patch;
+      rtl_actual_command_size = fw_patch_len;
+    }
+
+  else if (!memcmp(fw_patch, merged_patch_signature,
+                   sizeof(merged_patch_signature)))
+    {
+      /* Use Merged Patch */
+
+      LE_ARRAY_TO_UINT32(lmp_subversion, fw_patch + 0x08);
+      LE_ARRAY_TO_UINT16(num_of_patch, fw_patch + 0x0c);
+      for (i = 0; i < num_of_patch; i++)
+        {
+          LE_ARRAY_TO_UINT16(chipid_in_fw, fw_patch + 0x0e + 2 * i);
+          if (chipid_in_fw == chipid)
+            {
+              LE_ARRAY_TO_UINT16(fw_patch_len,
+                                 fw_patch + 0x0e + 2 * num_of_patch + 2 * i);
+              LE_ARRAY_TO_UINT32(fw_patch_offset,
+                                 fw_patch + 0x0e + 4 * num_of_patch + 4 * i);
+              break;
+            }
+        }
+
+      if (i >= num_of_patch)
+        {
+          /* No Match Patch Found */
+
+          return -EIO;
+        }
+
+      else
+        {
+          rtl_actual_command      = (uint8_t *)rtw_zmalloc(fw_patch_len);
+          rtl_actual_command_size = fw_patch_len;
+          if (!rtl_actual_command)
+            {
+              /* Malloc rtl_actual_command failed */
+
+              return -EIO;
+            }
+
+          else
+            {
+              rtw_memcpy(rtl_actual_command, fw_patch + fw_patch_offset,
+                         fw_patch_len);
+              LE_UINT32_TO_ARRAY(rtl_actual_command + fw_patch_len - 4,
+                                 lmp_subversion);
+            }
+        }
+    }
+
+  else
+    {
+      /* Something is Wrong with the Patch */
+
+      return -EIO;
+    }
+
+#else
+
+  /* FIXME: Dummy Here */
+
+  rtl_actual_command      = (uint8_t *)&rtl_vendor_command[0];
+  rtl_actual_command_size = rtl_vendor_command_size;
+#endif
+  return 0;
+}
+
+int hci_fetch_command(FAR uint8_t *command)
+{
+  unsigned int config_size = sizeof(rtl_vendor_init_config);
+  static unsigned int command_offset;
+  int fragment_size = 0;
+  int index;
+  if (command_offset >= config_size + rtl_actual_command_size)
+    {
+      if (rtl_actual_command && rtl_actual_command != rtl_vendor_command)
+        {
+          rtw_mfree(rtl_actual_command, rtl_actual_command_size);
+        }
+
+      return AMEBAZ_COMMAND_DONE;
+    }
+
+  if (command_offset < rtl_actual_command_size)
+    {
+      if (command_offset + AMEBAZ_COMMAND_FRAGMENT_SIZE
+                                            > rtl_actual_command_size)
+        {
+          fragment_size = rtl_actual_command_size - command_offset;
+        }
+
+      else
+        {
+          fragment_size = AMEBAZ_COMMAND_FRAGMENT_SIZE;
+        }
+
+      memcpy(command + 5, rtl_actual_command + command_offset,
+             fragment_size);
+      command_offset += fragment_size;
+    }
+
+  if (command_offset >= rtl_actual_command_size)
+    {
+      int config_offset = command_offset - rtl_actual_command_size;
+      int config_len = config_size - config_offset;
+      if (fragment_size < AMEBAZ_COMMAND_FRAGMENT_SIZE)
+        {
+          int free = AMEBAZ_COMMAND_FRAGMENT_SIZE - fragment_size;
+          int copy_size;
+          if (config_len > free)
+            {
+              copy_size = free;
+            }
+
+          else
+            {
+              copy_size = config_len;
+            }
+
+          memcpy(command + 5 + fragment_size,
+                 rtl_vendor_init_config + config_offset, copy_size);
+          command_offset += copy_size;
+          fragment_size += copy_size;
+        }
+    }
+
+  index = (command_offset / AMEBAZ_COMMAND_FRAGMENT_SIZE) - 1;
+  if (command_offset % AMEBAZ_COMMAND_FRAGMENT_SIZE > 0)
+    {
+      index++;
+    }
+
+  if (command_offset >= config_size + rtl_actual_command_size)
+    {
+      index |= 0x80;
+    }
+
+  command[3] = fragment_size + 1;
+  command[4] = index;
+  return AMEBAZ_COMMAND_VALID;
+}
+
+int hci_get_efuse_iqk_data(uint8_t *data)
+{
+  data[0] = 0x0c;
+  uint8_t *iqk_data = data + 1;
+  memcpy(iqk_data, hci_phy_efuse, data[0]);
+  return 0;
+}
+
+static void hci_read_efuse(void)
+{
+  uint16_t bt_phy_efuse_base = 0x100;
+  device_mutex_lock(RT_DEV_LOCK_EFUSE);
+
+  /* Read Phy Efuse */
+
+  for (int i = 0; i < 16; i++)
+    {
+      hal_efuse_read(bt_phy_efuse_base + i, hci_phy_efuse + i,
+                     LDO_OUT_DEFAULT_VOLT);
+    }
+
+  hal_efuse_read(0xf8, hci_phy_efuse + 16, LDO_OUT_DEFAULT_VOLT);
+  hal_efuse_read(0xf9, hci_phy_efuse + 17, LDO_OUT_DEFAULT_VOLT);
+
+  /* Read Logic Efuse */
+
+  ameba_efuse_logical_read(BT_LGC_EFUSE_OFFSET, BT_LGC_EFUSE_LEN,
+                           hci_lgc_efuse);
+
+  device_mutex_unlock(RT_DEV_LOCK_EFUSE);
+}
+
+static int hci_parse_config(void)
+{
+  uint32_t signature;
+  uint16_t payload_len;
+  uint16_t entry_offset;
+  uint16_t entry_len;
+  uint8_t *p_entry;
+  uint8_t *p;
+  uint8_t *p_len;
+  uint8_t i;
+  uint16_t tx_flatk;
+  p = rtl_vendor_init_config;
+  p_len = rtl_vendor_init_config + 4;
+  LE_STREAM_TO_UINT32(signature, p);
+  LE_STREAM_TO_UINT16(payload_len, p);
+  if (signature != BT_CONFIG_SIGNATURE)
+    {
+      /* Invalid Signature */
+
+      return -EIO;
+    }
+
+  if (payload_len != sizeof(rtl_vendor_init_config) - BT_CONFIG_HEADER_LEN)
+    {
+      /* Fix the len, just avoid the length is not corect */
+
+      LE_UINT16_TO_STREAM(p_len,
+                    sizeof(rtl_vendor_init_config) - BT_CONFIG_HEADER_LEN);
+    }
+
+  p_entry = rtl_vendor_init_config + BT_CONFIG_HEADER_LEN;
+  while (p_entry < rtl_vendor_init_config + sizeof(rtl_vendor_init_config))
+    {
+      p = p_entry;
+      LE_STREAM_TO_UINT16(entry_offset, p);
+      LE_STREAM_TO_UINT8(entry_len, p);
+      p_entry = p + entry_len;
+      switch (entry_offset)
+        {
+        case 0x000c:
+
+          /* FIXME: MP (If use mp, Set badurate 115200
+           * in rtl_vendor_init_config)
+           */
+
+          LE_STREAM_TO_UINT32(hci_cfg_baudrate, p);
+          break;
+        case 0x0018:
+
+          /* FIXME: MP (If use mp, Clear flowctl in rtl_vendor_init_config) */
+
+          break;
+        case 0x0030:
+
+          /* FIXME: Customer use Wi-Fi MAC - 1 as BT ADDR,
+           * so ignore action here
+           */
+
+#if 0
+          if (entry_len == 6)
+            {
+              if ((hci_lgc_efuse[0] != 0xff) && (hci_lgc_efuse[1] != 0xff))
+                {
+                  for (uint8_t i = 0 ; i < 6; i++)
+                    {
+                      p[i] = hci_lgc_efuse[5 - i];
+                    }
+                }
+            }
+
+#endif
+          break;
+        case 0x194:
+          if (hci_lgc_efuse[LEFUSE(0x196)] == 0xff)
+            {
+              if (!(hci_phy_efuse[2] & BIT0))
+                {
+                  tx_flatk = hci_phy_efuse[0xa] | hci_phy_efuse[0xb] << 8;
+                  bt_flatk_8710c(tx_flatk);
+                }
+
+              break;
+            }
+
+          else
+            {
+              p[0] = hci_lgc_efuse[LEFUSE(0x196)];
+              if (hci_lgc_efuse[LEFUSE(0x196)] & BIT1)
+                {
+                  p[1] = hci_lgc_efuse[LEFUSE(0x197)];
+                }
+
+              if (hci_lgc_efuse[LEFUSE(0x196)] & BIT2)
+                {
+                  p[2] = hci_lgc_efuse[LEFUSE(0x198)];
+                  p[3] = hci_lgc_efuse[LEFUSE(0x199)];
+                  tx_flatk = hci_lgc_efuse[LEFUSE(0x198)]
+                             | hci_lgc_efuse[LEFUSE(0x199)] << 8;
+                  bt_flatk_8710c(tx_flatk);
+                }
+
+              else
+                {
+                  if (!(hci_phy_efuse[2] & BIT0))
+                    {
+                      tx_flatk = hci_phy_efuse[0xa]
+                                 | hci_phy_efuse[0xb] << 8;
+                      bt_flatk_8710c(tx_flatk);
+                    }
+                }
+
+              if (hci_lgc_efuse[LEFUSE(0x196)] & BIT5)
+                {
+                  p[4] = hci_lgc_efuse[LEFUSE(0x19a)];
+                  p[5] = hci_lgc_efuse[LEFUSE(0x19b)];
+                }
+            }
+
+          break;
+        case 0x19f:
+          for (i = 0; i < entry_len; i ++)
+            {
+              if (hci_lgc_efuse[LEFUSE(0x19c + i)] != 0xff)
+                {
+                  p[i] = hci_lgc_efuse[LEFUSE(0x19c + i)];
+                }
+            }
+
+          break;
+        case 0x1a4:
+          for (i = 0; i < entry_len; i ++)
+            {
+              if (hci_lgc_efuse[LEFUSE(0x1a2 + i)] != 0xff)
+                {
+                  p[i] = hci_lgc_efuse[LEFUSE(0x1a2 + i)];
+                }
+            }
+
+          break;
+        default:
+          break;
+        }
+    }
+
+  return 0;
+}
+
+int hci_board_init(void)
+{
+  /* FIXME: Wi-Fi Coexist, MP, Trace_Setting */
+
+  hci_read_efuse();
+  if (!CHECK_SW(EFUSE_SW_BT_FW_LOG))
+    {
+      set_reg_val(0x400000cc, BIT2 | BIT1 | BIT0, 6);
+      rtw_msleep_os(5);
+      set_reg_val(0x400000cc, BIT8, 1);
+      rtw_msleep_os(5);
+    }
+
+  if (hci_parse_config())
+    {
+      return -EIO;
+    }
+
+  return 0;
+}
+
+int hci_board_init_done(void)
+{
+  /* FIXME: MP */
+
+  return 0;
+}
+

arch/arm/src/rtl8720c/amebaz_hci_board.h

@@ -0,0 +1,57 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_hci_board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_AMEBA_HCI_BOARD_H
+#define __INCLUDE_AMEBA_HCI_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define HCI_START_IQK
+#define AMEBAZ_COMMAND_FRAGMENT_SIZE    (252)
+#define AMEBAZ_COMMAND_DONE             (0)
+#define AMEBAZ_COMMAND_VALID            (1)
+#define BT_DEFAUT_LMP_SUBVER            0x8710
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+int hci_check_iqk(void);
+int hci_start_iqk(void);
+int hci_set_init_config_mac(FAR uint8_t *addr, uint8_t diffvalue);
+int hci_get_baudrate(FAR uint32_t *bt_baudrate,
+                         FAR uint32_t *uart_baudrate);
+int hci_find_fw_patch(uint8_t chipid);
+int hci_get_efuse_iqk_data(uint8_t *data);
+int hci_board_init(void);
+int hci_board_init_done(void);
+
+#endif /* __INCLUDE_AMEBA_FLASH_H */
+

arch/arm/src/rtl8720c/amebaz_netdev.c

@@ -0,0 +1,432 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_netdev.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <string.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/net/arp.h>
+#include <nuttx/kmalloc.h>
+#include "amebaz_netdev.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define WDDELAY   (1 * CLK_TCK / 2)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+static void amebaz_poll_work(FAR void *arg);
+static void amebaz_netdev_notify_tx_done(FAR struct amebaz_dev_s *priv)
+{
+  work_queue(LPWORK, &priv->pollwork, amebaz_poll_work, priv, 0);
+}
+
+static int amebaz_txpoll(FAR struct net_driver_s *dev)
+{
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private;
+  if (priv->dev.d_len > 0)
+    {
+#ifdef CONFIG_NET_IPv4
+#ifdef CONFIG_NET_IPv6
+      if (IFF_IS_IPv4(priv->dev.d_flags))
+#endif
+        {
+          arp_out(&priv->dev);
+        }
+
+#endif /* CONFIG_NET_IPv4 */
+#ifdef CONFIG_NET_IPv6
+#ifdef CONFIG_NET_IPv4
+      else
+#endif
+        {
+          neighbor_out(&priv->dev);
+        }
+
+#endif /* CONFIG_NET_IPv6 */
+      if (!devif_loopback(&priv->dev))
+        {
+          net_lock();
+          if (!priv->curr)
+            {
+              net_unlock();
+              amebaz_netdev_notify_tx_done(priv);
+              return false;
+            }
+
+          DEBUGASSERT(priv->curr->tail == priv->dev.d_buf);
+          skb_put(priv->curr, priv->dev.d_len);
+          rltk_wlan_send_skb(priv->devnum, priv->curr);
+          priv->dev.d_buf = NULL;
+          priv->curr = NULL;
+          net_unlock();
+          NETDEV_TXPACKETS(&priv->dev);
+          amebaz_netdev_notify_tx_done(priv);
+          return true;
+        }
+    }
+
+  return false;
+}
+
+static int amebaz_transmit(FAR struct amebaz_dev_s *priv)
+{
+  struct sk_buff *skb;
+  skb = rltk_wlan_alloc_skb(priv->dev.d_len);
+  if (!skb)
+    {
+      NETDEV_TXERRORS(&priv->dev);
+      return -ENOMEM;
+    }
+
+  NETDEV_TXPACKETS(&priv->dev);
+  memcpy(skb->tail, priv->dev.d_buf, priv->dev.d_len);
+  skb_put(skb, priv->dev.d_len);
+  rltk_wlan_send_skb(priv->devnum, skb);
+  NETDEV_TXDONE(&priv->dev);
+  return OK;
+}
+
+static void amebaz_reply(FAR struct amebaz_dev_s *priv)
+{
+  if (priv->dev.d_len > 0)
+    {
+#ifdef CONFIG_NET_IPv6
+      if (IFF_IS_IPv4(priv->dev.d_flags))
+#endif
+        {
+          arp_out(&priv->dev);
+        }
+
+#ifdef CONFIG_NET_IPv6
+      else
+        {
+          neighbor_out(&priv->dev);
+        }
+
+#endif
+      amebaz_transmit(priv);
+    }
+}
+
+void amebaz_netdev_notify_receive(FAR struct amebaz_dev_s *priv,
+                                  int index, unsigned int len)
+{
+  FAR struct net_driver_s *dev = &priv->dev;
+  FAR struct eth_hdr_s *hdr;
+  FAR struct sk_buff *skb;
+  FAR void *oldbuf;
+  skb = rltk_wlan_get_recv_skb(index);
+  if (skb == NULL)
+    {
+      return;
+    }
+
+  if (!IFF_IS_UP(dev->d_flags))
+    {
+      skb_pull(skb, len);
+      return;
+    }
+
+  NETDEV_RXPACKETS(&priv->dev);
+  net_lock();
+  oldbuf = priv->dev.d_buf;
+  hdr = (struct eth_hdr_s *)skb->data;
+  priv->dev.d_buf = (void *)skb->data;
+  priv->dev.d_len = len;
+#ifdef CONFIG_NET_PKT
+  pkt_input(&priv->dev);
+#endif
+  if (hdr->type == HTONS(TPID_8021QVLAN))
+    {
+      uint8_t temp_buffer[12];
+      memcpy(temp_buffer, skb->data, 12);
+      memcpy(skb->data + 4, temp_buffer, 12);
+      priv->dev.d_buf = skb->data = skb->data + 4;
+      priv->dev.d_len -= 4;
+    }
+
+#ifdef CONFIG_NET_IPv4
+  if (hdr->type == HTONS(ETHTYPE_IP))
+    {
+      NETDEV_RXIPV4(&priv->dev);
+      arp_ipin(&priv->dev);
+      ipv4_input(&priv->dev);
+      amebaz_reply(priv);
+    }
+
+  else
+    {
+#endif
+#ifdef CONFIG_NET_IPv6
+      if (hdr->type == HTONS(ETHTYPE_IP6))
+        {
+          NETDEV_RXIPV6(&priv->dev);
+          ipv6_input(&priv->dev);
+          amebaz_reply(priv);
+        }
+
+      else
+        {
+#endif
+#ifdef CONFIG_NET_ARP
+          if (hdr->type == htons(ETHTYPE_ARP))
+            {
+              arp_arpin(&priv->dev);
+              NETDEV_RXARP(&priv->dev);
+              if (priv->dev.d_len > 0)
+                {
+                  amebaz_transmit(priv);
+                }
+            }
+
+          else
+#endif
+            {
+              NETDEV_RXDROPPED(&priv->dev);
+            }
+#ifdef CONFIG_NET_IPv6
+        }
+#endif
+#ifdef CONFIG_NET_IPv4
+    }
+#endif
+
+  skb_pull(skb, len);
+  priv->dev.d_buf = oldbuf;
+  net_unlock();
+}
+
+static void amebaz_poll_expiry(wdparm_t arg)
+{
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)arg;
+  work_queue(LPWORK, &priv->pollwork, amebaz_poll_work, priv, 0);
+}
+
+static void amebaz_txavail_work(FAR void *arg)
+{
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)arg;
+  FAR struct net_driver_s *dev = &priv->dev;
+  net_lock();
+  if (IFF_IS_UP(dev->d_flags))
+    {
+      if (!priv->curr && rltk_wlan_check_isup(priv->devnum))
+        {
+          priv->curr = rltk_wlan_alloc_skb(MAX_NETDEV_PKTSIZE);
+          if (priv->curr)
+            {
+              priv->dev.d_buf = priv->curr->tail;
+              priv->dev.d_len = 0;
+            }
+        }
+
+      if (priv->dev.d_buf)
+        {
+          devif_timer(&priv->dev, 0, amebaz_txpoll);
+        }
+    }
+
+  net_unlock();
+}
+
+static void amebaz_poll_work(FAR void *arg)
+{
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)arg;
+  FAR struct net_driver_s *dev = &priv->dev;
+  net_lock();
+  if (IFF_IS_UP(dev->d_flags))
+    {
+      if (!priv->curr && rltk_wlan_check_isup(priv->devnum))
+        {
+          priv->curr = rltk_wlan_alloc_skb(MAX_NETDEV_PKTSIZE);
+          if (priv->curr)
+            {
+              priv->dev.d_buf = priv->curr->tail;
+              priv->dev.d_len = 0;
+            }
+        }
+
+      if (priv->dev.d_buf)
+        {
+          devif_timer(&priv->dev, WDDELAY, amebaz_txpoll);
+        }
+    }
+
+  wd_start(&priv->txpoll, WDDELAY, amebaz_poll_expiry, (wdparm_t)priv);
+  net_unlock();
+}
+
+static int amebaz_txavail(FAR struct net_driver_s *dev)
+{
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private;
+  if (work_available(&priv->pollwork))
+    {
+      work_queue(LPWORK, &priv->pollwork, amebaz_txavail_work, priv, 0);
+    }
+
+  return OK;
+}
+
+int amebaz_ioctl(FAR struct net_driver_s *dev, int cmd,
+                 unsigned long arg)
+{
+  FAR struct amebaz_dev_s *priv = (struct amebaz_dev_s *)dev->d_private;
+  int ret;
+  if (!IFF_IS_UP(dev->d_flags) ||
+      (!rltk_wlan_running(priv->devnum) && cmd != SIOCSIWMODE))
+    {
+      return -EINVAL;
+    }
+
+  switch (cmd)
+    {
+    case SIOCSIWSCAN:
+      ret = amebaz_wl_start_scan(priv, (void *)arg);
+      break;
+    case SIOCGIWSCAN:
+      ret = amebaz_wl_get_scan_results(priv, (void *)arg);
+      break;
+    case SIOCSIWENCODEEXT:
+      ret = amebaz_wl_set_encode_ext(priv, (void *)arg);
+      break;
+    case SIOCGIWENCODEEXT:
+      ret = amebaz_wl_get_encode_ext(priv, (void *)arg);
+      break;
+    case SIOCSIWESSID:
+      ret = amebaz_wl_set_ssid(priv, (void *)arg);
+      break;
+    case SIOCSIWAP:
+      ret = amebaz_wl_set_bssid(priv, (void *)arg);
+      break;
+    case SIOCSIWMODE:
+      ret = amebaz_wl_set_mode(priv, (void *)arg);
+      break;
+    case SIOCSIWCOUNTRY:
+      ret = amebaz_wl_set_country(priv, (void *)arg);
+      break;
+    case SIOCGIWFREQ:
+      ret = amebaz_wl_get_freq(priv, (void *)arg);
+      break;
+    case SIOCSIWFREQ:
+      ret = amebaz_wl_set_freq(priv, (void *)arg);
+      break;
+    case SIOCGIWAP:
+    case SIOCGIWMODE:
+    case SIOCGIWESSID:
+    case SIOCGIWSENS:
+    case SIOCSIWAUTH:
+    case SIOCGIWAUTH:
+    case SIOCSIFHWADDR:
+    case SIOCGIFHWADDR:
+    case SIOCSIWRATE:
+    case SIOCGIWRATE:
+    case SIOCSIWTXPOW:
+    case SIOCGIWTXPOW:
+      ret = amebaz_wl_process_command(priv, cmd, (void *)arg);
+      break;
+    default:
+      wlwarn("ERROR: Unrecognized IOCTL command: %d\n", cmd);
+      ret = -ENOTTY;  /* Special return value for this case */
+      break;
+    }
+
+  return ret;
+}
+
+static int amebaz_ifup(FAR struct net_driver_s *dev)
+{
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private;
+  if (!IFF_IS_UP(dev->d_flags))
+    {
+      priv->mode = RTW_MODE_NONE;
+      priv->conn.status = AMEBAZ_STATUS_DISABLED;
+      wd_start(&priv->txpoll, WDDELAY, amebaz_poll_expiry, (wdparm_t)dev);
+    }
+
+  return OK;
+}
+
+static int amebaz_ifdown(FAR struct net_driver_s *dev)
+{
+  int ret = 0;
+  FAR struct amebaz_dev_s *priv = (FAR struct amebaz_dev_s *)dev->d_private;
+  irqstate_t flags;
+  if (priv->devnum == 0 && rltk_wlan_running(1))
+    {
+      printf("must ifdown wlan 1 first\r\n");
+      return ERROR;
+    }
+
+  flags = enter_critical_section();
+  if (IFF_IS_UP(dev->d_flags))
+    {
+      if (priv->curr)
+        {
+          skb_put(priv->curr, 0);
+          rltk_wlan_send_skb(priv->devnum, priv->curr);
+
+          priv->curr = NULL;
+        }
+
+      wd_cancel(&priv->txpoll);
+      if (priv->devnum == 0)
+        {
+          rltk_wlan_deinit();
+        }
+
+      else if (priv->mode == RTW_MODE_STA_AP)
+        {
+          ret = rltk_set_mode_prehandle(RTW_MODE_STA_AP,
+                                        RTW_MODE_STA, "wlan0");
+          rtw_msleep_os(50);
+          ret = rltk_set_mode_posthandle(RTW_MODE_STA_AP,
+                                         RTW_MODE_STA, "wlan0");
+          while (rltk_wlan_running(1))
+            {
+              rtw_msleep_os(50);
+            }
+        }
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+int amebaz_netdev_register(FAR struct amebaz_dev_s *priv)
+{
+  struct net_driver_s *dev = &priv->dev;
+  dev->d_ifup    = amebaz_ifup;
+  dev->d_ifdown  = amebaz_ifdown;
+  dev->d_txavail = amebaz_txavail;
+#ifdef CONFIG_NETDEV_IOCTL
+  dev->d_ioctl   = amebaz_ioctl;
+#endif
+  dev->d_private = priv;
+  return netdev_register(dev, NET_LL_IEEE80211);
+}
+

arch/arm/src/rtl8720c/amebaz_netdev.h

@@ -0,0 +1,39 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_netdev.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_NETDEV_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_NETDEV_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "amebaz_driver.h"
+#include "amebaz_wlan.h"
+
+int   amebaz_netdev_register(FAR struct amebaz_dev_s *priv);
+void  amebaz_netdev_notify_receive(FAR struct amebaz_dev_s *priv,
+                                           int index, unsigned int len);
+#endif /* __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_NETDEV_H */

arch/arm/src/rtl8720c/amebaz_wlan.c

@@ -0,0 +1,124 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_wlan.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <string.h>
+#include <syslog.h>
+#include "amebaz_netdev.h"
+
+enum _WIFI_EVENT_INDICATE
+{
+  WIFI_EVENT_CONNECT                = 0,
+  WIFI_EVENT_DISCONNECT             = 1,
+  WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
+  WIFI_EVENT_SCAN_RESULT_REPORT     = 3,
+  WIFI_EVENT_SCAN_DONE              = 4,
+  WIFI_EVENT_RECONNECTION_FAIL      = 5,
+  WIFI_EVENT_SEND_ACTION_DONE       = 6,
+  WIFI_EVENT_RX_MGNT                = 7,
+  WIFI_EVENT_STA_ASSOC              = 8,
+  WIFI_EVENT_STA_DISASSOC           = 9,
+  WIFI_EVENT_STA_WPS_START          = 10,
+  WIFI_EVENT_WPS_FINISH             = 11,
+  WIFI_EVENT_EAPOL_START            = 12,
+  WIFI_EVENT_EAPOL_RECVD            = 13,
+  WIFI_EVENT_NO_NETWORK             = 14,
+  WIFI_EVENT_BEACON_AFTER_DHCP      = 15,
+  WIFI_EVENT_IP_CHANGED             = 16,
+  WIFI_EVENT_ICV_ERROR              = 17,
+  WIFI_EVENT_CHALLENGE_FAIL         = 18,
+  WIFI_EVENT_STA_START              = 19,
+  WIFI_EVENT_STA_STOP               = 20,
+  WIFI_EVENT_AP_START               = 21,
+  WIFI_EVENT_AP_STOP                = 22,
+  WIFI_EVENT_STA_GOT_IP             = 23,
+  WIFI_EVENT_STA_LOST_IP            = 24,
+  WIFI_EVENT_MAX,
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void wifi_set_country_code(void)
+{
+  /* wifi_set_country(RTW_COUNTRY_US); */
+}
+
+void wifi_indication(unsigned long event, char *buf, int buf_len, int flags)
+{
+  if (event != WIFI_EVENT_BEACON_AFTER_DHCP)
+    {
+      syslog(1, "%s: %d, event: %x\n", __func__, __LINE__, event);
+    }
+}
+
+void wext_wlan_indicate(unsigned int cmd, union iwreq_data *wrqu,
+                        char *extra)
+{
+  int index = 0;
+  if (cmd == IWEVCUSTOM)
+    {
+      amebaz_wl_connection_handler(index, wrqu, extra);
+    }
+
+  else if (cmd == SIOCGIWAP)
+    {
+      amebaz_wl_connection_handler(index, wrqu, extra);
+    }
+
+  else if (cmd == SIOCGIWSCAN)
+    {
+      amebaz_wl_scan_handler(index, wrqu, extra);
+    }
+
+  else
+    {
+      syslog(1, "%s: %d, event: %x\n", __func__, __LINE__, cmd);
+    }
+}
+
+void netif_post_sleep_processing(void)
+{
+}
+
+int netif_is_valid_ip(int index, unsigned char *ip_dest)
+{
+  return true;
+}
+
+unsigned char *rltk_wlan_get_ip(int index)
+{
+  return NULL;
+}
+
+void netif_rx(int index, unsigned int len)
+{
+  amebaz_wl_notify_rx_handler(index, len);
+}
+
+void rltk_wlan_set_netif_info(int index, void *dev, unsigned char *addr)
+{
+  amebaz_wl_netif_info_handler(index, dev, addr);
+}
+

arch/arm/src/rtl8720c/amebaz_wlan.h

@@ -0,0 +1,416 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/amebaz_wlan.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_WLAN_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_WLAN_H
+#define WEP_ENABLED             0x0001
+#define TKIP_ENABLED            0x0002
+#define AES_ENABLED             0x0004
+#define WSEC_SWFLAG             0x0008
+#define AES_CMAC_ENABLED        0x0010
+#define SHARED_ENABLED          0x00008000
+#define WPA_SECURITY            0x00200000
+#define WPA2_SECURITY           0x00400000
+#define WPS_ENABLED             0x10000000
+#define PSCAN_ENABLE            0x01 /* enable for partial channel scan */
+#define PSCAN_FAST_SURVEY       0x02 /* set to select scan time to FAST_SURVEY_TO, otherwise SURVEY_TO */
+#define PSCAN_SIMPLE_CONFIG     0x04 /* set to select scan time to FAST_SURVEY_TO and resend probe request */
+
+enum
+{
+  /* CHANNEL PLAN */
+
+  RTW_COUNTRY_WORLD1,  /* 0x20 */
+  RTW_COUNTRY_ETSI1,   /* 0x21 */
+  RTW_COUNTRY_FCC1,    /* 0x22 */
+  RTW_COUNTRY_MKK1,    /* 0x23 */
+  RTW_COUNTRY_ETSI2,   /* 0x24 */
+  RTW_COUNTRY_FCC2,    /* 0x2a */
+  RTW_COUNTRY_WORLD2,  /* 0x47 */
+  RTW_COUNTRY_MKK2,    /* 0x58 */
+  RTW_COUNTRY_GLOBAL,  /* 0x41 */
+
+  /* SPECIAL */
+
+  RTW_COUNTRY_WORLD, /* WORLD1 */
+  RTW_COUNTRY_EU,    /* ETSI1 */
+
+  /* JAPANESE */
+
+  RTW_COUNTRY_JP, /* MKK1 */
+
+  /* FCC , 19 countries */
+
+  RTW_COUNTRY_AS, /* FCC2 */
+  RTW_COUNTRY_BM,
+  RTW_COUNTRY_CA,
+  RTW_COUNTRY_DM,
+  RTW_COUNTRY_DO,
+  RTW_COUNTRY_FM,
+  RTW_COUNTRY_GD,
+  RTW_COUNTRY_GT,
+  RTW_COUNTRY_GU,
+  RTW_COUNTRY_HT,
+  RTW_COUNTRY_MH,
+  RTW_COUNTRY_MP,
+  RTW_COUNTRY_NI,
+  RTW_COUNTRY_PA,
+  RTW_COUNTRY_PR,
+  RTW_COUNTRY_PW,
+  RTW_COUNTRY_TW,
+  RTW_COUNTRY_US,
+  RTW_COUNTRY_VI,
+
+  /* others,  ETSI */
+
+  RTW_COUNTRY_AD, /* ETSI1 */
+  RTW_COUNTRY_AE,
+  RTW_COUNTRY_AF,
+  RTW_COUNTRY_AI,
+  RTW_COUNTRY_AL,
+  RTW_COUNTRY_AM,
+  RTW_COUNTRY_AN,
+  RTW_COUNTRY_AR,
+  RTW_COUNTRY_AT,
+  RTW_COUNTRY_AU,
+  RTW_COUNTRY_AW,
+  RTW_COUNTRY_AZ,
+  RTW_COUNTRY_BA,
+  RTW_COUNTRY_BB,
+  RTW_COUNTRY_BD,
+  RTW_COUNTRY_BE,
+  RTW_COUNTRY_BF,
+  RTW_COUNTRY_BG,
+  RTW_COUNTRY_BH,
+  RTW_COUNTRY_BL,
+  RTW_COUNTRY_BN,
+  RTW_COUNTRY_BO,
+  RTW_COUNTRY_BR,
+  RTW_COUNTRY_BS,
+  RTW_COUNTRY_BT,
+  RTW_COUNTRY_BY,
+  RTW_COUNTRY_BZ,
+  RTW_COUNTRY_CF,
+  RTW_COUNTRY_CH,
+  RTW_COUNTRY_CI,
+  RTW_COUNTRY_CL,
+  RTW_COUNTRY_CN,
+  RTW_COUNTRY_CO,
+  RTW_COUNTRY_CR,
+  RTW_COUNTRY_CX,
+  RTW_COUNTRY_CY,
+  RTW_COUNTRY_CZ,
+  RTW_COUNTRY_DE,
+  RTW_COUNTRY_DK,
+  RTW_COUNTRY_DZ,
+  RTW_COUNTRY_EC,
+  RTW_COUNTRY_EE,
+  RTW_COUNTRY_EG,
+  RTW_COUNTRY_ES,
+  RTW_COUNTRY_ET,
+  RTW_COUNTRY_FI,
+  RTW_COUNTRY_FR,
+  RTW_COUNTRY_GB,
+  RTW_COUNTRY_GE,
+  RTW_COUNTRY_GF,
+  RTW_COUNTRY_GH,
+  RTW_COUNTRY_GL,
+  RTW_COUNTRY_GP,
+  RTW_COUNTRY_GR,
+  RTW_COUNTRY_GY,
+  RTW_COUNTRY_HK,
+  RTW_COUNTRY_HN,
+  RTW_COUNTRY_HR,
+  RTW_COUNTRY_HU,
+  RTW_COUNTRY_ID,
+  RTW_COUNTRY_IE,
+  RTW_COUNTRY_IL,
+  RTW_COUNTRY_IN,
+  RTW_COUNTRY_IQ,
+  RTW_COUNTRY_IR,
+  RTW_COUNTRY_IS,
+  RTW_COUNTRY_IT,
+  RTW_COUNTRY_JM,
+  RTW_COUNTRY_JO,
+  RTW_COUNTRY_KE,
+  RTW_COUNTRY_KH,
+  RTW_COUNTRY_KN,
+  RTW_COUNTRY_KP,
+  RTW_COUNTRY_KR,
+  RTW_COUNTRY_KW,
+  RTW_COUNTRY_KY,
+  RTW_COUNTRY_KZ,
+  RTW_COUNTRY_LA,
+  RTW_COUNTRY_LB,
+  RTW_COUNTRY_LC,
+  RTW_COUNTRY_LI,
+  RTW_COUNTRY_LK,
+  RTW_COUNTRY_LR,
+  RTW_COUNTRY_LS,
+  RTW_COUNTRY_LT,
+  RTW_COUNTRY_LU,
+  RTW_COUNTRY_LV,
+  RTW_COUNTRY_MA,
+  RTW_COUNTRY_MC,
+  RTW_COUNTRY_MD,
+  RTW_COUNTRY_ME,
+  RTW_COUNTRY_MF,
+  RTW_COUNTRY_MK,
+  RTW_COUNTRY_MN,
+  RTW_COUNTRY_MO,
+  RTW_COUNTRY_MQ,
+  RTW_COUNTRY_MR,
+  RTW_COUNTRY_MT,
+  RTW_COUNTRY_MU,
+  RTW_COUNTRY_MV,
+  RTW_COUNTRY_MW,
+  RTW_COUNTRY_MX,
+  RTW_COUNTRY_MY,
+  RTW_COUNTRY_NG,
+  RTW_COUNTRY_NL,
+  RTW_COUNTRY_NO,
+  RTW_COUNTRY_NP,
+  RTW_COUNTRY_NZ,
+  RTW_COUNTRY_OM,
+  RTW_COUNTRY_PE,
+  RTW_COUNTRY_PF,
+  RTW_COUNTRY_PG,
+  RTW_COUNTRY_PH,
+  RTW_COUNTRY_PK,
+  RTW_COUNTRY_PL,
+  RTW_COUNTRY_PM,
+  RTW_COUNTRY_PT,
+  RTW_COUNTRY_PY,
+  RTW_COUNTRY_QA,
+  RTW_COUNTRY_RS,
+  RTW_COUNTRY_RU,
+  RTW_COUNTRY_RW,
+  RTW_COUNTRY_SA,
+  RTW_COUNTRY_SE,
+  RTW_COUNTRY_SG,
+  RTW_COUNTRY_SI,
+  RTW_COUNTRY_SK,
+  RTW_COUNTRY_SN,
+  RTW_COUNTRY_SR,
+  RTW_COUNTRY_SV,
+  RTW_COUNTRY_SY,
+  RTW_COUNTRY_TC,
+  RTW_COUNTRY_TD,
+  RTW_COUNTRY_TG,
+  RTW_COUNTRY_TH,
+  RTW_COUNTRY_TN,
+  RTW_COUNTRY_TR,
+  RTW_COUNTRY_TT,
+  RTW_COUNTRY_TZ,
+  RTW_COUNTRY_UA,
+  RTW_COUNTRY_UG,
+  RTW_COUNTRY_UY,
+  RTW_COUNTRY_UZ,
+  RTW_COUNTRY_VC,
+  RTW_COUNTRY_VE,
+  RTW_COUNTRY_VN,
+  RTW_COUNTRY_VU,
+  RTW_COUNTRY_WF,
+  RTW_COUNTRY_WS,
+  RTW_COUNTRY_YE,
+  RTW_COUNTRY_YT,
+  RTW_COUNTRY_ZA,
+  RTW_COUNTRY_ZW,
+  RTW_COUNTRY_MAX
+};
+
+enum
+{
+  RTW_BSS_TYPE_INFRASTRUCTURE = 0, /* *< Denotes infrastructure network */
+  RTW_BSS_TYPE_ADHOC          = 1, /* *< Denotes an 802.11 ad-hoc IBSS network */
+  RTW_BSS_TYPE_ANY            = 2, /* *< Denotes either infrastructure or ad-hoc network */
+  RTW_BSS_TYPE_UNKNOWN        = -1 /* *< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */
+};
+
+enum
+{
+  RTW_SECURITY_OPEN           = 0,                                              /* *< Open security */
+  RTW_SECURITY_WEP_PSK        = WEP_ENABLED,                                    /* *< WEP Security with open authentication */
+  RTW_SECURITY_WEP_SHARED     = (WEP_ENABLED | SHARED_ENABLED),                 /* *< WEP Security with shared authentication */
+  RTW_SECURITY_WPA_TKIP_PSK   = (WPA_SECURITY  | TKIP_ENABLED),                 /* *< WPA Security with TKIP */
+  RTW_SECURITY_WPA_AES_PSK    = (WPA_SECURITY  | AES_ENABLED),                  /* *< WPA Security with AES */
+  RTW_SECURITY_WPA2_AES_PSK   = (WPA2_SECURITY | AES_ENABLED),                  /* *< WPA2 Security with AES */
+  RTW_SECURITY_WPA2_TKIP_PSK  = (WPA2_SECURITY | TKIP_ENABLED),                 /* *< WPA2 Security with TKIP */
+  RTW_SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED),   /* *< WPA2 Security with AES & TKIP */
+  RTW_SECURITY_WPA_WPA2_MIXED = (WPA_SECURITY  | WPA2_SECURITY),                /* *< WPA/WPA2 Security */
+  RTW_SECURITY_WPA2_AES_CMAC  = (WPA2_SECURITY | AES_CMAC_ENABLED),             /* *< WPA2 Security with AES and Management Frame Protection */
+  RTW_SECURITY_WPS_OPEN       = WPS_ENABLED,                                    /* *< WPS with open security */
+  RTW_SECURITY_WPS_SECURE     = (WPS_ENABLED | AES_ENABLED),                    /* *< WPS with AES security */
+  RTW_SECURITY_UNKNOWN        = -1,                                             /* *< May be returned by scan function if security is unknown. Do not pass this to the join function! */
+  RTW_SECURITY_FORCE_32_BIT   = 0x7fffffff                                      /* *< Exists only to force rtw_security_t type to 32 bits */
+};
+
+enum
+{
+  RTW_WPS_TYPE_DEFAULT              = 0x0000,
+  RTW_WPS_TYPE_USER_SPECIFIED       = 0x0001,
+  RTW_WPS_TYPE_MACHINE_SPECIFIED    = 0x0002,
+  RTW_WPS_TYPE_REKEY                = 0x0003,
+  RTW_WPS_TYPE_PUSHBUTTON           = 0x0004,
+  RTW_WPS_TYPE_REGISTRAR_SPECIFIED  = 0x0005,
+  RTW_WPS_TYPE_NONE                 = 0x0006,
+  RTW_WPS_TYPE_WSC                  = 0x0007
+};
+
+enum
+{
+  RTW_802_11_BAND_5GHZ              = 0, /* *< Denotes 5GHz radio band */
+  RTW_802_11_BAND_2_4GHZ            = 1  /* *< Denotes 2.4GHz radio band */
+};
+
+begin_packed_struct struct rtw_ssid
+{
+  unsigned char                 len;     /* *< SSID length */
+  unsigned char                 val[33]; /* *< SSID name (AP name) */
+} end_packed_struct;
+
+begin_packed_struct struct rtw_mac
+{
+  unsigned char                 octet[6]; /* *< Unique 6-byte MAC address */
+} end_packed_struct;
+
+typedef unsigned long             rtw_bss_type_t;
+typedef unsigned long             rtw_security_t;
+typedef unsigned long             rtw_wps_type_t;
+typedef unsigned long             rtw_802_11_band_t;
+typedef struct rtw_ssid           rtw_ssid_t;
+typedef struct rtw_mac            rtw_mac_t;
+typedef struct rtw_scan_result    rtw_scan_result_t;
+typedef struct rtw_network_info   rtw_network_info_t;
+typedef struct rtw_scan_ap_result rtw_scan_ap_result_t;
+
+begin_packed_struct struct rtw_network_info
+{
+  rtw_ssid_t              ssid;
+  rtw_mac_t               bssid;
+  rtw_security_t          security_type;
+  unsigned char          *password;
+  int password_len;
+  int key_id;
+} end_packed_struct;
+
+begin_packed_struct struct rtw_scan_result
+{
+  rtw_ssid_t        SSID;             /* *< Service Set Identification (i.e. Name of Access Point) */
+  rtw_mac_t         BSSID;            /* *< Basic Service Set Identification (i.e. MAC address of Access Point) */
+  signed short      signal_strength;  /* *< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */
+  rtw_bss_type_t    bss_type;         /* *< Network type */
+  rtw_security_t    security;         /* *< Security type */
+  rtw_wps_type_t    wps_type;         /* *< WPS type */
+  unsigned int      channel;          /* *< Radio channel that the AP beacon was received on */
+  rtw_802_11_band_t band;             /* *< Radio band */
+} end_packed_struct;
+
+begin_packed_struct struct rtw_scan_ap_result
+{
+  char                    len;
+  uint8_t                 BSSID[IFHWADDRLEN];
+  int                     signal_strength;
+  char                    security;
+  char                    wps_type;
+  char                    channel;
+  char                    SSID[0];
+} end_packed_struct;
+
+enum
+{
+  RTW_MODE_NONE = 0,
+  RTW_MODE_STA,
+  RTW_MODE_AP,
+  RTW_MODE_STA_AP,
+  RTW_MODE_PROMISC,
+  RTW_MODE_P2P
+};
+
+struct sk_buff_head
+{
+  struct list_head    *next;
+  struct list_head    *prev;
+  unsigned int        qlen;
+};
+
+struct sk_buff
+{
+  struct sk_buff      *next;
+  struct sk_buff      *prev;
+  struct sk_buff_head *list;
+  unsigned char       *head;
+  unsigned char       *data;
+  unsigned char       *tail;
+  unsigned char       *end;
+  void                *dev;
+  unsigned int        len;
+  int                 dyalloc_flag;
+};
+
+unsigned char  *skb_put(struct sk_buff *skb,
+                          unsigned int len);
+unsigned char  *skb_pull(struct sk_buff *skb,
+                           unsigned int len);
+int             rltk_wlan_init(int index, unsigned long mode);
+void            rltk_wlan_deinit(void);
+void            rltk_wlan_deinit_fastly(void);
+int             rltk_wlan_start(int index);
+void            rltk_wlan_statistic(unsigned char index);
+unsigned char   rltk_wlan_running(unsigned char index);
+int             rltk_wlan_control(unsigned long cmd, void *data);
+int             rltk_wlan_handshake_done(void);
+int             rltk_wlan_rf_on(void);
+int             rltk_wlan_rf_off(void);
+int             rltk_wlan_check_bus(void);
+int             rltk_wlan_wireless_mode(unsigned char mode);
+int             rltk_wlan_get_wireless_mode(unsigned char *pmode);
+int             rltk_wlan_set_wps_phase(unsigned char is_trigger_wps);
+int             rtw_ps_enable(int enable);
+int             rltk_wlan_is_connected_to_ap(void);
+int             rltk_set_mode_prehandle(unsigned char curr_mode,
+                                               unsigned char next_mode,
+                                               const char *ifname);
+int             rltk_set_mode_posthandle(unsigned char curr_mode,
+                                                unsigned char next_mode,
+                                                const char *ifname);
+int             rltk_remove_softap_in_concurrent_mode(const char *ifname);
+unsigned char   rltk_wlan_check_isup(int index);
+void            rltk_wlan_tx_inc(int index);
+void            rltk_wlan_tx_dec(int index);
+struct sk_buff *rltk_wlan_get_recv_skb(int index);
+struct sk_buff *rltk_wlan_alloc_skb(unsigned int len);
+void            rltk_wlan_set_netif_info(int index_wlan, void *dev,
+                                                unsigned char *addr);
+void            rltk_wlan_send_skb(int index, struct sk_buff *skb);
+unsigned char  *rltk_wlan_get_ip(int index);
+int             netif_is_valid_ip(int index, unsigned char *ip_dest);
+unsigned char  *netif_get_hwaddr(int index);
+void            netif_rx(int index, unsigned int len);
+void            netif_post_sleep_processing(void);
+void            netif_pre_sleep_processing(void);
+
+#endif /* __DRIVERS_WIRELESS_IEEE80211_AMEBAZ_AMEBAZ_WLAN_H */
+

arch/arm/src/rtl8720c/chip.h

@@ -0,0 +1,48 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_AMEBA_CHIP_H
+#define __ARCH_ARM_SRC_AMEBA_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#  include <sys/types.h>
+#endif
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef ARRAY_SIZE
+#  define ARRAY_SIZE(x)               (sizeof(x) / sizeof((x)[0]))
+#endif
+/* If the common ARMv7-M vector handling logic is used,
+ * then it expects the following
+ * definition in this file that provides the number of
+ * supported external interrupts.
+ */
+#define ARMV8M_PERIPHERAL_INTERRUPTS  (CONFIG_AMEBA_NR_IRQS - 16)
+
+#endif /* __ARCH_ARM_SRC_AMEBA_CHIP_H */

arch/arm/src/rtl8720c/include/chip.h

@@ -0,0 +1,20 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/include/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+

arch/arm/src/rtl8720c/include/irq.h

@@ -0,0 +1,118 @@
+/****************************************************************************
+ * arch/arm/src/rtl8720c/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_SONG_IRQ_H
+#define __ARCH_ARM_INCLUDE_SONG_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Exception/interrupt vector numbers */
+
+/* Vector  0: Reset stack pointer value */
+
+/* Vector  1: Reset */
+
+#define NVIC_IRQ_NMI               (2)    /* Vector  2: Non-Maskable Interrupt (NMI) */
+
+#define NVIC_IRQ_HARDFAULT         (3)    /* Vector  3: Hard fault */
+
+#define NVIC_IRQ_MEMFAULT          (4)    /* Vector  4: Memory management (MPU) */
+
+#define NVIC_IRQ_BUSFAULT          (5)    /* Vector  5: Bus fault */
+
+#define NVIC_IRQ_USAGEFAULT        (6)    /* Vector  6: Usage fault */
+
+/* Vectors 7-10: Reserved */
+
+#define NVIC_IRQ_SVCALL            (11)   /* Vector 11: SVC call */
+
+#define NVIC_IRQ_DBGMONITOR        (12)   /* Vector 12: Debug Monitor */
+
+/* Vector 13: Reserved */
+
+#define NVIC_IRQ_PENDSV            (14)   /* Vector 14: Pendable system service request */
+
+#define NVIC_IRQ_SYSTICK           (15)   /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16). These definitions are chip-specific */
+
+#define NVIC_IRQ_FIRST             (16)   /* Vector number of the first interrupt */
+
+#define NVIC_IRQ_WLAN              (28)   /* Vector 28: Wireless Lan */
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the INTC.  This does, however, waste several
+ * words of memory in the IRQ to handle mapping tables.
+ */
+
+#define NR_IRQS                    CONFIG_AMEBA_NR_IRQS
+
+/* NVIC priority levels */
+
+#define NVIC_SYSH_PRIORITY_MIN     0xff /* All bits set in minimum priority */
+
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x40 /* Midpoint is the default */
+
+#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+
+#define NVIC_SYSH_PRIORITY_STEP    0x40 /* Three bits priority used, bits[7-6] as group */
+
+#define NVIC_SYSH_PRIORITY_SUBSTEP 0x20 /* Three bits priority used, bit[5] as sub */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_INCLUDE_SONG_IRQ_H */
+