From 1924a960646c78e9f79e47636f2aa4d2d2585962 Mon Sep 17 00:00:00 2001 From: Chengdong Wang Date: Sat, 27 Jun 2026 23:31:33 +0800 Subject: [PATCH] arch/riscv: Add CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI for fence.i The fence.i instruction is only available when the Zifencei extension (CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI) is supported by the hardware. This commit adds a macro wrapper around fence.i usages to prevent compilation errors on toolchains or targets where the Zifencei extension is absent. Signed-off-by: Chengdong Wang --- arch/risc-v/include/barriers.h | 6 +++++- arch/risc-v/src/common/riscv_fpu.S | 3 ++- arch/risc-v/src/common/riscv_mmu.h | 2 ++ arch/risc-v/src/common/riscv_vpu.S | 3 ++- arch/risc-v/src/mpfs/mpfs_head.S | 2 ++ 5 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/risc-v/include/barriers.h b/arch/risc-v/include/barriers.h index fa6a8d75f32..742ddf86463 100644 --- a/arch/risc-v/include/barriers.h +++ b/arch/risc-v/include/barriers.h @@ -39,6 +39,10 @@ /* UP_ISB() is used to synchronize the instruction and data streams */ -#define UP_ISB() __asm__ __volatile__ ("fence.i" ::: "memory") +#ifdef CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI +# define UP_ISB() __asm__ __volatile__ ("fence.i" ::: "memory") +#else +# define UP_ISB() +#endif #endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */ diff --git a/arch/risc-v/src/common/riscv_fpu.S b/arch/risc-v/src/common/riscv_fpu.S index aaeb42e68f3..586c3b28f7c 100644 --- a/arch/risc-v/src/common/riscv_fpu.S +++ b/arch/risc-v/src/common/riscv_fpu.S @@ -72,8 +72,9 @@ riscv_fpuconfig: csrs CSR_STATUS, a0 fscsr zero - +#ifdef CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI fence.i +#endif ret /**************************************************************************** diff --git a/arch/risc-v/src/common/riscv_mmu.h b/arch/risc-v/src/common/riscv_mmu.h index a7c0b486994..4cb029fb0cf 100644 --- a/arch/risc-v/src/common/riscv_mmu.h +++ b/arch/risc-v/src/common/riscv_mmu.h @@ -224,7 +224,9 @@ static inline void mmu_write_satp(uintptr_t reg) "csrw satp, %0\n" "sfence.vma x0, x0\n" "fence rw, rw\n" +#ifdef CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI "fence.i\n" +#endif : : "rK" (reg) : "memory" diff --git a/arch/risc-v/src/common/riscv_vpu.S b/arch/risc-v/src/common/riscv_vpu.S index bb4369f978c..7cc2e693f32 100644 --- a/arch/risc-v/src/common/riscv_vpu.S +++ b/arch/risc-v/src/common/riscv_vpu.S @@ -70,8 +70,9 @@ riscv_vpuconfig: li a0, MSTATUS_VS_INIT csrs CSR_STATUS, a0 - +#ifdef CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI fence.i +#endif ret /**************************************************************************** diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S index 5b0e049cf38..a3f666fa80c 100644 --- a/arch/risc-v/src/mpfs/mpfs_head.S +++ b/arch/risc-v/src/mpfs/mpfs_head.S @@ -172,7 +172,9 @@ __start: csrw CSR_MIE, a2 /* Set MSIE bit to receive IPI */ /* flush the instruction cache */ +#ifdef CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI fence.i +#endif .wait_boot: wfi