From 17cc0b9bfe207e64c6df3922510785eac01adb8d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 25 Apr 2018 14:54:14 -0600 Subject: [PATCH] arch/arm/src/imxrt: Minor reparitioning to account for the fact that the GPIO5 base address is not contiguous with the GPIO1-4 base addresses. --- arch/arm/src/imxrt/chip/imxrt105x_memorymap.h | 1 - arch/arm/src/imxrt/chip/imxrt_gpio.h | 12 ++----- arch/arm/src/imxrt/imxrt_gpio.c | 32 +++++++++++++++++++ arch/arm/src/imxrt/imxrt_gpio.h | 27 +++++++++++++--- configs/stm32f4discovery/README.txt | 21 ++++++------ 5 files changed, 69 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h b/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h index 2b6278a3c23..b6201eb819e 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h +++ b/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h @@ -145,7 +145,6 @@ #define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ #define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ /* 0x401b4000 16KB Reserved */ -#define IMXRT_GPIO_BASE(n) (0x401b8000 + ((n) << 14)) #define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ #define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ #define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ diff --git a/arch/arm/src/imxrt/chip/imxrt_gpio.h b/arch/arm/src/imxrt/chip/imxrt_gpio.h index 3dd363c20a3..910e278be54 100644 --- a/arch/arm/src/imxrt/chip/imxrt_gpio.h +++ b/arch/arm/src/imxrt/chip/imxrt_gpio.h @@ -51,8 +51,9 @@ #define GPIO2 1 /* Port 2 index */ #define GPIO3 2 /* Port 3 index */ #define GPIO4 3 /* Port 4 index */ +#define GPIO5 4 /* Port 5 index */ -#define IMXRT_GPIO_NPORTS 4 /* Four total ports */ +#define IMXRT_GPIO_NPORTS 5 /* Five total ports */ #define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */ /* Register offsets *************************************************************************/ @@ -68,15 +69,6 @@ /* Register addresses ***********************************************************************/ -#define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO_PSR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO_ICR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO_ICR2(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET) - #define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) #define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) #define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index fe9b78b4bab..e0213a115a8 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -223,9 +223,33 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio2_padmux, /* GPIO2 */ g_gpio3_padmux, /* GPIO3 */ g_gpio4_padmux, /* GPIO4 */ + NULL, /* GPIO5 REVISIT */ NULL /* End of list */ }; +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */ + +uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = +{ + IMXRT_GPIO1_BASE +#if IMXRT_GPIO_NPORTS > 1 + , IMXRT_GPIO2_BASE +#endif +#if IMXRT_GPIO_NPORTS > 2 + , IMXRT_GPIO3_BASE +#endif +#if IMXRT_GPIO_NPORTS > 3 + , IMXRT_GPIO4_BASE +#endif +#if IMXRT_GPIO_NPORTS > 4 + , IMXRT_GPIO5_BASE +#endif +}; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -300,6 +324,8 @@ static int imxrt_gpio_configinput(gpio_pinset_t pinset) uintptr_t regaddr; unsigned int index; + DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS); + /* Configure pin as in input */ imxrt_gpio_dirin(port, pin); @@ -344,6 +370,8 @@ static inline int imxrt_gpio_configoutput(gpio_pinset_t pinset) int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS); + /* Set the output value */ imxrt_gpio_setoutput(port, pin, value); @@ -483,6 +511,8 @@ void imxrt_gpio_write(gpio_pinset_t pinset, bool value) int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS); + flags = enter_critical_section(); imxrt_gpio_setoutput(port, pin, value); leave_critical_section(flags); @@ -503,6 +533,8 @@ bool imxrt_gpio_read(gpio_pinset_t pinset) int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; bool value; + DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS); + flags = enter_critical_section(); value = imxrt_gpio_getinput(port, pin); leave_critical_section(flags); diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index e6a736f32b5..95651d423d4 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -50,6 +50,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + /* 32-bit Encoding: * * ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM @@ -86,10 +87,11 @@ #define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */ #define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) -# define GPIO_PORT1 (0 << GPIO_PORT_SHIFT) /* GPIO1 */ -# define GPIO_PORT2 (1 << GPIO_PORT_SHIFT) /* GPIO2 */ -# define GPIO_PORT3 (2 << GPIO_PORT_SHIFT) /* GPIO3 */ -# define GPIO_PORT4 (3 << GPIO_PORT_SHIFT) /* GPIO4 */ +# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */ +# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */ +# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */ +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO4 */ /* GPIO Pin Number: * @@ -179,6 +181,19 @@ #define GPIO_IOMUX_SHIFT (0) /* Bits 9-15: IOMUX pin configuration */ #define GPIO_IOMUX_MASK (0xffff << GPIO_IOMUX_SHIFT) +/* Helper addressing macros */ + +#define IMXRT_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIO5 macros as indices */ + +#define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO_PSR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO_ICR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO_ICR2(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET) + /************************************************************************************ * Public Types ************************************************************************************/ @@ -200,6 +215,10 @@ extern "C" #define EXTERN extern #endif +/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */ + +EXTERN uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS]; + /************************************************************************************ * Public Function Prototypes ************************************************************************************/ diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt index 536c9c74a6d..2b8c96efe47 100644 --- a/configs/stm32f4discovery/README.txt +++ b/configs/stm32f4discovery/README.txt @@ -1367,15 +1367,18 @@ Configuration Sub-directories that the part supports auto baudrate detection, but I have found no documentation on how to use that. - Currently only a fixed, configurable BAUD is used and this must - be set to the BT860 default. + Currently the "generic" HCI UART upper half is used with the BT860 + and that upper half driver supports only a fixed (but configurable + BAUD) is used and this must be set to the BT860 default (115200). - Baud rate can be set with vendor-specific command. Ideally, the - sequence would be: (1) start at default baud rate, (2) get local - version info, (3) send the vendor-specific baud rate change command, - (4) wait for response, and (5) set local UART to higher baud rate. + A custom BT860 upper half driver is needed that can use vendor + specific command: Baud rate can be set with such a vendor-specific + command. Ideally, the sequence would be: (1) start at default baud + rate, (2) get local version info, (3) send the vendor-specific baud + rate change command, (4) wait for response, and (5) set the local + UART to the matching, higher baud rate. - The custom, vendor-specific command is + The custom, vendor-specific BT860 command is: {0x18, 0xfc, 0x06, 0x00, 0x00, NN, NN, NN, NN} @@ -1401,8 +1404,8 @@ Configuration Sub-directories This is another version of the NuttShell configuration for the STM32F4-Discovery with the STM32F4DIS-BB base board. It is very similar to the netnsh configuration except that it has IPv6 enabled and IPv4 - disabled. Several network utilities that are not yet available under - IPv6 are disabled. + disabled. Several network utilities that are not yet available when + IPv6 is disabled. NOTES: