diff --git a/arch/arm/src/imxrt/hardware/imxrt_usbphy.h b/arch/arm/src/imxrt/hardware/imxrt_usbphy.h
index ea6d4ef932d..e3b1590585f 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_usbphy.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_usbphy.h
@@ -119,7 +119,7 @@
 #define USBPHY_CTRL_ENHOSTDISCONDET   (1 << 1)   /* Bit 1:  Enable HighSpeed disconnect detector */
 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ  (1 << 0)   /* Bit 0:  Enable OTG_ID_CHG_IRQ */
 
-/* USB PHY PLL Control/Status Register (PLL_SIC, only in IMXRT117X) */
+/* USB PHY PLL Control/Status Register (PLL_SIC, IMXRT117x and IMXRT118x) */
 #define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT   (2)        /* Bits 2-5: PLL_POSTDIV */
 #define USBPHY_PLL_SIC_PLL_POSTDIV_MASK    (0x7 << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)
 #define USBPHY_PLL_SIC_PLL_POSTDIV(n)      (((n) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
@@ -130,7 +130,7 @@
 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL     (1 << 19)  /* Bit 19: REFBIAS_PWD_SEL */
 #define USBPHY_PLL_SIC_REFBIAS_PWD         (1 << 20)  /* Bit 20: Power down the reference bias */
 #define USBPHY_PLL_SIC_PLL_REG_ENABLE      (1 << 21)  /* Bit 21: PLL_REG_ENABLE */
-#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT   (22)       /* Bits 22-25: PLL_DIV_SEL */
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT   (22)       /* Bits 22-24: PLL_DIV_SEL */
 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK    (0x7 << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)
 #define USBPHY_PLL_SIC_PLL_DIV_SEL(n)      (((n) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
 #define USBPHY_PLL_SIC_PLL_LOCK            (1 << 31)  /* Bit 31: PLL_LOCK */
diff --git a/arch/arm/src/imxrt/imxrt_usbdev.c b/arch/arm/src/imxrt/imxrt_usbdev.c
index 117cd5adf89..8036239077c 100644
--- a/arch/arm/src/imxrt/imxrt_usbdev.c
+++ b/arch/arm/src/imxrt/imxrt_usbdev.c
@@ -2997,10 +2997,15 @@ void arm_usbinitialize(void)
   imxrt_clockall_usboh3();
 
 #if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || defined(CONFIG_ARCH_FAMILY_IMXRT118x)
-  up_mdelay(1);
+  putreg32(USBPHY_CTRL_SFTRST,
+           IMXRT_USBPHY_CTRL_CLR(0));
 
-  putreg32(USBPHY_PLL_SIC_PLL_POWER |
-           USBPHY_PLL_SIC_PLL_REG_ENABLE,
+  putreg32(USBPHY_PLL_SIC_PLL_REG_ENABLE,
+           IMXRT_USBPHY_PLL_SIC_SET(0));
+
+  up_udelay(15);
+
+  putreg32(USBPHY_PLL_SIC_PLL_POWER,
            IMXRT_USBPHY_PLL_SIC_SET(0));
 
   putreg32(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK,