Merged in masayuki2009/nuttx.nuttx/fe310_with_pll (pull request #1094)

fe310 with pll

* arch: fe310: Introduce CONFIG_ARCH_CHIP_FE310_QEMU

* boards: hifive1-revb: Introduce CONFIG_ARCH_CHIP_FE310_QEMU

* arch: fe310: Add support for PLL

* boards: hifive1-revb: Increase uart0 tx buff size and add getprime app

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Masayuki Ishikawa 2019-12-11 12:01:53 +00:00 • committed by Gregory Nutt
parent 813902cf87
commit 0eb9bfa49d
16 changed files with 486 additions and 44 deletions

View file

@ -10,19 +10,20 @@
$ make
$ sudo make install
3. Modify flash origin address
3. Modify defconfig
index 559c1813b8..a67c37b576 100644
--- a/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
+++ b/boards/risc-v/fe310/hifive1-revb/scripts/ld.script
@@ -35,7 +35,7 @@
MEMORY
{
- flash (rx) : ORIGIN = 0x20010000, LENGTH = 4096K
+ flash (rx) : ORIGIN = 0x20400000, LENGTH = 4096K
sram (rwx) : ORIGIN = 0x80000000, LENGTH = 16K
}
index c449421741..5a76600785 100644
--- a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig
+++ b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig
@@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="hifive1-revb"
CONFIG_ARCH_BOARD_HIFIVE1_REVB=y
CONFIG_ARCH_CHIP="fe310"
CONFIG_ARCH_CHIP_FE310=y
-CONFIG_ARCH_CHIP_FE310_G002=y
+CONFIG_ARCH_CHIP_FE310_QEMU=y
CONFIG_ARCH_INTERRUPTSTACK=1536
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
4. Configure and build NuttX

View file

@ -31,6 +31,5 @@
5. TODO
Configure PLL
Support GPIO/SPI/I2C/RTC/WDT/PWM
Support RISC-V User mode

View file

@ -65,8 +65,10 @@ CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=12
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_GETPRIME_STACKSIZE=2048
CONFIG_UART0_RXBUFSIZE=8
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_UART0_TXBUFSIZE=4
CONFIG_UART0_TXBUFSIZE=32
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0

View file

@ -37,7 +37,11 @@ include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/risc-v/src/rv32im/Toolchain.defs
LDSCRIPT = ld.script
ifeq ($(CONFIG_ARCH_CHIP_FE310_QEMU),y)
LDSCRIPT = ld-qemu.script
else
LDSCRIPT = ld.script
endif
ifeq ($(WINTOOL),y)
# Windows-native toolchains

View file

@ -0,0 +1,118 @@
/****************************************************************************
* boards/risc-v/fe310/hifive1-revb/scripts/ld-qemu.script
*
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
MEMORY
{
flash (rx) : ORIGIN = 0x20400000, LENGTH = 4096K
sram (rwx) : ORIGIN = 0x80000000, LENGTH = 16K
}
OUTPUT_ARCH("riscv")
ENTRY(_stext)
EXTERN(_vectors)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : ALIGN(4) {
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : ALIGN(4) {
*(.ARM.extab*)
} > flash
.ARM.exidx : ALIGN(4) {
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > flash
_eronly = ABSOLUTE(.);
.data : ALIGN(4) {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.sdata .sdata.*)
*(.gnu.linkonce.d.*)
*(.gnu.linkonce.s.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : ALIGN(4) {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.sbss .sbss.*)
*(.gnu.linkonce.b.*)
*(.gnu.linkonce.sb.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}