From 0e09d162e24ade4d6f604c8c092e8092e31c3d95 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 21 Apr 2020 21:37:47 +0200 Subject: [PATCH] arch/arm/src/stm32/stm32_adc.c: fix injected channels configuration for ADC IPv1 --- arch/arm/src/stm32/stm32_adc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index f4ecc4eac00..02fa5e88783 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -3798,8 +3798,22 @@ static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) for (i = 0 ; i < priv->cj_channels; i += 1) { +#if defined(HAVE_IP_ADC_V1) + /* Injected channels sequence for for ADC IPv1: + * + * 1 2 3 4 + * IL=1: JSQR4, + * IL=2: JSQR3, JSQR4 + * IL=3: JSQR2, JSQR3, JSQR4 + * IL=4: JSQR1, JSQR2, JSQR3, JSQR4 + */ + + setbits |= (priv->j_chanlist[priv->cj_channels - 1 - i] << + (ADC_JSQR_JSQ4_SHIFT - ADC_JSQR_JSQ_SHIFT * i)); +#else setbits |= priv->j_chanlist[i] << (ADC_JSQR_JSQ1_SHIFT + - ADC_JSQR_JSQ_SHIFT * i); + ADC_JSQR_JSQ_SHIFT * i); +#endif } /* Write register */