Merged nuttx/nuttx into neilh20/anuttx/master

2026-09-07 09:26:38 +00:00 · 2016-07-24 10:57:27 -07:00 · 2016-07-24 10:57:27 -07:00 · 0d6be8e022
commit 0d6be8e022
parent f3fb492f68 88cb41a0dc
400 changed files with 10130 additions and 2388 deletions
--- a/80
+++ b/80
@ -12295,3 +12295,83 @@
 	  Matthias Renner (2016-07-08).
 	* drivers/pipe: Add missing configuration for pipe ring buffer size.
 	  From Frank Benkert (2016-07-08).
+	* STM32L4: Fix incorrect clock setup for LPTIM1.  From ziggurat29
+	  (2016-07-08).
+	* nucleo-l476rg and stm32lf76vg-disco: Define timer clock frequencies on
+	  STM32L4-based boards.  From ziggurat29 (2016-07-08).
+	* STM32L4: Add support for tickless OS, and incidentally timers, pwm,
+	  oneshot, free-running....  From ziggurat29 (2016-07-08).
+	* SAM3/4 I2C: Fix reversed logic in twi_startmessage().  From Wolfgang
+	  Reissnegger (2016-07-09).
+	* VFS ioctl().  Per comments from David Sidrane, file_ioctl() should not
+	  return succeed if the ioctl method is not supported.  It probably
+	  should return ENOTTY in that case (2016-07-09).
+	* libm: This change should significantly improve the performance of
+	  single precision floating point math library functions. The vast
+	  majority of changes have to do with preventing the compiler from
+	  needlessly promoting floats to doubles, performing the calculation
+	  with doubles, only to demote the result to float. These changes only
+	  affect the math lib functions that return float. From David Alessio
+	  (2016-07-11).
+	* STM32F4 Discovery: Add FPU support for ostest for the STM32F4Discovery
+	  platform. From David Alessio (2016-07-11).
+	* Build system:  Remove the includes/apps link to apps/include.  It is
+	  no longer used.  From Sebastien Lorquet (2016-07-11).
+	* printf(): If there are no streams, let printf() fall back to use
+	  syslog() for output (2016-07-11).
+	* Qemu-i486: Fix qemu-i486/ostest/Make.defs test for M32.  From Heath
+	  Petersen (2016-07-12).
+	* UART 16550: Handle when CONFIG_SERIAL_UART_ARCH_IOCTL is not enabled.
+	  From Heath Petersen (2016-07-12).
+	* Kinetis Ethernet:  Add support for the KSZ8081 PHY (2016-07-12).
+	* SST26 Driver: Before accessing the sst26 flash, the "Global Unlock"
+	  command must me executed, which I do in the sst26 driver.  BUT re-
+	  reading the datasheet, the WREN instruction is required to enable the
+	  execution of this command. This was not done. I have no idea how the
+	  driver currently works except by chance. The writes should never
+	  happen at all, the flash is half-enabled!  From Sebastien Lorquet
+	  (2016-07-12).
+	* Freedom K64F: Add a networking NSH configuration. (2016-07-12).
+	* N25Qxx Driver: Alter the notion of 'blocksize' to be equivalent to
+	  'flash write page size' in order to align with assumptions in the
+	  smartfs driver (at least, maybe other things do as well).  Correct a
+	  bug that was previously masked by having blocksize=eraseblocksize
+	  which would cause buffer overflows and delicious hardfaults.  Trivial
+	  spelling changes in comments, etc.  From ziggurat29 (2016-07-12).
+	* STM32L476 Discovery: Update stm32l476 disco to include init code for
+	  smartfs and nxffs for cases where those fs are included in build.
+	  From ziggurat29 (2016-07-12).
+	* Kinetis Ethernet and Freedom-K64F:  Freedcom-K64F PHY address was
+	  wrong.  Modified Ethernet driver to try all PHY addresses and then
+	  only fail if the driver cannot find a usable PHY address.  MDIO pin
+	  must have an internal pull-up on the Freedom-K64F (2016-07-12).
+	* Kinetis Ethernet:  Add support for CONFIG_NET_NOINTS (2016-07-12).
+	* SmartFS: Fix a 32-byte memory leak.  From Ken Pettit (2016-07-12).
+	* Freedom-K64F: SDHC is now enabled in the nsh configuration (but does
+	  not work)Add hooks for automounter; Change NSH configuration to use
+	  Windows (2016-07-13).
+	* SAMV7 USBHS Device:  This change solves a problem which causes data
+	  loss while sending data via USB. This problem is caused by an incorrect
+	  handling of the endpoint state in the USB driver sam_usbdevhs.  This
+	  leads under some circumstances to situations in which an DMA transfer
+	  is setup while a previous DMA transfer is currently active. Amongst
+	  other things I introduced the new endpoint state USBHS_EPSTATE_SENDING_DMA
+	  for the fix.  To reproduce the problem, I used a program which send as
+	  many data as possible via a CDC/ACM device and verified the received
+	  data on the PC.  From Stefan Kolb (2016-07-13).
+	* STM32: Fix bug in oneshot timer.  From Max Neklyudov (2016-07-13).
+	* STM32L4: Port foward bugfix from stm32 of oneshot timer.  From
+	  ziggurat29 (2016-07-13).
+	* STM32 and EFM32: I'm using syslog through ITM. In this case
+	  syslog_channel function is call before RAM initialisation in
+	  stm32_clockconfig. But syslog channel uses a global variable that is
+	  reset to default by the RAM initialization.  From Pierre-noel
+	  Bouteville (2016-07-14).
+	* LPC43xx SPIFI: If CONFIG_SPIFI_SECTOR512 undefined, lpc43_bwrite
+	  doesn't do actual write (probably copy/paste errors). Still not sure
+	  about current state of lpc43_spifi implementation, but for me NXFFS
+	  works with this patch.  From Vytautas Lukenskas (2016-07-14).
+	* SMART MTD layer: Fixes freesector logic error when sectorsPerBlk=256,
+	  adds DEBUGASSERT for invalid geometry and additional memory debug
+	  logic.  Also fixes the dangling pointer on error bug.  From Ken
+	  Pettit (2016-07-14).
--- a/Documentation/NuttShell.html
+++ b/Documentation/NuttShell.html
@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
-      <p>Last Updated: February 8, 2016</p>
+      <p>Last Updated: July 20, 2016</p>
    </td>
  </tr>
 </table>
@ -3277,7 +3277,7 @@ nsh&gt;
  </tr>
  <tr>
    <td><b><code>mkfifo</code></b></td>
-    <td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0</td>
+    <td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0 &amp;&amp; <code>CONFIG_PIPES</code></td>
    <td><code>CONFIG_NSH_DISABLE_MKFIFO</code></td>
  </tr>
  <tr>
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@ -4439,7 +4439,7 @@ void board_autoled_off(int led);
 </p>
 <ul>
  <li><b>Interface Definition</b>.
-    The header file for the NuttX PWM driver reside at <code>include/nuttx/pwm.h</code>.
+    The header file for the NuttX PWM driver reside at <code>include/nuttx/drivers/pwm.h</code>.
    This header file includes both the application level interface to the PWM driver as well as the interface between the &quot;upper half&quot; and &quot;lower half&quot; drivers.
    The PWM module uses a standard character driver framework.
    However, since the PWM driver is a devices control interface and not a data transfer interface,
@ -4472,7 +4472,7 @@ void board_autoled_off(int led);
 </p>
 <ul>
  <li><b>Interface Definition</b>.
-    The header file for the NuttX CAN driver reside at <code>include/nuttx/can.h</code>.
+    The header file for the NuttX CAN driver resides at <code>include/nuttx/drivers/can.h</code>.
    This header file includes both the application level interface to the CAN driver as well as the interface between the &quot;upper half&quot; and &quot;lower half&quot; drivers.
    The CAN module uses a standard character driver framework.
  </li>
--- a/8
+++ b/8
@ -339,10 +339,10 @@ config ARCH_MATH_H
 	default n
 	---help---
 		There is also a re-directing version of math.h in the source tree.
-		However, it resides out-of-the-way at include/nuttx/math.h because it
+		However, it resides out-of-the-way at include/nuttx/lib/math.h because it
 		conflicts too often with the system math.h. If ARCH_MATH_H=y is
 		defined, however, the top-level makefile will copy the redirecting
-		math.h header file from include/nuttx/math.h to include/math.h. math.h
+		math.h header file from include/nuttx/lib/math.h to include/math.h. math.h
 		will then include the architecture-specific version of math.h that you
 		must provide at nuttx/arch/>architecture</include/math.h.

@ -371,7 +371,7 @@ config ARCH_STDARG_H
 	default n
 	---help---
 		There is also a redirecting version of stdarg.h in the source tree
-		as well. It also resides out-of-the-way at include/nuttx/stdarg.h.
+		as well. It also resides out-of-the-way at include/nuttx/lib/stdarg.h.
 		This is because you should normally use your toolchain's stdarg.h
 		file. But sometimes, your toolchain's stdarg.h file may have other
 		header file dependencies and so may not be usable in the NuttX build
@ -379,7 +379,7 @@ config ARCH_STDARG_H
 		specific stdarg.h header file at nuttx/arch/<architecture>/include/stdarg.h

 		If ARCH_STDARG_H=y is defined, the top-level makefile will copy the
-		re-directing stdarg.h header file from include/nuttx/stdarg.h to
+		re-directing stdarg.h header file from include/nuttx/lib/stdarg.h to
 		include/stdarg.h. So for the architectures that cannot use their
 		toolchain's stdarg.h file, they can use this alternative by defining
 		ARCH_STDARG_H=y and providing. If ARCH_STDARG_H, is not defined, then
--- a/Makefile.unix
+++ b/Makefile.unix
@ -183,16 +183,16 @@ BIN = nuttx$(EXEEXT)
 all: $(BIN)
 .PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean

-# Target used to copy include/nuttx/math.h.  If CONFIG_ARCH_MATH_H is
+# Target used to copy include/nuttx/lib/math.h.  If CONFIG_ARCH_MATH_H is
 # defined, then there is an architecture specific math.h header file
 # that will be included indirectly from include/math.h.  But first, we
 # have to copy math.h from include/nuttx/. to include/.  Logic within
-# include/nuttx/math.h will hand the redirection to the architecture-
+# include/nuttx/lib/math.h will hand the redirection to the architecture-
 # specific math.h header file.
 #
 # If the CONFIG_LIBM is defined, the Rhombus libm will be built at libc/math.
 # Definitions and prototypes for the Rhombus libm are also contained in
-# include/nuttx/math.h and so the file must also be copied in that case.
+# include/nuttx/lib/math.h and so the file must also be copied in that case.
 #
 # If neither CONFIG_ARCH_MATH_H nor CONFIG_LIBM is defined, then no math.h
 # header file will be provided.  You would want that behavior if (1) you
@ -208,8 +208,8 @@ endif
 endif

 ifeq ($(NEED_MATH_H),y)
-include/math.h: include/nuttx/math.h
-	$(Q) cp -f include/nuttx/math.h include/math.h
+include/math.h: include/nuttx/lib/math.h
+	$(Q) cp -f include/nuttx/lib/math.h include/math.h
 else
 include/math.h:
 endif
@ -221,20 +221,20 @@ endif
 # the settings in this float.h are actually correct for your platform!

 ifeq ($(CONFIG_ARCH_FLOAT_H),y)
-include/float.h: include/nuttx/float.h
-	$(Q) cp -f include/nuttx/float.h include/float.h
+include/float.h: include/nuttx/lib/float.h
+	$(Q) cp -f include/nuttx/lib/float.h include/float.h
 else
 include/float.h:
 endif

-# Target used to copy include/nuttx/stdarg.h.  If CONFIG_ARCH_STDARG_H is
+# Target used to copy include/nuttx/lib/stdarg.h.  If CONFIG_ARCH_STDARG_H is
 # defined, then there is an architecture specific stdarg.h header file
-# that will be included indirectly from include/stdarg.h.  But first, we
+# that will be included indirectly from include/lib/stdarg.h.  But first, we
 # have to copy stdarg.h from include/nuttx/. to include/.

 ifeq ($(CONFIG_ARCH_STDARG_H),y)
-include/stdarg.h: include/nuttx/stdarg.h
-	$(Q) cp -f include/nuttx/stdarg.h include/stdarg.h
+include/stdarg.h: include/nuttx/lib/stdarg.h
+	$(Q) cp -f include/nuttx/lib/stdarg.h include/stdarg.h
 else
 include/stdarg.h:
 endif
--- a/README.txt
+++ b/README.txt
@ -321,13 +321,13 @@ Notes about Header Files

    If you have a custom, architecture specific math.h header file, then
    that header file should be placed at arch/<cpu>/include/math.h.  There
-    is a stub math.h header file located at include/nuttx/math.h.  This stub
+    is a stub math.h header file located at include/nuttx/lib/math.h.  This stub
    header file can be used to "redirect" the inclusion to an architecture-
    specific math.h header file.  If you add an architecture specific math.h
    header file then you should also define CONFIG_ARCH_MATH_H=y in your
    NuttX Configuration file.  If CONFIG_ARCH_MATH_H is selected, then the
    top-level Makefile will copy the stub math.h header file from
-    include/nuttx/math.h to include/math.h where it will become the system
+    include/nuttx/lib/math.h to include/math.h where it will become the system
    math.h header file.  The stub math.h header file does nothing other
    than to include that architecture-specific math.h header file as the
    system math.h header file.
--- a/12
+++ b/12
@ -1,4 +1,4 @@
-NuttX TODO List (Last updated July 3, 2016)
+NuttX TODO List (Last updated July 20, 2016)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

 This file summarizes known NuttX bugs, limitations, inconsistencies with
@ -447,6 +447,7 @@ o Kernel/Protected Build
               mkfatfs  mkfatfs
               mkrd     ramdisk_register()
               ping     icmp_ping()
+               mount    foreach_mountpoint()

               The busybox mkfatfs does not involve any OS calls; it does
               its job by simply opening the block driver (using open/xopen)
@ -1399,6 +1400,15 @@ o File system / Generic drivers (fs/, drivers/)
               socket structures.  There really should be one array that
               is a union of file and socket descriptors.  Then socket and
               file descriptors could lie in the same range.
+
+               Another example of how the current implementation limits
+               functionality:  I recently started an implement of the FILEMAX
+               (using pctl() instead sysctl()).  My objective was to be able
+               to control the number of available file descriptors on a task-
+               by-task basis.  The complexity due to the partitioning of
+               desciptor space in a range for file descriptors and a range
+               for socket descriptors made this feature nearly impossible to
+               implement.
  Status:      Open
  Priority:    Low

--- a/arch/arm/include/lpc17xx/lpc176x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc176x_irq.h
@ -147,7 +147,7 @@
 * 42
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 #  define LPC17_VALID_GPIOINT0  (0x7fff8ffful) /* GPIO port 0 interrupt set */
 #  define LPC17_VALID_GPIOINT2  (0x00003ffful) /* GPIO port 2 interrupt set */

--- a/arch/arm/include/lpc17xx/lpc178x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc178x_irq.h
@ -166,7 +166,7 @@
 * 42
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 #  define LPC17_VALID_GPIOINT0  (0xfffffffful) /* GPIO port 0 interrupt set */
 #  define LPC17_VALID_GPIOINT2  (0xfffffffful) /* GPIO port 2 interrupt set */

--- a/arch/arm/include/samdl/samd20_irq.h
+++ b/arch/arm/include/samdl/samd20_irq.h
@ -81,7 +81,7 @@

 /* GPIO interrupts.  Up to 16 pins may be configured to support interrupts */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
 #  define SAM_IRQ_EXTINT0  (SAM_IRQ_NIRQS+0)    /* External interrupt 0 */
 #  define SAM_IRQ_EXTINT1  (SAM_IRQ_NIRQS+1)    /* External interrupt 1 */
 #  define SAM_IRQ_EXTINT2  (SAM_IRQ_NIRQS+2)    /* External interrupt 2 */
--- a/arch/arm/include/samdl/samd21_irq.h
+++ b/arch/arm/include/samdl/samd21_irq.h
@ -88,7 +88,7 @@

 /* GPIO interrupts.  Up to 16 pins may be configured to support interrupts */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
 #  define SAM_IRQ_EXTINT0  (SAM_IRQ_NIRQS+0)    /* External interrupt 0 */
 #  define SAM_IRQ_EXTINT1  (SAM_IRQ_NIRQS+1)    /* External interrupt 1 */
 #  define SAM_IRQ_EXTINT2  (SAM_IRQ_NIRQS+2)    /* External interrupt 2 */
--- a/arch/arm/include/samdl/saml21_irq.h
+++ b/arch/arm/include/samdl/saml21_irq.h
@ -89,7 +89,7 @@

 /* GPIO interrupts.  Up to 16 pins may be configured to support interrupts */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
 #  define SAM_IRQ_EXTINT0  (SAM_IRQ_NIRQS+0)    /* External interrupt 0 */
 #  define SAM_IRQ_EXTINT1  (SAM_IRQ_NIRQS+1)    /* External interrupt 1 */
 #  define SAM_IRQ_EXTINT2  (SAM_IRQ_NIRQS+2)    /* External interrupt 2 */
--- a/arch/arm/src/armv7-r/arm_doirq.c
+++ b/arch/arm/src/armv7-r/arm_doirq.c
@ -52,22 +52,6 @@

 #include "group/group.h"

-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@ -44,14 +44,16 @@
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
 #include <nuttx/sched_note.h>
-#include <nuttx/fs/fs.h>
+#include <nuttx/drivers/drivers.h>
 #include <nuttx/fs/loop.h>
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
 #include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
 #include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>

 #include <arch/board/board.h>

@ -158,21 +160,21 @@ void up_initialize(void)

  up_irqinitialize();

+#ifdef CONFIG_PM
  /* Initialize the power management subsystem.  This MCU-specific function
   * must be called *very* early in the initialization sequence *before* any
   * other device drivers are initialized (since they may attempt to register
   * with the power management subsystem).
   */

-#ifdef CONFIG_PM
  up_pminitialize();
 #endif

+#ifdef CONFIG_ARCH_DMA
  /* Initialize the DMA subsystem if the weak function up_dmainitialize has been
   * brought into the build
   */

-#ifdef CONFIG_ARCH_DMA
 #ifdef CONFIG_HAVE_WEAKFUNCTIONS
  if (up_dmainitialize)
 #endif
@ -196,6 +198,14 @@ void up_initialize(void)
  devnull_register();   /* Standard /dev/null */
 #endif

+#if defined(CONFIG_DEV_RANDOM)
+  devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+  devurandom_register();   /* Standard /dev/urandom */
+#endif
+
 #if defined(CONFIG_DEV_ZERO)
  devzero_register();   /* Standard /dev/zero */
 #endif
@ -228,22 +238,10 @@ void up_initialize(void)
  ramlog_consoleinit();
 #endif

-  /* Initialize the HW crypto and /dev/crypto */
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+  /* Register the master pseudo-terminal multiplexor device */

-#if defined(CONFIG_CRYPTO)
-  up_cryptoinitialize();
-#endif
-
-#if CONFIG_NFILE_DESCRIPTORS > 0
-#if defined(CONFIG_CRYPTO_CRYPTODEV)
-  devcrypto_register();
-#endif
-#endif
-
-  /* Initialize the Random Number Generator (RNG)  */
-
-#ifdef CONFIG_DEV_RANDOM
-  up_rnginitialize();
+  (void)ptmx_register();
 #endif

  /* Early initialization of the system logging device.  Some SYSLOG channel
@ -253,6 +251,16 @@ void up_initialize(void)

  syslog_initialize(SYSLOG_INIT_EARLY);

+#if defined(CONFIG_CRYPTO)
+  /* Initialize the HW crypto and /dev/crypto */
+
+  up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+  devcrypto_register();
+#endif
+
 #ifndef CONFIG_NETDEV_LATEINIT
  /* Initialize the network */

--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@ -545,12 +545,6 @@ void up_usbuninitialize(void);
 # define up_usbuninitialize()
 #endif

-/* Random Number Generator (RNG) ********************************************/
-
-#ifdef CONFIG_DEV_RANDOM
-void up_rnginitialize(void);
-#endif
-
 /* Debug ********************************************************************/
 #ifdef CONFIG_STACK_COLORATION
 void up_stack_color(FAR void *stackbase, size_t nbytes);
--- a/arch/arm/src/efm32/efm32_clockconfig.c
+++ b/arch/arm/src/efm32/efm32_clockconfig.c
@ -909,9 +909,6 @@ static inline void efm32_itm_syslog(void)

  efm32_enable_auxhfrco();

-  /* Then perform ARMv7-M ITM SYSLOG initialization */
-
-  itm_syslog_initialize();
 }
 #else
 #  define efm32_itm_syslog()
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@ -93,10 +93,6 @@ volatile uint32_t *g_current_regs[1];

 extern uint32_t _vectors[];

-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
@ -261,15 +257,9 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
    {
      if (irq < NR_VECTORS)
        {
-          n = irq - EFM32_IRQ_INTERRUPTS;
+          n        = irq - EFM32_IRQ_INTERRUPTS;
          *regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
-          while (n >= 32)
-            {
-              n -= 32;
-            }
-
-          *bit     = 1 << n;
+          *bit     = (uint32_t)1 << (n & 0x1f);
        }
      else
        {
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@ -47,7 +47,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_arch.h"
--- a/arch/arm/src/efm32/efm32_pwm.h
+++ b/arch/arm/src/efm32/efm32_pwm.h
@ -39,7 +39,7 @@
 /* The EFM32 does not have dedicated PWM hardware.  Rather, pulsed output 
 * control is a capability of the EFM32 timers.  The logic in this file 
 * implements the lower half of the standard, NuttX PWM interface using the 
- * EFM32 timers. That interface is described in include/nuttx/pwm.h.
+ * EFM32 timers. That interface is described in include/nuttx/drivers/pwm.h.
 */

 /****************************************************************************
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@ -275,6 +275,12 @@ void __start(void)

  showprogress('C');

+#ifdef CONFIG_ARMV7M_ITMSYSLOG
+  /* Perform ARMv7-M ITM SYSLOG initialization */
+
+  itm_syslog_initialize();
+#endif
+
  /* Perform early serial initialization */

  up_earlyserialinit();
--- a/arch/arm/src/kinetis/Kconfig
+++ b/arch/arm/src/kinetis/Kconfig
@ -483,12 +483,12 @@ config KINETIS_FTM2_CHANNEL

 menu "Kinetis GPIO Interrupt Configuration"

-config GPIO_IRQ
+config KINETIS_GPIOIRQ
 	bool "GPIO pin interrupts"
 	---help---
 		Enable support for interrupting GPIO pins

-if GPIO_IRQ
+if KINETIS_GPIOIRQ

 config KINETIS_PORTAINTS
 	bool "GPIOA interrupts"
@ -615,13 +615,6 @@ config KINETIS_SD4BIT_FREQ
 		Frequency to use for transferring data to/from an SD card using all four data lines.

 endif
-
-config KINETIS_SDHC_DMAPRIO
-	int "SDHC DMA priority"
-	depends on SDIO_DMA
-	---help---
-		SDHC DMA priority
-
 endmenu # Kinetis SDHC Configuration

 menu "Kinetis UART Configuration"
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@ -103,7 +103,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += kinetis_userspace.c kinetis_mpuinit.c
 endif

-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_KINETIS_GPIOIRQ),y)
 CHIP_CSRCS += kinetis_pinirq.c
 endif

--- a/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
+++ b/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
@ -44,7 +44,7 @@

 #include "chip.h"

-#ifdef KINETIS_K64
+#ifdef KINETIS_K60

 /************************************************************************************
 * Pre-processor Definitions
@ -192,5 +192,5 @@
 * Public Functions
 ************************************************************************************/

-#endif /* KINETIS_K64 */
+#endif /* KINETIS_K60 */
 #endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H */
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@ -476,7 +476,7 @@ bool kinetis_gpioread(uint32_t pinset);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
 void kinetis_pinirqinitialize(void);
 #else
 #  define kinetis_pinirqinitialize()
@ -514,7 +514,7 @@ xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
 void kinetis_pinirqenable(uint32_t pinset);
 #else
 #  define kinetis_pinirqenable(pinset)
@ -528,7 +528,7 @@ void kinetis_pinirqenable(uint32_t pinset);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
 void kinetis_pinirqdisable(uint32_t pinset);
 #else
 #  define kinetis_pinirqdisable(pinset)
--- a/arch/arm/src/kinetis/kinetis_clockconfig.c
+++ b/arch/arm/src/kinetis/kinetis_clockconfig.c
@ -39,8 +39,6 @@

 #include <nuttx/config.h>

-#include <arch/board/board.h>
-
 #include "up_arch.h"

 #include "kinetis.h"
@ -50,6 +48,8 @@
 #include "chip/kinetis_llwu.h"
 #include "chip/kinetis_pinmux.h"

+#include <arch/board/board.h>
+
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@ -1840,7 +1840,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
          phydata = 0xffff;
          ret = kinetis_readmii(priv, phyaddr, MII_PHYID1, &phydata);
        }
-      while (ret >= 0 && phydata == 0xffff && ++retries < 3);
+      while ((ret < 0 || phydata == 0xffff) && ++retries < 3);

      /* If we successfully read anything then break out, using this PHY address */

--- a/arch/arm/src/kinetis/kinetis_irq.c
+++ b/arch/arm/src/kinetis/kinetis_irq.c
@ -439,7 +439,7 @@ void up_irqinitialize(void)
   * configured pin interrupts.
   */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
  kinetis_pinirqinitialize();
 #endif

--- a/arch/arm/src/kinetis/kinetis_pinirq.c
+++ b/arch/arm/src/kinetis/kinetis_pinirq.c
@ -52,7 +52,7 @@
 #include "kinetis.h"
 #include "chip/kinetis_port.h"

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ

 /****************************************************************************
 * Pre-processor Definitions
@ -450,4 +450,4 @@ void kinetis_pinirqdisable(uint32_t pinset)
    }
 #endif /* HAVE_PORTINTS */
 }
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_KINETIS_GPIOIRQ */
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@ -49,7 +49,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/kinetis/kinetis_sdhc.c
 *
- *   Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -85,10 +85,6 @@
 #  define CONFIG_KINETIS_SDHC_PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif

-#ifndef CONFIG_KINETIS_SDHC_DMAPRIO
-#  define CONFIG_KINETIS_SDHC_DMAPRIO DMA_CCR_PRIMED
-#endif
-
 #ifndef CONFIG_DEBUG_MEMCARD_INFO
 #  undef CONFIG_SDIO_XFRDEBUG
 #endif
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@ -2738,7 +2738,7 @@ static int khci_interrupt(int irq, void *context)
 #ifdef CONFIG_USBOTG
  /* Session Request Protocol (SRP) Time Out Check */

-  /* if USB OTG SRP is ready */
+  /* Check if USB OTG SRP is ready */
 #  warning "Missing logic"
    {
      /* Check if the 1 millisecond timer has expired */
@ -2960,6 +2960,8 @@ x
        }
    }

+  UNUSED(otgir); /* May not be used, depending on above conditional logic */
+
  /* Clear the pending USB interrupt.  Goto is used in the above to assure
   * that all interrupt exists pass through this logic.
   */
--- a/arch/arm/src/kl/Kconfig
+++ b/arch/arm/src/kl/Kconfig
@ -345,12 +345,12 @@ config KL_TPM2_CHANNEL

 comment "Kinetis GPIO Interrupt Configuration"

-config GPIO_IRQ
+config KL_GPIOIRQ
 	bool "GPIO pin interrupts"
 	---help---
 		Enable support for interrupting GPIO pins

-if GPIO_IRQ
+if KL_GPIOIRQ

 config KL_PORTAINTS
 	bool "GPIOA interrupts"
--- a/arch/arm/src/kl/Make.defs
+++ b/arch/arm/src/kl/Make.defs
@ -81,7 +81,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += kl_userspace.c
 endif

-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_KL_GPIOIRQ),y)
 CHIP_CSRCS += kl_gpioirq.c
 endif

--- a/arch/arm/src/kl/kl_gpio.h
+++ b/arch/arm/src/kl/kl_gpio.h
@ -386,7 +386,7 @@ xcpt_t kl_gpioirqattach(uint32_t pinset, xcpt_t pinisr);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
 void kl_gpioirqenable(uint32_t pinset);
 #else
 #  define kl_gpioirqenable(pinset)
@ -400,7 +400,7 @@ void kl_gpioirqenable(uint32_t pinset);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
 void kl_gpioirqdisable(uint32_t pinset);
 #else
 #  define kl_gpioirqdisable(pinset)
--- a/arch/arm/src/kl/kl_gpioirq.c
+++ b/arch/arm/src/kl/kl_gpioirq.c
@ -51,7 +51,7 @@
 #include "chip/kl_port.h"
 #include "kl_gpio.h"

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ

 /****************************************************************************
 * Pre-processor Definitions
@ -396,4 +396,4 @@ void kl_gpioirqdisable(uint32_t pinset)
    }
 #endif /* HAVE_PORTINTS */
 }
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_KL_GPIOIRQ */
--- a/arch/arm/src/kl/kl_irq.c
+++ b/arch/arm/src/kl/kl_irq.c
@ -248,7 +248,7 @@ void up_irqinitialize(void)
   * configured pin interrupts.
   */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
  kl_gpioirqinitialize();
 #endif

--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@ -48,7 +48,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/lpc11xx/Kconfig
+++ b/arch/arm/src/lpc11xx/Kconfig
@ -237,7 +237,7 @@ config CAN_REGDEBUG

 endmenu

-config GPIO_IRQ
+config LPC11_GPIOIRQ
 	bool "GPIO interrupt support"
 	default n
 	---help---
--- a/arch/arm/src/lpc11xx/Make.defs
+++ b/arch/arm/src/lpc11xx/Make.defs
@ -84,7 +84,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += lpc11_userspace.c
 endif

-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC11_GPIOIRQ),y)
 CHIP_CSRCS += lpc11_gpioint.c
 endif

--- a/arch/arm/src/lpc11xx/lpc111x_gpio.c
+++ b/arch/arm/src/lpc11xx/lpc111x_gpio.c
@ -79,7 +79,7 @@
 * actually set up to interrupt until the interrupt is enabled.
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
 uint64_t g_intedge0;
 uint64_t g_intedge2;
 #endif
@ -295,7 +295,7 @@ static int lpc11_pullup(lpc11_pinset_t cfgset, unsigned int port,
 *
 ****************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
 static void lpc11_setintedge(unsigned int port, unsigned int pin,
                             unsigned int value)
 {
@ -323,7 +323,7 @@ static void lpc11_setintedge(unsigned int port, unsigned int pin,
  *intedge &= ~((uint64_t)3     << shift);
  *intedge |=  ((uint64_t)value << shift);
 }
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC11_GPIOIRQ */

 /****************************************************************************
 * Name: lpc11_setopendrain
@ -453,7 +453,7 @@ static inline int lpc11_configinput(lpc11_pinset_t cfgset, unsigned int port,

      /* Forget about any falling/rising edge interrupt enabled */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
      lpc11_setintedge(port, pin, 0);
 #endif
    }
@ -495,7 +495,7 @@ static inline int lpc11_configinterrupt(lpc11_pinset_t cfgset, unsigned int port
  /* Then just remember the rising/falling edge interrupt enabled */

  DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
  lpc11_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
 #endif
  return OK;
--- a/arch/arm/src/lpc11xx/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/lpc11_gpio.h
@ -88,7 +88,7 @@ extern "C"
 * lpc11_gpioint.c, and lpc11_gpiodbg.c
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
 EXTERN uint64_t g_intedge0;
 EXTERN uint64_t g_intedge2;
 #endif
@ -108,7 +108,7 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS];
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
 void lpc11_gpioirqinitialize(void);
 #else
 #  define lpc11_gpioirqinitialize()
@ -152,7 +152,7 @@ bool lpc11_gpioread(lpc11_pinset_t pinset);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
 void lpc11_gpioirqenable(int irq);
 #else
 #  define lpc11_gpioirqenable(irq)
@ -166,7 +166,7 @@ void lpc11_gpioirqenable(int irq);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
 void lpc11_gpioirqdisable(int irq);
 #else
 #  define lpc11_gpioirqdisable(irq)
--- a/arch/arm/src/lpc11xx/lpc11_gpioint.c
+++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c
@ -51,7 +51,7 @@
 #include "chip.h"
 #include "lpc11_gpio.h"

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ

 /****************************************************************************
 * Pre-processor Definitions
@ -543,5 +543,5 @@ void lpc11_gpioirqdisable(int irq)
    }
 }

-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC11_GPIOIRQ */

--- a/arch/arm/src/lpc11xx/lpc11_irq.c
+++ b/arch/arm/src/lpc11xx/lpc11_irq.c
@ -244,7 +244,7 @@ void up_irqinitialize(void)
   * configured pin interrupts.
   */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
  lpc11_gpioirqinitialize();
 #endif

--- a/arch/arm/src/lpc11xx/lpc11_timer.c
+++ b/arch/arm/src/lpc11xx/lpc11_timer.c
@ -47,7 +47,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/lpc17xx/Kconfig
+++ b/arch/arm/src/lpc17xx/Kconfig
@ -604,7 +604,7 @@ config LPC17_CAN_REGDEBUG

 endmenu

-config GPIO_IRQ
+config LPC17_GPIOIRQ
 	bool "GPIO interrupt support"
 	default n
 	---help---
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@ -133,7 +133,7 @@ ifeq ($(CONFIG_LPC17_EMC),y)
 CHIP_CSRCS += lpc17_emc.c
 endif

-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC17_GPIOIRQ),y)
 CHIP_CSRCS += lpc17_gpioint.c
 endif

--- a/arch/arm/src/lpc17xx/lpc176x_gpio.c
+++ b/arch/arm/src/lpc17xx/lpc176x_gpio.c
@ -78,7 +78,7 @@
 * actually set up to interrupt until the interrupt is enabled.
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 uint64_t g_intedge0;
 uint64_t g_intedge2;
 #endif
@ -300,7 +300,7 @@ static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port,
 *
 ****************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 static void lpc17_setintedge(unsigned int port, unsigned int pin,
                             unsigned int value)
 {
@ -328,7 +328,7 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin,
  *intedge &= ~((uint64_t)3     << shift);
  *intedge |=  ((uint64_t)value << shift);
 }
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */

 /****************************************************************************
 * Name: lpc17_setopendrain
@ -412,7 +412,7 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un

      /* Forget about any falling/rising edge interrupt enabled */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
      lpc17_setintedge(port, pin, 0);
 #endif
    }
@ -453,7 +453,7 @@ static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port
  /* Then just remember the rising/falling edge interrupt enabled */

  DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
  lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
 #endif
  return OK;
--- a/arch/arm/src/lpc17xx/lpc178x_gpio.c
+++ b/arch/arm/src/lpc17xx/lpc178x_gpio.c
@ -79,7 +79,7 @@
 * actually set up to interrupt until the interrupt is enabled.
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 uint64_t g_intedge0;
 uint64_t g_intedge2;
 #endif
@ -526,7 +526,7 @@ static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port,
 *
 ****************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 static void lpc17_setintedge(unsigned int port, unsigned int pin,
                             unsigned int value)
 {
@ -554,7 +554,7 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin,
  *intedge &= ~((uint64_t)3     << shift);
  *intedge |=  ((uint64_t)value << shift);
 }
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */

 /****************************************************************************
 * Name: lpc17_configinput
@ -601,7 +601,7 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port,

      /* Forget about any falling/rising edge interrupt enabled */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
      lpc17_setintedge(port, pin, 0);
 #endif
    }
@ -656,7 +656,7 @@ static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port
  /* Then just remember the rising/falling edge interrupt enabled */

  DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
  lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
 #endif
  return OK;
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@ -57,7 +57,7 @@
 #include <arch/board/board.h>
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #include "up_internal.h"
 #include "up_arch.h"
--- a/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpio.h
@ -89,7 +89,7 @@ extern "C"
 * lpc17_gpioint.c, and lpc17_gpiodbg.c
 */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 EXTERN uint64_t g_intedge0;
 EXTERN uint64_t g_intedge2;
 #endif
@ -109,7 +109,7 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS];
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 void lpc17_gpioirqinitialize(void);
 #else
 #  define lpc17_gpioirqinitialize()
@ -153,7 +153,7 @@ bool lpc17_gpioread(lpc17_pinset_t pinset);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 void lpc17_gpioirqenable(int irq);
 #else
 #  define lpc17_gpioirqenable(irq)
@ -167,7 +167,7 @@ void lpc17_gpioirqenable(int irq);
 *
 ************************************************************************************/

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
 void lpc17_gpioirqdisable(int irq);
 #else
 #  define lpc17_gpioirqdisable(irq)
--- a/arch/arm/src/lpc17xx/lpc17_gpioint.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpioint.c
@ -51,7 +51,7 @@
 #include "chip.h"
 #include "lpc17_gpio.h"

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ

 /****************************************************************************
 * Pre-processor Definitions
@ -543,4 +543,4 @@ void lpc17_gpioirqdisable(int irq)
    }
 }

-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
--- a/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/arch/arm/src/lpc17xx/lpc17_irq.c
@ -412,7 +412,7 @@ void up_irqinitialize(void)
   * GPIO pins.
   */

-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
  lpc17_gpioirqinitialize();
 #endif

@ -456,7 +456,7 @@ void up_disable_irq(int irq)
          putreg32(regval, regaddr);
        }
    }
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
  else if (irq >= LPC17_VALID_FIRST0L)
    {
      /* Maybe it is a (derived) GPIO IRQ */
@ -501,7 +501,7 @@ void up_enable_irq(int irq)
          putreg32(regval, regaddr);
        }
    }
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
  else if (irq >= LPC17_VALID_FIRST0L)
    {
      /* Maybe it is a (derived) GPIO IRQ */
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@ -47,7 +47,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@ -47,7 +47,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/lpc17xx/lpc17_timer.c
+++ b/arch/arm/src/lpc17xx/lpc17_timer.c
@ -47,7 +47,7 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@ -81,36 +81,43 @@ config ARCH_FAMILY_LPC4320
 	bool
 	default y if ARCH_CHIP_LPC4320FBD144 || ARCH_CHIP_LPC4320FET100
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 config ARCH_FAMILY_LPC4330
 	bool
 	default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 || ARCH_CHIP_LPC4337JET100
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 config ARCH_FAMILY_LPC4337
 	bool
 	default y if ARCH_CHIP_LPC4337JBD144
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 config ARCH_FAMILY_LPC4350
 	bool
 	default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 config ARCH_FAMILY_LPC4353
 	bool
 	default y if ARCH_CHIP_LPC4353FBD208 || ARCH_CHIP_LPC4353FET180 || ARCH_CHIP_LPC4353FET256
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 config ARCH_FAMILY_LPC4357
 	bool
 	default y if ARCH_CHIP_LPC4357FET180 || ARCH_CHIP_LPC4357FBD208 || ARCH_CHIP_LPC4357FET256
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 config ARCH_FAMILY_LPC4370
 	bool
 	default y if ARCH_CHIP_LPC4370FET100
 	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_AHB_SRAM_BANK1

 choice
 	prompt "LPC43XX Boot Configuration"
@ -177,9 +184,15 @@ config LPC43_DAC
 config LPC43_EMC
 	bool "External Memory Controller (EMC)"
 	default n
+	select ARCH_HAVE_EXTSDRAM0
+	select ARCH_HAVE_EXTSDRAM1
+	select ARCH_HAVE_EXTSDRAM2
+	select ARCH_HAVE_EXTSDRAM3

 config LPC43_ETHERNET
 	bool "Ethernet"
+	select NETDEVICES
+	select ARCH_HAVE_PHY
 	default n

 config LPC43_EVNTMNTR
@ -320,6 +333,158 @@ config LPC43_GPIO_IRQ
 	---help---
 		Enable support for GPIO interrupts

+menu "Internal Memory Configuration"
+
+config ARCH_HAVE_AHB_SRAM_BANK1
+	bool
+
+if !LPC43_BOOT_SRAM
+
+config LPC43_USE_LOCSRAM_BANK1
+	bool "Use local SRAM bank 1 memory region"
+	default n
+	---help---
+		Add local SRAM bank 1 memory region.
+
+endif # LPC43_BOOT_SRAM
+
+config LPC43_USE_AHBSRAM_BANK0
+	bool "Use AHB SRAM bank 0 memory region"
+	default n
+	---help---
+		Add local AHB SRAM bank 0 memory region.
+
+config LPC43_USE_AHBSRAM_BANK1
+	bool "Use AHB SRAM bank 1 memory region"
+	default n
+	depends on ARCH_HAVE_AHB_SRAM_BANK1
+	---help---
+		Add local AHB SRAM bank 1 memory region.
+
+config LPC43_HEAP_AHBSRAM_BANK2
+	bool "Use AHB SRAM bank 2 (ETB SRAM) memory region"
+	default n
+	---help---
+		Add local AHB SRAM bank 2 (ETB SRAM) memory region.
+
+endmenu # LPC43xx Internal Memory Configuration
+
+menu "External Memory Configuration"
+
+config ARCH_HAVE_EXTSDRAM0
+	bool
+
+config ARCH_HAVE_EXTSDRAM1
+	bool
+
+config ARCH_HAVE_EXTSDRAM2
+	bool
+
+config ARCH_HAVE_EXTSDRAM3
+	bool
+
+config LPC43_EXTSDRAM0
+	bool "Configure external SDRAM0 (on DYNCS0)"
+	default n
+	depends on ARCH_HAVE_EXTSDRAM0
+	select ARCH_HAVE_EXTSDRAM
+	---help---
+		Configure external SDRAM memory and, if applicable, map then external
+		SDRAM into the memory map.
+
+if LPC43_EXTSDRAM0
+
+config LPC43_EXTSDRAM0_SIZE
+	int "External SDRAM0 size"
+	default 0
+	---help---
+		Size of the external SDRAM on DYNCS0 in bytes.
+
+config LPC43_EXTSDRAM0_HEAP
+	bool "Add external SDRAM on DYNCS0 to the heap"
+	default y
+	---help---
+		Add the external SDRAM on DYNCS0 into the heap.
+
+endif # LCP43_EXTSDRAM0
+
+config LPC43_EXTSDRAM1
+	bool "Configure external SDRAM1 (on DYNCS1)"
+	default n
+	depends on ARCH_HAVE_EXTSDRAM1
+	select ARCH_HAVE_EXTSDRAM
+	---help---
+		Configure external SDRAM memoryand, if applicable, map then external
+		SDRAM into the memory map.
+
+if LPC43_EXTSDRAM1
+
+config LPC43_EXTSDRAM1_SIZE
+	int "External SDRAM1 size"
+	default 0
+	---help---
+		Size of the external SDRAM on DYNCS1 in bytes.
+
+config LPC43_EXTSDRAM1_HEAP
+	bool "Add external SDRAM on DYNCS1 to the heap"
+	default y
+	---help---
+		Add the external SDRAM on DYNCS1 into the heap.
+
+endif # LCP43_EXTSDRAM1
+
+config LPC43_EXTSDRAM2
+	bool "Configure external SDRAM2 (on DYNCS2)"
+	default n
+	depends on ARCH_HAVE_EXTSDRAM2
+	select ARCH_HAVE_EXTSDRAM
+	---help---
+		Configure external SDRAM memoryand, if applicable, map then external
+		SDRAM into the memory map.
+
+if LPC43_EXTSDRAM2
+
+config LPC43_EXTSDRAM2_SIZE
+	int "External SDRAM2 size"
+	default 0
+	---help---
+		Size of the external SDRAM on DYNCS2 in bytes.
+
+config LPC43_EXTSDRAM2_HEAP
+    bool "Add external SDRAM on DYNCS2 to the heap"
+	default y
+	---help---
+	    Add the external SDRAM on DYNCS2 into the heap.
+
+endif # LCP43_EXTSDRAM2
+
+config LPC43_EXTSDRAM3
+	bool "Configure external SDRAM3 (on DYNCS3)"
+	default n
+	depends on ARCH_HAVE_EXTSDRAM3
+	select ARCH_HAVE_EXTSDRAM
+	---help---
+		Configure external SDRAM memoryand, if applicable, map then external
+		SDRAM into the memory map.
+
+if LPC43_EXTSDRAM3
+
+config LPC43_EXTSDRAM3_SIZE
+	int "External SDRAM3 size"
+	default 0
+	---help---
+		Size of the external SDRAM in bytes.
+
+config LPC43_EXTSDRAM3_HEAP
+	bool "Add external SDRAM on DYNCS3 to the heap"
+	default y
+	---help---
+		Add the external SDRAM on DYNCS3 into the heap.
+
+endif # LCP43_EXTSDRAM3
+
+endmenu # External Memory Configuration
+
 if LPC43_ETHERNET
 menu "Ethernet MAC configuration"

--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@ -126,6 +126,10 @@ ifeq ($(CONFIG_LPC43_ETHERNET),y)
 CHIP_CSRCS += lpc43_ethernet.c
 endif

+ifeq ($(CONFIG_LPC43_EMC),y)
+CHIP_CSRCS += lpc43_emc.c
+endif
+
 ifeq ($(CONFIG_LPC43_SPI),y)
 CHIP_CSRCS += lpc43_spi.c
 else
--- a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
+++ b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
@ -90,6 +90,8 @@
 /* AHB SRAM */

 #define LPC43_AHBSRAM_BANK0_BASE   (LPC43_AHBSRAM_BASE)
+#define LPC43_AHBSRAM_BANK1_BASE   (LPC43_AHBSRAM_BASE + 0x00008000)
+#define LPC43_AHBSRAM_BANK2_BASE   (LPC43_AHBSRAM_BASE + 0x0000c000)
 #define LPC43_EEPROM_BASE          (LPC43_AHBSRAM_BASE + 0x00004000)
 #define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x02000000)

--- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
+++ b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
@ -190,86 +190,86 @@
 #define PINCONF_CTOUT15_2        (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_0)
 #define PINCONF_CTOUT15_3        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_11)

-#define PINCONF_EMC_A0           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_9)
-#define PINCONF_EMC_A1           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_10)
-#define PINCONF_EMC_A2           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_11)
-#define PINCONF_EMC_A3           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_12)
-#define PINCONF_EMC_A4           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_13)
-#define PINCONF_EMC_A5           (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_0)
-#define PINCONF_EMC_A6           (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_1)
-#define PINCONF_EMC_A7           (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_2)
-#define PINCONF_EMC_A8           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_8)
-#define PINCONF_EMC_A9           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_7)
-#define PINCONF_EMC_A10          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_6)
-#define PINCONF_EMC_A11          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_2)
-#define PINCONF_EMC_A12          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_1)
-#define PINCONF_EMC_A13          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_0)
-#define PINCONF_EMC_A14          (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_8)
-#define PINCONF_EMC_A15          (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_7)
-#define PINCONF_EMC_A16          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_16)
-#define PINCONF_EMC_A17          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_15)
-#define PINCONF_EMC_A18          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_0)
-#define PINCONF_EMC_A19          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_1)
-#define PINCONF_EMC_A20          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_2)
-#define PINCONF_EMC_A21          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_3)
-#define PINCONF_EMC_A22          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_4)
-#define PINCONF_EMC_A23          (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_4)
-#define PINCONF_EMC_BLS0         (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_4)
-#define PINCONF_EMC_BLS1         (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_6)
-#define PINCONF_EMC_BLS2         (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_13)
-#define PINCONF_EMC_BLS3         (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_10)
-#define PINCONF_EMC_CAS          (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_4)
-#define PINCONF_EMC_CKEOUT0      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_11)
-#define PINCONF_EMC_CKEOUT1      (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_2)
-#define PINCONF_EMC_CKEOUT2      (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_1)
-#define PINCONF_EMC_CKEOUT3      (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_15)
-#define PINCONF_EMC_CS0          (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_5)
-#define PINCONF_EMC_CS1          (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_3)
-#define PINCONF_EMC_CS2          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_12)
-#define PINCONF_EMC_CS3          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_11)
-#define PINCONF_EMC_D0           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_7)
-#define PINCONF_EMC_D1           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_8)
-#define PINCONF_EMC_D2           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_9)
-#define PINCONF_EMC_D3           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_10)
-#define PINCONF_EMC_D4           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_11)
-#define PINCONF_EMC_D5           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_12)
-#define PINCONF_EMC_D6           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_13)
-#define PINCONF_EMC_D7           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_14)
-#define PINCONF_EMC_D8           (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_4)
-#define PINCONF_EMC_D9           (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_5)
-#define PINCONF_EMC_D10          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_6)
-#define PINCONF_EMC_D11          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_7)
-#define PINCONF_EMC_D12          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_0)
-#define PINCONF_EMC_D13          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_1)
-#define PINCONF_EMC_D14          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_2)
-#define PINCONF_EMC_D15          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_3)
-#define PINCONF_EMC_D16          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_2)
-#define PINCONF_EMC_D17          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_3)
-#define PINCONF_EMC_D18          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_4)
-#define PINCONF_EMC_D19          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_5)
-#define PINCONF_EMC_D20          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_6)
-#define PINCONF_EMC_D21          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_7)
-#define PINCONF_EMC_D22          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_8)
-#define PINCONF_EMC_D23          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_9)
-#define PINCONF_EMC_D24          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_5)
-#define PINCONF_EMC_D25          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_6)
-#define PINCONF_EMC_D26          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_7)
-#define PINCONF_EMC_D27          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_8)
-#define PINCONF_EMC_D28          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_9)
-#define PINCONF_EMC_D29          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_10)
-#define PINCONF_EMC_D30          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_11)
-#define PINCONF_EMC_D31          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_12)
-#define PINCONF_EMC_DQMOUT0      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_12)
-#define PINCONF_EMC_DQMOUT1      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_10)
-#define PINCONF_EMC_DQMOUT2      (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_0)
-#define PINCONF_EMC_DQMOUT3      (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_13)
-#define PINCONF_EMC_DYCS0        (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_9)
-#define PINCONF_EMC_DYCS1        (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_1)
-#define PINCONF_EMC_DYCS2        (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_14)
-#define PINCONF_EMC_DYCS3        (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_14)
-#define PINCONF_EMC_OE           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_3)
-#define PINCONF_EMC_RAS          (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5)
-#define PINCONF_EMC_WE           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_EMC_A0           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_EMC_A1           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_EMC_A2           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_EMC_A3           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_12)
+#define PINCONF_EMC_A4           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_EMC_A5           (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_EMC_A6           (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_EMC_A7           (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_EMC_A8           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_EMC_A9           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_EMC_A10          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_EMC_A11          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_EMC_A12          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_EMC_A13          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_EMC_A14          (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_EMC_A15          (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_EMC_A16          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_EMC_A17          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_EMC_A18          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_0)
+#define PINCONF_EMC_A19          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_1)
+#define PINCONF_EMC_A20          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_EMC_A21          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_EMC_A22          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_4)
+#define PINCONF_EMC_A23          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSA|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS0         (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS1         (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_EMC_BLS2         (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_EMC_BLS3         (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_10)
+#define PINCONF_EMC_CAS          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_EMC_CKEOUT0      (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_11)
+#define PINCONF_EMC_CKEOUT1      (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_EMC_CKEOUT2      (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_EMC_CKEOUT3      (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_EMC_CS0          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_EMC_CS1          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_EMC_CS2          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_12)
+#define PINCONF_EMC_CS3          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_EMC_D0           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_EMC_D1           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_EMC_D2           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_EMC_D3           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_EMC_D4           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_EMC_D5           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_EMC_D6           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_EMC_D7           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_EMC_D8           (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_EMC_D9           (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_EMC_D10          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_EMC_D11          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_EMC_D12          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_EMC_D13          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_EMC_D14          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_EMC_D15          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_EMC_D16          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_EMC_D17          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_EMC_D18          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_EMC_D19          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_EMC_D20          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_EMC_D21          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_EMC_D22          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_EMC_D23          (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_EMC_D24          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_EMC_D25          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_EMC_D26          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_EMC_D27          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_EMC_D28          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_EMC_D29          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_EMC_D30          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_EMC_D31          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT0      (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT1      (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_10)
+#define PINCONF_EMC_DQMOUT2      (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_EMC_DQMOUT3      (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_EMC_DYCS0        (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_9)
+#define PINCONF_EMC_DYCS1        (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_EMC_DYCS2        (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_14)
+#define PINCONF_EMC_DYCS3        (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_14)
+#define PINCONF_EMC_OE           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_EMC_RAS          (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_EMC_WE           (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6)

 #define PINCONF_ENET_COL_1       (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1)
 #define PINCONF_ENET_COL_2       (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_6)
--- a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
+++ b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
@ -1,7 +1,7 @@
 /****************************************************************************************************
 * arch/arm/src/lpc43xx/chip/lpc43_ccu.h
 *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -45,6 +45,7 @@
 /****************************************************************************************************
 * Pre-processor Definitions
 ****************************************************************************************************/
+
 /* Register Offsets *********************************************************************************/

 #define LPC43_CCU1_PM_OFFSET                 0x0000 /* CCU1 power mode register */
@ -343,6 +344,23 @@
 #define CCU_CLK_STAT_WAKEUP                  (1 << 2)  /* Bit 2:  Wake-up mechanism enable status */
                                                       /* Bits 3-31:  Reserved */

+/* CCU1 Branch Clock EMCDIV Configuration Registers */
+
+#define CCU_CLK_EMCDIV_CFG_RUN               (1 << 0)  /* Bit 0: Run enable */
+#define CCU_CLK_EMCDIV_CFG_AUTO              (1 << 1)  /* Bit 1: Auto (AHB disable mechanism) enable */
+#define CCU_CLK_EMCDIV_CFG_WAKEUP            (1 << 2)  /* Bit 2: Wake-up mechanism enable */
+                                                       /* Bits 3-4: Reserved */
+#define CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT       (5)                                         /* Bits 5-7: Clock divider */
+#define CCU_CLK_EMCDIV_CLOCK_DIV_MASK        (7 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT)
+#  define CCU_CLK_EMCDIV_CFG_DIV_FUNC(n)     ((n) << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT)
+#  define CCU_CLK_EMCDIV_CFG_DIV_NODIV       (0 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: No division */
+#  define CCU_CLK_EMCDIV_CFG_DIV_BY2         (1 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: Division by 2 */
+                                                       /* Bits 8-26: Reserved */
+#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT   (27)                                        /* Bits 27-29: Clock divider status */
+#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK    (7 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT)
+#  define CCU_CLK_EMCDIV_CFG_DIVSTAT_NODIV   (0 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT) /* Bit 27-29: No division */
+#  define CCU_CLK_EMCDIV_CFG_DIVSTAT_BY2     (1 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK)  /* Bit 26-29: Divistion by 2 */
+
 /****************************************************************************************************
 * Public Types
 ****************************************************************************************************/
--- a/arch/arm/src/lpc43xx/chip/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/chip/lpc43_emc.h
@ -1,7 +1,7 @@
 /****************************************************************************************************
 * arch/arm/src/lpc43xx/chip/lpc43_emc.h
 *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -45,6 +45,7 @@
 /****************************************************************************************************
 * Pre-processor Definitions
 ****************************************************************************************************/
+
 /* Register Offsets *********************************************************************************/

 #define LPC43_EMC_CONTROL_OFFSET          0x0000 /* EMC Control register */
@ -213,6 +214,7 @@
 #define EMC_CONTROL_LOWPOWER              (1 << 2)  /* Bit 2:  Low-power mode */
                                                    /* Bits 3-31: Reserved */
 /* EMC Status register */
+
 #define EMC__
 #define EMC_STATUS_BUSY                   (1 << 0)  /* Bit 0:  Busy */
 #define EMC_STATUS_WB                     (1 << 1)  /* Bit 1:  Write buffer status */
@ -333,13 +335,64 @@
 #  define EMC_DYNCONFIG_MD_SDRAM           (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM (POR reset value) */
                                                     /* Bits 5-6: Reserved */
 #define EMC_DYNCONFIG_AM0_SHIFT            (7)       /* Bits 7-12: AM0 Address mapping (see user manual) */
-#define EMC_DYNCONFIG_AM0_MASK             (0x3f << EMC_DYNCONFIG_AM0_SHIFT)
+#define EMC_DYNCONFIG_AM0_MASK             (0x3F << EMC_DYNCONFIG_AM0_SHIFT)
                                                     /* Bit 13: Reserved */
 #define EMC_DYNCONFIG_AM1                  (1 << 14) /* Bit 14: AM1 Address mapping (see user manual) */
                                                     /* Bits 15-18: Reserved */
-#define EMC_DYNCONFIG_BENA                 (1 << 10) /* Bit 19: Buffer enable */
+#define EMC_DYNCONFIG_BENA                 (1 << 19) /* Bit 19: Buffer enable */
 #define EMC_DYNCONFIG_WP                   (1 << 20) /* Bit 20: Write protect. */
                                                     /* Bits 21-31: Reserved */
+
+/* Dynamic Memory Configuration register  Memory Configuration Values */
+/* TODO: complete configuration */
+
+/* Data Bus Width Value in LPC43_EMC_DYNCONFIG register (bit 14) */
+
+#define EMC_DYNCONFIG_DATA_BUS_16          (0 << 14) /* Data bus width 16 bit */
+#define EMC_DYNCONFIG_DATA_BUS_32          (1 << 14) /* Data bus width 32 bit */
+
+/* Low power SDRAM value in LPC43_EMC_DYNCONFIG register (bit 12) */
+
+#define EMC_DYNCONFIG_LPSDRAM              (1 << 12) /* Low power SDRAM value (Bank, Row, Column)*/
+#define EMC_DYNCONFIG_HPSDRAM              (0 << 12) /* High performance SDRAM value (Row, Bank, Column)*/
+
+/* Address mapping table for LPC43_EMC_DYNCONFIG register (bits 7-11) */
+
+/* Device size bits in LPC43_EMC_DYNCONFIG register (bits 9-11) */
+
+#define EMC_DYNCONFIG_DEV_SIZE_SHIFT       (9)
+#define EMC_DYNCONFIG_DEV_SIZE_MASK        (0x7)
+#  define EMC_DYNCONFIG_DEV_SIZE_16Mb      (0x00 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+#  define EMC_DYNCONFIG_DEV_SIZE_64Mb      (0x01 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+#  define EMC_DYNCONFIG_DEV_SIZE_128Mb     (0x02 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+#  define EMC_DYNCONFIG_DEV_SIZE_256Mb     (0x03 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+#  define EMC_DYNCONFIG_DEV_SIZE_512Mb     (0x04 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+
+/* Bus width bits in LPC43_EMC_DYNCONFIG register (bits 7-8) */
+
+#define EMC_DYNCONFIG_DEV_BUS_SHIFT        (7)
+#define EMC_DYNCONFIG_DEV_BUS_MASK         (0x3)
+#  define EMC_DYNCONFIG_DEV_BUS_8          (0x00 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+#  define EMC_DYNCONFIG_DEV_BUS_16         (0x01 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+#  define EMC_DYNCONFIG_DEV_BUS_32         (0x02 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+
+#define EMC_DYNCONFIG_2Mx8_2BANKS_11ROWS_9COLS    ((0x0 << 9) | (0x0 << 7))  /* 16Mb  (2Mx8),   2 banks, row length = 11, column length = 9  */
+#define EMC_DYNCONFIG_1Mx16_2BANKS_11ROWS_8COLS   ((0x0 << 9) | (0x1 << 7))  /* 16Mb  (1Mx16),  2 banks, row length = 11, column length = 8  */
+#define EMC_DYNCONFIG_8Mx8_4BANKS_12ROWS_9COLS    ((0x1 << 9) | (0x0 << 7))  /* 64Mb  (8Mx8),   4 banks, row length = 12, column length = 9  */
+#define EMC_DYNCONFIG_4Mx16_4BANKS_12ROWS_8COLS   ((0x1 << 9) | (0x1 << 7))  /* 64Mb  (4Mx16),  4 banks, row length = 12, column length = 8  */
+#define EMC_DYNCONFIG_2Mx32_4BANKS_11ROWS_8COLS   ((0x1 << 9) | (0x2 << 7))  /* 64Mb  (2Mx32),  4 banks, row length = 11, column length = 8, 32 bit bus only */
+#define EMC_DYNCONFIG_16Mx8_4BANKS_12ROWS_10COLS  ((0x2 << 9) | (0x0 << 7))  /* 128Mb (16Mx8),  4 banks, row length = 12, column length = 10 */
+#define EMC_DYNCONFIG_8Mx16_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))  /* 128Mb (8Mx16),  4 banks, row length = 12, column length = 9  */
+#define EMC_DYNCONFIG_4Mx32_4BANKS_12ROWS_8COLS   ((0x2 << 9) | (0x2 << 7))  /* 128Mb (4Mx32),  4 banks, row length = 12, column length = 8  */
+#define EMC_DYNCONFIG_32Mx8_4BANKS_13ROWS_10COLS  ((0x3 << 9) | (0x0 << 7))  /* 256Mb (32Mx8),  4 banks, row length = 13, column length = 10, 32 bit bus only */
+#define EMC_DYNCONFIG_16Mx16_4BANKS_13ROWS_9COLS  ((0x3 << 9) | (0x1 << 7))  /* 256Mb (16Mx16), 4 banks, row length = 13, column length = 9  */
+#define EMC_DYNCONFIG_8Mx32_4BANKS_13ROWS_8COLS   ((0x3 << 9) | (0x2 << 7))  /* 256Mb (8Mx32),  4 banks, row length = 13, column length = 8, 32 bit bus only  */
+#define EMC_DYNCONFIG_8Mx32_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))  /* 256Mb (8Mx32),  4 banks, row length = 12, column length = 9, 32 bit bus only  */
+#define EMC_DYNCONFIG_64Mx8_4BANKS_13ROWS_10COLS  ((0x4 << 9) | (0x0 << 7))  /* 512Mb (64Mx8),  4 banks, row length = 13, column length = 11 */
+#define EMC_DYNCONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7))  /* 512Mb (32Mx16), 4 banks, row length = 13, column length = 10 */
+#define EMC_DYNCONFIG_16Mx32_4BANKS_13ROWS_9COLS  ((0x3 << 9) | (0x1 << 7))  /* 512Mb (16Mx32), 4 banks, row length = 13, column length = 9, 32 bit bus only  */
+#define EMC_DYNCONFIG_32Mx32_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7))  /* 1Gb   (32Mx32), 4 banks, row length = 13, column length = 10,32 bit bus only  */
+
 /* Dynamic Memory RAS & CAS Delay registers */

 #define EMC_DYNRASCAS_RAS_SHIFT            (0)       /* Bits 0-1: RAS latency (active to read/write delay) */
@ -354,6 +407,35 @@
 #  define EMC_DYNRASCAS_CAS_2CCLK          (2 << EMC_DYNRASCAS_CAS_SHIFT) /* Two CCLK cycles */
 #  define EMC_DYNRASCAS_CAS_3CCLK          (3 << EMC_DYNRASCAS_CAS_SHIFT) /* Three CCLK cycles (POR reset value) */
                                                     /* Bits 10-31: Reserved */
+
+/* Dynamic SDRAM mode register definitions */
+
+                                                     /* Bits 0-2: Burst length. All other values are reserved. */
+#define EMC_DYNMODE_BURST_LENGTH_SHIFT     (0)
+#define EMC_DYNMODE_BURST_LENGTH_MASK      (0x7)
+#  define EMC_DYNMODE_BURST_LENGTH_1       (0 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+#  define EMC_DYNMODE_BURST_LENGTH_2       (1 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+#  define EMC_DYNMODE_BURST_LENGTH_4       (2 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+#  define EMC_DYNMODE_BURST_LENGTH_8       (3 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+                                                     /* Bit 3: Burst mode type */
+#define EMC_DYNMODE_BURST_TYPE_SHIFT            (3)
+#  define EMC_DYNMODE_BURST_TYPE_SEQUENTIAL     (0 << EMC_DYNMODE_BURST_TYPE_SHIFT)       /* burst type sequential */
+#  define EMC_DYNMODE_BURST_TYPE_INTERLEAVED    (1 << EMC_DYNMODE_BURST_TYPE_INTERLEAVED) /* burst type interleaved */
+                                                     /* Bits 4-6: Latency mode. All other values are reserved. */
+#define EMC_DYNMODE_CAS_SHIFT              (4)
+#define EMC_DYNMODE_CAS_MASK               (0x7)
+#  define EMC_DYNMODE_CAS_2                (2 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 2 cycles */
+#  define EMC_DYNMODE_CAS_3                (3 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 3 cycles */
+                                                     /* Bits 7-8: Operating mode. All other values are reserved. */
+#define EMC_DYNMODE_OPMODE_SHIFT           (7)
+#define EMC_DYNMODE_OPMODE_MASK            (0x3)
+#  define EMC_DYNMODE_OPMODE_STANDARD      (0 << EMC_DYNMODE_OPMODE_SHIFT) /* dynamic standard operation mode */
+                                                    /* Bit 9: Write burst mode */
+#define EMC_DYNMODE_WBMODE_SHIFT           (9)
+#  define EMC_DYNMODE_WBMODE_PROGRAMMED    (0 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode programmed */
+#  define EMC_DYNMODE_WBMODE_SINGLE_LOC    (1 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode single loc */
+                                                    /* Bits 10-11: Reserved */
+
 /* Static Memory Configuration registers */

 #define EMC_STATCONFIG_MW_SHIFT            (0)       /* Bits 0-1: Memory width */
--- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c
+++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c
@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/lpc43xx/lpc43_allocateheap.c
 *
- *   Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012-2013, 2015-2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -61,6 +61,7 @@
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
+
 /* Get customizations for each supported chip.
 *
 * SRAM Resources
@ -95,6 +96,25 @@
 * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
 * banks but are treated as two banks of 48 an 16Kb by the NuttX memory
 * manager.  This gives some symmetry to all of the members of the family.
+ *
+ * ----------------------------------------------------------------------
+ * EMC SDRAM
+ * ----------------------------------------------------------------------
+ * LPC43xx may have dynamic RAM connected on EMC bus. Up to 4 chips can be
+ * connected.
+ *
+ * DYCS0 (0x2800 0000) up to 128MB
+ * DYCS1 (0x3000 0000) up to 256MB
+ * DYCS2 (0x6000 0000) up to 256MB
+ * DYCS3 (0x7000 0000) up to 256MB
+ *
+ * LPC43xx may have static RAM connected on EMC bus.
+ *
+ * CS0 (0x1C00 0000) up to 16MB
+ * CS1 (0x1D00 0000) up to 16MB
+ * CS2 (0x1E00 0000) up to 16MB
+ * CS3 (0x1F00 0000) up to 16MB
+ *
 */

 /* Configuration ************************************************************/
@ -136,58 +156,89 @@
 *
 *    CONFIG_RAM_START = The start of the data RAM region which may be
 *      either local SRAM bank 0 (Configuration A) or 1 (Configuration B).
- *    CONFIG_RAM_START = The size of the data RAM region.
- *    CONFIG_RAM_END   = The sum of the above
+ *    CONFIG_RAM_SIZE  = The size of the data RAM region.
+ *    CONFIG_RAM_END   = The sum of the above.
+ */
+
+/* External Memory Configuration
+ *
+ * Dynamic memory configuration
+ *   For dynamic memory configuration at least one of LPC43_EXTSDRAMx
+ *   should by defined.
+ * Also, together with LPC43_EXTSDRAMx should be defined:
+ *   LPC43_EXTSDRAMxSIZE = External RAM size in bytes.
+ *   LPC43_EXTSDRAMxHEAP = Should this RAM be use as heap space?
 */

 /* Check for Configuration A. */

+#undef MM_USE_LOCSRAM_BANK0
+#undef MM_USE_LOCSRAM_BANK1
+#undef MM_USE_AHBSRAM_BANK0
+#undef MM_USE_AHBSRAM_BANK1
+#undef MM_USE_AHBSRAM_BANK2
+#undef MM_USE_EXTSDRAM0
+#undef MM_USE_EXTSDRAM1
+#undef MM_USE_EXTSDRAM2
+#undef MM_USE_EXTSDRAM3
+#undef MM_HAVE_REGION
+
 #ifndef CONFIG_LPC43_BOOT_SRAM

 /* Configuration A */
-/* CONFIG_RAM_START should be set to the base of AHB SRAM, local 0. */
+/* CONFIG_RAM_START shoudl be set to the base of local SRAM, Bank 0. */

 #  if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE
-#    error "CONFIG_RAM_START must be set to the base address of RAM Bank 0"
+#    error "CONFIG_RAM_START must be set to the base address of RAM bank 0"
 #  endif

-/* The configured RAM size should be equal to the size of local SRAM Bank 0 */
+/* The configured RAM size should be equal to the size of local SRAM Bank 0. */

 #  if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE
-#    error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 0"
+#    error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 0"
 #  endif

-/* Now we can assign all of the memory regions for configuration A */
+/* Local SRAM Bank 0 will be used as main memory region */

-#  define MM_REGION1_BASE  LPC43_LOCSRAM_BANK0_BASE
-#  define MM_REGION1_SIZE  LPC43_LOCSRAM_BANK0_SIZE
-#  define MM_REGION2_BASE  LPC43_LOCSRAM_BANK1_BASE
-#  define MM_REGION2_SIZE  LPC43_LOCSRAM_BANK1_SIZE
-#  define MM_REGION3_BASE  LPC43_AHBSRAM_BANK0_BASE
-#  define MM_REGION3_SIZE  LPC43_AHBSRAM_BANK0_SIZE
-#else
+#  define MM_USE_LOCSRAM_BANK0 0
+
+/* Use local SRAM Bank 1 if configured */
+
+#  ifdef CONFIG_LPC43_USE_LOCSRAM_BANK1
+#    define MM_USE_LOCSRAM_BANK1 1
+#  endif
+
+#else /* CONFIG_LPC43_BOOT_SRAM */

 /* Configuration B */
-/* CONFIG_RAM_START should be set to the base of local SRAM, bank 1. */
+/* CONFIG_RAM_START should be set to the base of local SRAM, Bank 1. */

 #  if CONFIG_RAM_START != LPC43_LOCSRAM_BANK1_BASE
-#    error "CONFIG_RAM_START must be set to the base address of SRAM Bank 1"
+#    error "CONFIG_RAM_START must be set to the base address of RAM bank 1"
 #  endif

-/* The configured RAM size should be equal to the size of local SRAM Bank 1 */
+/* The configured RAM size should be equal to the size of local SRAM Bank 1. */

 #  if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE
-#    error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 1"
+#    error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 1"
 #  endif

-/* Now we can assign all of the memory regions for configuration B */
+/* Shouldn't use Local SRAM Bank 0 as system use it for code.
+ * Local SRAM Bank1 is used as main memory region.
+ */

-#  define MM_REGION1_BASE  LPC43_LOCSRAM_BANK1_BASE
-#  define MM_REGION1_SIZE  LPC43_LOCSRAM_BANK1_SIZE
-#  define MM_REGION2_BASE  LPC43_AHBSRAM_BANK0_BASE
-#  define MM_REGION2_SIZE  LPC43_AHBSRAM_BANK0_SIZE
-#  undef  MM_REGION3_BASE
-#  undef  MM_REGION3_SIZE
+#  define MM_USE_LOCSRAM_BANK1 0
+
+#endif /* CONFIG_LPC43_BOOT_SRAM */
+
+/* Configure other memory banks */
+
+#ifdef CONFIG_LPC43_AHBSRAM_BANK0
+#  define MM_USE_AHBSRAM_BANK0 1
+#endif
+
+#ifdef CONFIG_LPC43_AHBSRAM_BANK1
+#  define MM_USE_AHBSRAM_BANK1 1
 #endif

 #define MM_DMAREGION_BASE  LPC43_AHBSRAM_BANK2_BASE
@ -199,8 +250,69 @@

 #warning "Missing Logic"

-#define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
-#define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+#ifdef CONFIG_LPC43_AHBSRAM_BANK2
+#  define MM_USE_AHBSRAM_BANK2 1
+#  define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
+#  define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+#endif
+
+/* External RAM configuration */
+
+/* Check if external SDRAM is supported and, if so, it is intended to be used
+ * used as heap.
+ */
+
+#if !defined(CONFIG_LPC43_EXTSDRAM0) || !defined(CONFIG_LPC43_EXTSDRAM0_HEAP)
+#  undef CONFIG_LPC43_EXTSDRAM0_SIZE
+#  define CONFIG_LPC43_EXTSDRAM0_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM1) || !defined(CONFIG_LPC43_EXTSDRAM1_HEAP)
+#  undef CONFIG_LPC43_EXTSDRAM1_SIZE
+#  define CONFIG_LPC43_EXTSDRAM1_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM2) || !defined(CONFIG_LPC43_EXTSDRAM2_HEAP)
+#  undef CONFIG_LPC43_EXTSDRAM2_SIZE
+#  define CONFIG_LPC43_EXTSDRAM2_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM3) || !defined(CONFIG_LPC43_EXTSDRAM3_HEAP)
+#  undef CONFIG_LPC43_EXTSDRAM3_SIZE
+#  define CONFIG_LPC43_EXTSDRAM3_SIZE 0
+#endif
+
+#if CONFIG_LPC43_EXTSDRAM0_SIZE > 0
+#  define MM_USE_EXTSDRAM0 1
+#  define MM_EXTSDRAM0_REGION LPC43_DYCS0_BASE
+#  define MM_EXTSDRAM0_SIZE   CONFIG_LPC43_EXTSDRAM0_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM0_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM1_SIZE > 0
+#  define MM_USE_EXTSDRAM1 1
+#  define MM_EXTSDRAM1_REGION LPC43_DYCS1_BASE
+#  define MM_EXTSDRAM1_SIZE   CONFIG_LPC43_EXTSDRAM1_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM2_SIZE > 0
+#  define MM_USE_EXTSDRAM2 1
+#  define MM_EXTSDRAM2_REGION LPC43_DYCS2_BASE
+#  define MM_EXTSDRAM2_SIZE   CONFIG_LPC43_EXTSDRAM2_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM3_SIZE > 0
+#  define HAVE_EXTSDRAM3_REGION 1
+#  define MM_EXTSDRAM3_REGION LPC43_DYCS3_BASE
+#  define MM_EXTSDRAM3_SIZE   CONFIG_LPC43_EXTSDRAM3_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM3_SIZE */
+
+#if CONFIG_MM_REGIONS > 1 && \
+    (defined(MM_USE_LOCSRAM_BANK1) || defined(MM_USE_AHBSRAM_BANK0) || \
+     defined(MM_USE_AHBSRAM_BANK1) || defined(MM_USE_AHBSRAM_BANK2) || \
+     defined(MM_USE_EXTSDRAM0)     || defined(MM_USE_EXTSDRAM1) || \
+     defined(MM_USE_EXTSDRAM2)     || defined(MM_USE_EXTSDRAM3))
+#  define MM_HAVE_REGION 1
+#endif

 /****************************************************************************
 * Private Data
@ -216,15 +328,31 @@
 * thread is the thread that the system boots on and, eventually, becomes the
 * idle, do nothing task that runs only when there is nothing else to run.
 * The heap continues from there until the configured end of memory.
- * g_idle_topstack is the beginning of this heap region (not necessarily aligned).
+ * g_idle_topstack is the beginning of this heap region (not necessarily
+ * aligned).
 */

 const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;

+#ifdef MM_HAVE_REGION
+static uint8_t g_mem_region_next = 0;
+#endif
+
 /****************************************************************************
 * Private Functions
 ****************************************************************************/

+#ifdef MM_HAVE_REGION
+static void mem_addregion(FAR void *region_start, size_t region_size)
+{
+  if (g_mem_region_next <= CONFIG_MM_REGIONS)
+    {
+      kmm_addregion(region_start, region_size);
+      g_mem_region_next++;
+    }
+}
+#endif
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@ -265,35 +393,42 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 #if CONFIG_MM_REGIONS > 1
 void up_addregion(void)
 {
-#if CONFIG_MM_REGIONS > 1
-  /* Add the next SRAM region (which should exist) */
+#ifdef MM_HAVE_REGION
+  /* start from second region */

-  kmm_addregion((FAR void *)MM_REGION2_BASE, MM_REGION2_SIZE);
+  g_mem_region_next = 2;

-#ifdef MM_REGION3_BASE
-  /* Add the third SRAM region (which will not exist in configuration B) */
+#  ifdef MM_USE_LOCSRAM_BANK1
+  mem_addregion((FAR void *)LPC43_LOCSRAM_BANK1_BASE, LPC43_LOCSRAM_BANK1_SIZE);
+#  endif

-#if CONFIG_MM_REGIONS > 2
-  /* Add the third SRAM region (which may not exist) */
+#  ifdef MM_USE_AHBSRAM_BANK0
+  mem_addregion((FAR void *)LPC43_AHBSRAM_BANK0_BASE, LPC43_AHBSRAM_BANK0_SIZE);
+#  endif

-  kmm_addregion((FAR void *)MM_REGION3_BASE, MM_REGION3_SIZE);
+#  ifdef MM_USE_AHBSRAM_BANK1
+  mem_addregion((FAR void *)LPC43_AHBSRAM_BANK1_BASE, LPC43_AHBSRAM_BANK1_SIZE);
+#  endif

-#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE)
-  /* Add the DMA region (which may not be available) */
+#  ifdef MM_USE_AHBSRAM_BANK2
+  mem_addregion((FAR void *)MM_DMAREGION_BASE, MM_DMAREGION_SIZE);
+#  endif

-  kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
+#  ifdef MM_USE_EXTSDRAM0
+  mem_addregion((FAR void *)MM_EXTSDRAM0_REGION, MM_EXTSDRAM0_SIZE);
+#  endif

-#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
-#endif /* CONFIG_MM_REGIONS > 2 */
-#else  /* MM_REGION3_BASE */
+#  ifdef MM_USE_EXTSDRAM1
+  mem_addregion((FAR void *)MM_EXTSDRAM1_REGION, MM_EXTSDRAM1_SIZE);
+#  endif

-#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE)
-  /* Add the DMA region (which may not be available) */
+#  ifdef MM_USE_EXTSDRAM2
+  mem_addregion((FAR void *)MM_EXTSDRAM2_REGION, MM_EXTSDRAM2_SIZE);
+#  endif

-  kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
-
-#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
-#endif /* MM_REGION3_BASE */
-#endif /* CONFIG_MM_REGIONS > 1 */
+#  ifdef MM_USE_EXTSDRAM3
+  mem_addregion((FAR void *)MM_EXTSDRAM3_REGION, MM_EXTSDRAM3_SIZE);
+#  endif
+#endif
 }
 #endif
--- a/arch/arm/src/lpc43xx/lpc43_emc.c
+++ b/arch/arm/src/lpc43xx/lpc43_emc.c
@ -0,0 +1,141 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_emc.c
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+
+/* TODO: add #if defined(CONFIG_LPC43_EMC) */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <time.h>
+#include <string.h>
+#include <debug.h>
+#include <queue.h>
+#include <errno.h>
+
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/wdog.h>
+
+#include "up_internal.h"
+
+#include "chip.h"
+#include "lpc43_pinconfig.h"
+#include "lpc43_emc.h"
+#include "chip/lpc43_creg.h"
+#include "chip/lpc43_cgu.h"
+#include "chip/lpc43_ccu.h"
+#include "lpc43_rgu.h"
+#include "lpc43_gpio.h"
+#include "up_arch.h"
+#include <arch/board/board.h>
+
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_emcinit
+ *
+ * Description:
+ *   Initialize EMC controller. Start in full power
+ *   mode.
+ *
+ ****************************************************************************/
+void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode)
+{
+  uint32_t regval;
+
+  /* Enable clock for EMC controller. */
+
+  regval = getreg32(LPC43_CCU1_M4_EMC_CFG);
+  regval |= CCU_CLK_CFG_RUN;
+  putreg32(regval, LPC43_CCU1_M4_EMC_CFG);
+
+  /* Configure endian mode and clock ratio. */
+
+  regval = 0;
+  if (endian_mode)
+    regval |= EMC_CONFIG_EM;
+  if (clock_ratio)
+    regval |= EMC_CONFIG_CR;
+
+  putreg32(regval, LPC43_EMC_CONFIG);
+
+  /* Enable EMC 001 normal memory map, no low power mode. */
+
+  putreg32(EMC_CONTROL_ENA, LPC43_EMC_CONTROL);
+}
+
+/****************************************************************************
+ * Name: lpc43_lowpowermode
+ *
+ * Description:
+ *   Set EMC lowpower mode.
+ *
+ ****************************************************************************/
+void lpc43_lowpowermode(uint8_t enable)
+{
+  uint32_t regval;
+
+  regval = getreg32(LPC43_EMC_CONTROL);
+  if (enable)
+    {
+      regval |= EMC_CONTROL_LOWPOWER;
+      putreg32(regval, LPC43_EMC_CONTROL);
+    }
+  else
+    {
+      regval &= ~EMC_CONTROL_LOWPOWER;
+      putreg32(regval, LPC43_EMC_CONTROL);
+    }
+}
+
+/****************************************************************************
+ * Name: lpc43_emcenable
+ *
+ * Description:
+ *   Enable or disable EMC controller.
+ *
+ ****************************************************************************/
+void lpc43_emcenable(uint8_t enable)
+{
+  uint32_t regval;
+
+  regval = getreg32(LPC43_EMC_CONTROL);
+  if (enable)
+    {
+      regval |= EMC_CONTROL_ENA;
+      putreg32(regval, LPC43_EMC_CONTROL);
+    }
+  else
+    {
+      regval &= ~EMC_CONTROL_ENA;
+      putreg32(regval, LPC43_EMC_CONTROL);
+    }
+}
--- a/arch/arm/src/lpc43xx/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/lpc43_emc.h
@ -1,7 +1,7 @@
 /************************************************************************************
 * arch/arm/src/lpc43xx/lpc43_emc.h
 *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -48,16 +48,22 @@
 * Pre-processor Definitions
 ************************************************************************************/

-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/* Chip select Definitions **********************************************************/
+
+#define EMC_CS0    0
+#define EMC_CS1    1
+#define EMC_CS2    2
+#define EMC_CS3    3
+
+#define EMC_DYNCS0 0
+#define EMC_DYNCS1 1
+#define EMC_DYNCS2 2
+#define EMC_DYNCS3 3

 /************************************************************************************
- * Public Data
+ * Public Function Prototypes
 ************************************************************************************/

-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode);

 #endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H */
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@ -91,10 +91,6 @@ volatile uint32_t *g_current_regs[1];

 extern uint32_t _vectors[];

-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
@ -250,15 +246,9 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,

  if (irq >= LPC43_IRQ_EXTINT)
    {
-      n = irq - LPC43_IRQ_EXTINT;
+      n        = irq - LPC43_IRQ_EXTINT;
      *regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
-      while (n >= 32)
-        {
-          n -= 32;
-        }
-
-      *bit     = 1 << n;
+      *bit     = (uint32_t)1 << (n & 0x1f);
    }

  /* Handle processor exceptions.  Only a few can be disabled */
--- a/arch/arm/src/lpc43xx/lpc43_spifi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.c
@ -1,7 +1,7 @@
 /****************************************************************************
 *  arch/arm/src/lpc43/lpc43_spifi.c
 *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -779,12 +779,13 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
  lpc43_cachewrite(priv, buffer, startblock, nblocks);

  lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_512SHIFT)
-  return nblocks;
+  return (ssize_t)nblocks;

 #else

  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
  FAR uint8_t *dest;
+  int ret;

  finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);

@ -792,19 +793,17 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t

  dest = SPIFI_BASE + (startblock << SPIFI_BLKSHIFT);

-#if defined(CONFIG_SPIFI_SECTOR512)
  /* Write all of the erase blocks to FLASH */

-  ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_512SHIFT);
+  ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_BLKSHIFT);
  if (ret < 0)
    {
      ferr("ERROR: lpc43_pagewrite failed: %d\n", ret);
      return ret;
    }
-#endif

-  lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT)
-  return nblocks;
+  lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT);
+  return (ssize_t)nblocks;

 #endif
 }
--- a/arch/arm/src/sam34/chip/sam3x_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam3x_memorymap.h
@ -91,6 +91,7 @@
 #  define SAM_TC8_BASE         0x40088080 /* 0x40088080-0x400880bf:   Timer Counter 5 */
                                          /* 0x400880c0-0x4008ffff    Reserved */
 #define SAM_TWI_BASE           0x4008c000 /* 0x4008c000-0x4001ffff: Two-Wire Interface */
+#  define SAM_TWIN_BASE(n)     (SAM_TWI_BASE + ((n) << 14))
 #  define SAM_TWI0_BASE        0x4008c000 /* 0x4008c000-0x4008ffff:   Two-Wire Interface 0 */
 #  define SAM_TWI1_BASE        0x40090000 /* 0x40090000-0x40093fff:   Two-Wire Interface 1 */
 #define SAM_PWM_BASE           0x40094000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */
--- a/arch/arm/src/sam34/chip/sam4cm_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4cm_memorymap.h
@ -77,8 +77,12 @@
 #define SAM_TC3_BASE           0x40014000
 #define SAM_TC4_BASE           0x40014040
 #define SAM_TC5_BASE           0x40014080
+
+#define SAM_TWI_BASE           0x40018000
+#define SAM_TWIN_BASE(n)       (SAM_TWI_BASE + ((n) << 14))
 #define SAM_TWI0_BASE          0x40018000
 #define SAM_TWI1_BASE          0x4001C000
+
 #define SAM_USART0_BASE        0x40024000
 #define SAM_USART1_BASE        0x40028000
 #define SAM_USART2_BASE        0x4002C000
--- a/arch/arm/src/sam34/chip/sam4e_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4e_memorymap.h
@ -108,6 +108,7 @@
 #  define SAM_USART0_BASE      0x400a0000 /* 0x400a0000-0x400a3fff:   USART0 */
 #  define SAM_USART1_BASE      0x400a4000 /* 0x400a4000-0x400abfff:   USART1 */
 #define SAM_TWI_BASE           0x400a8000 /* 0x400a8000-0x400affff: Two-Wire Interface */
+#  define SAM_TWIN_BASE(n)     (SAM_TWI_BASE + ((n) << 14))
 #  define SAM_TWI0_BASE        0x400a8000 /* 0x400a8000-0x400abfff:   Two-Wire Interface 0 */
 #  define SAM_TWI1_BASE        0x400ac000 /* 0x400ac000-0x400affff:   Two-Wire Interface 1 */
 #define SAM_AFEC_BASE          0x400b0000 /* 0x400b0000-0x400b7fff: Analog Front End */
--- a/arch/arm/src/sam34/chip/sam4l_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4l_memorymap.h
@ -82,6 +82,9 @@
                                        /* 0x4000c000-0x4000ffff: Reserved */
 #define SAM_TC0_BASE         0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */
 #define SAM_TC1_BASE         0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */
+
+#define SAM_TWIMS_BASE       0x40180000 /* 0x40180000-0x401fffff: Two-wire Master/Slave */
+#define SAM_TWIN_BASE(n)     (SAM_TWIMS_BASE + ((n) << 14))
 #define SAM_TWIMS0_BASE      0x40180000 /* 0x40180000-0x401bffff: Two-wire Master/Slave Interface 0 */
 #define SAM_TWIMS1_BASE      0x401c0000 /* 0x401c0000-0x401fffff: Two-wire Master/Slave Interface 1 */
                                        /* 0x40020000-0x40023fff: Reserved */
--- a/arch/arm/src/sam34/chip/sam4s_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h
@ -84,6 +84,7 @@
 #  define SAM_TC5_BASE         0x40014080 /* 0x40014080-0x400140bf:   Timer Counter 5 */

 #define SAM_TWI_BASE           0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */
+#  define SAM_TWIN_BASE(n)     (SAM_TWI_BASE + ((n) << 14))
 #  define SAM_TWI0_BASE        0x40018000 /* 0x40018000-0x4001bfff:   Two-Wire Interface 0 */
 #  define SAM_TWI1_BASE        0x4001c000 /* 0x4001c000-0x4001ffff:   Two-Wire Interface 1 */
 #define SAM_PWM_BASE           0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */
--- a/arch/arm/src/sam34/chip/sam_tc.h
+++ b/arch/arm/src/sam34/chip/sam_tc.h
@ -2,7 +2,7 @@
 * arch/arm/src/sam34/chip/sam_tc.h
 * Timer Counter (TC) definitions for the SAM3U, SAM4E, and SAM4S
 *
- *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -537,16 +537,10 @@
 #  define TC_BMR_TC1XC1S_TIOA2       (3 << TC_BMR_TC1XC1S_SHIFT)
 #define TC_BMR_TC2XC2S_SHIFT         (4)       /* Bits 4-5: External Clock Signal 2 Selection */
 #define TC_BMR_TC2XC2S_MASK          (3 << TC_BMR_TC2XC2S_SHIFT)
-#if defined(CONFIG_ARCH_CHIP_SAM4s) || defined(CONFIG_ARCH_CHIP_SAM4E)
-#  define TC_BMR_TC2XC2S_TCLK2       (0 << TC_BMR_TC2XC2S_SHIFT)
-#  define TC_BMR_TC2XC2S_TIOA1       (2 << TC_BMR_TC2XC2S_SHIFT)
-#  define TC_BMR_TC2XC2S_TIOA2       (3 << TC_BMR_TC2XC2S_SHIFT)
-#else
 #  define TC_BMR_TC2XC2S_TCLK2       (0 << TC_BMR_TC2XC2S_SHIFT)
 #  define TC_BMR_TC2XC2S_NONE        (1 << TC_BMR_TC2XC2S_SHIFT)
 #  define TC_BMR_TC2XC2S_TIOA0       (2 << TC_BMR_TC2XC2S_SHIFT)
 #  define TC_BMR_TC2XC2S_TIOA1       (3 << TC_BMR_TC2XC2S_SHIFT)
-#endif
 #define TC_BMR_QDEN                  (1 << 8)  /* Bit 8:  Quadrature Decoder Enabled */
 #define TC_BMR_POSEN                 (1 << 9)  /* Bit 9:  Position Enabled */
 #define TC_BMR_SPEEDEN               (1 << 10) /* Bit 10: Speed Enabled */
--- a/arch/arm/src/sam34/chip/sam_twi.h
+++ b/arch/arm/src/sam34/chip/sam_twi.h
@ -143,6 +143,7 @@
 #define TWI_MMR_MREAD              (1 << 12) /* Bit 12: Master Read Direction */
 #define TWI_MMR_DADR_SHIFT         (16)      /* Bits 16-22:  Device Address */
 #define TWI_MMR_DADR_MASK          (0x7f << TWI_MMR_DADR_SHIFT)
+#  define TWI_MMR_DADR(n)          ((uint32_t)(n) << TWI_MMR_DADR_SHIFT)

 /* TWI Slave Mode Register */

@ -186,6 +187,9 @@
 #define TWI_INT_RXBUFF             (1 << 14) /* Bit 14: RX Buffer */
 #define TWI_INT_TXBUFE             (1 << 15) /* Bit 15: TX Buffer Empty */

+#define TWI_INT_ERRORS             (0x00000340)
+#define TWI_INT_ALL                (0x0000ffff)
+
 /* TWI Receive Holding Register */

 #define TWI_RHR_RXDATA_SHIFT       (0)       /* Bits 0-7:  Master or Slave Receive Holding Data */
--- a/arch/arm/src/sam34/sam_serial.c
+++ b/arch/arm/src/sam34/sam_serial.c
@ -692,8 +692,8 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr)

 static int up_setup(struct uart_dev_s *dev)
 {
-  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
 #ifndef CONFIG_SUPPRESS_UART_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
  uint32_t regval;
  uint32_t imr;

--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@ -305,6 +305,7 @@ struct sam_ep_s
  uint8_t              zlpneeded:1;  /* Zero length packet needed at end of transfer */
  uint8_t              zlpsent:1;    /* Zero length packet has been sent */
  uint8_t              txbusy:1;     /* Write request queue is busy (recursion avoidance kludge) */
+  uint8_t              lastbank:1;   /* Last bank we read data from */
 };

 struct sam_usbdev_s
@ -1188,9 +1189,14 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,

  /* We get here when an RXDATABK0/1 interrupt occurs.  That interrupt
   * cannot be cleared until all of the data has been taken from the RX
-   * FIFO.  But we can
+   * FIFO.
+   *
+   * Also, we need to remember which bank we read last so the interrupt handler
+   * can determine the correct bank read sequence for future reads.
   */

+  privep->lastbank = bank;
+
  sam_csr_clrbits(epno, bank ? UDPEP_CSR_RXDATABK1 : UDPEP_CSR_RXDATABK0);

  /* Complete the transfer immediately and give the data to the class
@ -1873,7 +1879,6 @@ static void sam_ep_bankinterrupt(struct sam_usbdev_s *priv,
       * transferred from the FIFO.
       */

-      privep->epstate = UDP_EPSTATE_IDLE;
      (void)sam_req_read(priv, privep, pktsize, bank);
    }

@ -1959,6 +1964,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
  struct sam_ep_s *privep;
  uintptr_t regaddr;
  uint32_t csr;
+  bool bk0;
+  bool bk1;

  DEBUGASSERT((unsigned)epno < SAM_UDP_NENDPOINTS);

@ -2020,34 +2027,82 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
        }
    }

-  /* OUT packet received in data bank 0 */

-  if ((csr & UDPEP_CSR_RXDATABK0) != 0)
+  /* OUT packet received.
+   *
+   * OUT packets are received in two banks. The hardware does not provide
+   * information about which bank has been filled last. Therefore we need to
+   * keep track about which bank we read last to figure out which bank(s) we
+   * need to read next.
+   *
+   * When we get here either none, one or both banks can be filled with data.
+   * Depending on which bank we read last and which bank(s) contain data we
+   * need to correctly sequence the FIFO reads:
+   *
+   * case  lastbank      bk0    bk1     read sequence
+   *  1.      0           0      0      No data to read
+   *  2.      0           1      0      Only read bank 0
+   *  3.      0           0      1      Only read bank 1
+   *  4.      0           1      1      Read bank 1, then read bank 0
+   *
+   *  5.      1           0      0      No data to read
+   *  6.      1           1      0      Only read bank 0
+   *  7.      1           0      1      Only read bank 1 (should not happen)
+   *  8.      1           1      1      Read bank 0, then read bank 1
+   *
+   * lastbank will be updated in sam_req_read() after the FIFO has been read
+   * and clear RXDATABKx.
+   */
+
+  bk0 = (csr & UDPEP_CSR_RXDATABK0) != 0;
+  bk1 = (csr & UDPEP_CSR_RXDATABK1) != 0;
+
+  /* 2. and 6. - Only read bank 0 */
+
+  if (bk0 && !bk1)
    {
      usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
-
-      /* Handle data received on Bank 0.  sam_ep_bankinterrupt will
-       * clear the  RXDATABK0 interrupt once that data has been
-       * transferred from the FIFO.
-       */
-
      sam_ep_bankinterrupt(priv, privep, csr, 0);
    }

-  /* OUT packet received in data bank 1 */
+  /* 3. and 7. - Only read bank 1*/

-  else if ((csr & UDPEP_CSR_RXDATABK1) != 0)
+  else if (!bk0 && bk1)
    {
+#ifdef CONFIG_DEBUG_USB_WARN
+      if (privep->lastbank == 1)
+        {
+          uwarn("WARNING: Unexpected USB RX case.\n");
+        }
+#endif
+
      usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
-      DEBUGASSERT(SAM_UDP_NBANKS(epno) > 1);
-
-      /* Handle data received on Bank 1.  sam_ep_bankinterrupt will
-       * clear the  RXDATABK1 interrupt once that data has been
-       * transferred from the FIFO.
-       */
-
      sam_ep_bankinterrupt(priv, privep, csr, 1);
    }
+  else if (bk0 && bk1)
+    {
+      /* 4. - Read bank 1, then read bank 0 */
+
+      if (privep->lastbank == 0)
+        {
+          usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
+          sam_ep_bankinterrupt(priv, privep, csr, 1);
+
+          usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+          sam_ep_bankinterrupt(priv, privep, csr, 0);
+        }
+
+      /* 8. - Read bank 0, then read bank 1 */
+
+      else
+        {
+          usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+          sam_ep_bankinterrupt(priv, privep, csr, 0);
+
+          usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
+          sam_ep_bankinterrupt(priv, privep, csr, 1);
+        }
+    }

  /* STALL sent */

@ -2510,6 +2565,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
  privep->zlpneeded = false;
  privep->zlpsent   = false;
  privep->txbusy    = false;
+  privep->lastbank  = 1;
 }

 /****************************************************************************
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@ -60,7 +60,7 @@

 #include <arch/board/board.h>
 #include <nuttx/arch.h>
-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #include "up_internal.h"
 #include "up_arch.h"
--- a/arch/arm/src/sama5/sam_can.h
+++ b/arch/arm/src/sama5/sam_can.h
@ -45,7 +45,7 @@
 #include "chip.h"
 #include "chip/sam_can.h"

-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1))

--- a/arch/arm/src/sama5/sam_pwm.c
+++ b/arch/arm/src/sama5/sam_pwm.c
@ -47,7 +47,7 @@
 #include <debug.h>

 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>

 #include "chip/sam_pinmap.h"
 #include <arch/board/board.h>
--- a/arch/arm/src/sama5/sam_trng.c
+++ b/arch/arm/src/sama5/sam_trng.c
@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/sama5/sam_trng.c
 *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Derives, in part, from Max Holtzberg's STM32 RNG Nuttx driver:
@ -52,6 +52,8 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/drivers/drivers.h>

 #include "up_arch.h"
 #include "up_internal.h"
@ -59,6 +61,9 @@
 #include "sam_periphclks.h"
 #include "sam_trng.h"

+#if defined(CONFIG_SAMA5_TRNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
 /****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/
@ -325,14 +330,10 @@ errout:
 }

 /****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_rnginitialize
+ * Name: sam_rng_initialize
 *
 * Description:
- *   Initialize the TRNG hardware and register the /dev/randome driver.
+ *   Initialize the TRNG hardware.
 *
 * Input Parameters:
 *   None
@ -342,7 +343,7 @@ errout:
 *
 ****************************************************************************/

-void up_rnginitialize(void)
+static int sam_rng_initialize(void)
 {
  int ret;

@ -360,10 +361,11 @@ void up_rnginitialize(void)

  /* Initialize the TRNG interrupt */

-  if (irq_attach(SAM_IRQ_TRNG, sam_interrupt))
+  ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt);
+  if (ret < 0)
    {
      ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
-      return;
+      return ret;
    }

  /* Disable the interrupts at the TRNG */
@ -374,16 +376,80 @@ void up_rnginitialize(void)

  putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);

-  /* Register the character driver */
-
-  ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
-  if (ret < 0)
-    {
-      ferr("ERROR: Failed to register /dev/random\n");
-      return;
-    }
-
  /* Enable the TRNG interrupt at the AIC */

  up_enable_irq(SAM_IRQ_TRNG);
+  return OK;
 }
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ *   Initialize the TRNG hardware and register the /dev/random driver.
+ *   Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+  int ret;
+
+  ret = sam_rng_initialize();
+  if (ret >= 0)
+    {
+      ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
+      if (ret < 0)
+        {
+          ferr("ERROR: Failed to register /dev/random\n");
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ *   Register /dev/urandom
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+  int ret;
+
+#ifndef CONFIG_DEV_RANDOM
+  ret = sam_rng_initialize();
+  if (ret >= 0)
+#endif
+    {
+      ret = register_driver("/dev/urandom", &g_trngops, 0644, NULL);
+      if (ret < 0)
+        {
+          ferr("ERROR: Failed to register /dev/urandom\n");
+        }
+    }
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
+#endif /* CONFIG_SAMA5_TRNG */
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@ -56,7 +56,7 @@
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
 #include <nuttx/semaphore.h>
-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #include "cache.h"
 #include "up_internal.h"
--- a/arch/arm/src/samv7/sam_mcan.h
+++ b/arch/arm/src/samv7/sam_mcan.h
@ -45,7 +45,7 @@
 #include "chip.h"
 #include "chip/sam_mcan.h"

-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #if defined(CONFIG_CAN) && (defined(CONFIG_SAMV7_MCAN0) || \
    defined(CONFIG_SAMV7_MCAN1))
--- a/arch/arm/src/samv7/sam_trng.c
+++ b/arch/arm/src/samv7/sam_trng.c
@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/samv7/sam_trng.c
 *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Derives from the SAMA5D3 TRNG Nuttx driver which, in turn, derives, in
@ -53,6 +53,8 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/drivers/drivers.h>

 #include "up_arch.h"
 #include "up_internal.h"
@ -60,6 +62,9 @@
 #include "sam_periphclks.h"
 #include "sam_trng.h"

+#if defined(CONFIG_SAMV7_TRNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
 /****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/
@ -326,14 +331,10 @@ errout:
 }

 /****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_rnginitialize
+ * Name: sam_rng_initialize
 *
 * Description:
- *   Initialize the TRNG hardware and register the /dev/randome driver.
+ *   Initialize the TRNG hardware.
 *
 * Input Parameters:
 *   None
@ -343,7 +344,7 @@ errout:
 *
 ****************************************************************************/

-void up_rnginitialize(void)
+static int sam_rng_initialize(void)
 {
  int ret;

@ -361,10 +362,11 @@ void up_rnginitialize(void)

  /* Initialize the TRNG interrupt */

-  if (irq_attach(SAM_IRQ_TRNG, sam_interrupt))
+  ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt);
+  if (ret < 0)
    {
      ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
-      return;
+      return ret;
    }

  /* Disable the interrupts at the TRNG */
@ -375,16 +377,79 @@ void up_rnginitialize(void)

  putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);

-  /* Register the character driver */
-
-  ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
-  if (ret < 0)
-    {
-      ferr("ERROR: Failed to register /dev/random\n");
-      return;
-    }
-
  /* Enable the TRNG interrupt at the AIC */

  up_enable_irq(SAM_IRQ_TRNG);
+  return OK;
 }
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ *   Initialize the TRNG hardware and register the /dev/random driver.
+ *   Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+  int ret;
+
+  ret = sam_rng_initialize();
+  if (ret >= 0)
+    {
+      ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
+      if (ret < 0)
+        {
+          ferr("ERROR: Failed to register /dev/random\n");
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ *   Register /dev/urandom
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+  int ret;
+
+#ifndef CONFIG_DEV_RANDOM
+  ret = sam_rng_initialize();
+  if (ret >= 0)
+#endif
+    {
+      ret = register_driver("/dev/urandom", &g_trngops, 0644, NULL);
+      if (ret < 0)
+        {
+          ferr("ERROR: Failed to register /dev/urandom\n");
+        }
+    }
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@ -301,6 +301,7 @@ enum sam_epstate_e
  USBHS_EPSTATE_STALLED,      /* Endpoint is stalled */
  USBHS_EPSTATE_IDLE,         /* Endpoint is idle (i.e. ready for transmission) */
  USBHS_EPSTATE_SENDING,      /* Endpoint is sending data */
+  USBHS_EPSTATE_SENDING_DMA,  /* Endpoint is sending data via DMA */
  USBHS_EPSTATE_NBUSYBK,      /* Endpoint DMA complete, waiting for NBUSYBK==0 */
  USBHS_EPSTATE_RECEIVING,    /* Endpoint is receiving data */
                              /* --- Endpoint 0 Only --- */
@ -1006,7 +1007,7 @@ static void sam_dma_wrsetup(struct sam_usbdev_s *priv, struct sam_ep_s *privep,

  /* Switch to the sending state */

-  privep->epstate   = USBHS_EPSTATE_SENDING;
+  privep->epstate   = USBHS_EPSTATE_SENDING_DMA;
  privreq->inflight = 0;

  /* Get the endpoint number */
@ -1211,16 +1212,23 @@ static void sam_req_complete(struct sam_ep_s *privep, int16_t result)

      privreq->req.result = result;

-      /* Callback to the request completion handler */
-
-      privreq->flink = NULL;
-      privreq->req.callback(&privep->ep, &privreq->req);
-
-      /* Reset the endpoint state and restore the stalled indication */
+      /* Reset the endpoint state and restore the stalled indication.
+       *
+       * At least the USB class CDC/ACM calls the function sam_ep_submit within
+       * the callback. This function uses sam_req_write or sam_req_read to process
+       * the request, both functions can change the state. Therefore it is verry
+       * important to set the state to USBHS_EPSTATE_IDLE before the callback is
+       * called.
+       */

      privep->epstate   = USBHS_EPSTATE_IDLE;
      privep->zlpneeded = false;
      privep->zlpsent   = false;
+
+      /* Callback to the request completion handler */
+
+      privreq->flink = NULL;
+      privreq->req.callback(&privep->ep, &privreq->req);
    }
 }

@ -2497,7 +2505,8 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)

      /* Were we sending?  Or receiving? */

-      if (privep->epstate == USBHS_EPSTATE_SENDING)
+      if (privep->epstate == USBHS_EPSTATE_SENDING ||
+          privep->epstate == USBHS_EPSTATE_SENDING_DMA)
        {
          uint32_t nbusybk;
          uint32_t byct;
@ -2923,7 +2932,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
       */

      if (privep->epstate == USBHS_EPSTATE_RECEIVING ||
-          privep->epstate == USBHS_EPSTATE_SENDING)
+          privep->epstate == USBHS_EPSTATE_SENDING ||
+          privep->epstate == USBHS_EPSTATE_SENDING_DMA)
        {
          sam_req_complete(privep, -EPROTO);
        }
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@ -1206,7 +1206,6 @@ config STM32_CONNECTIVITYLINE
 	select STM32_HAVE_TIM5
 	select STM32_HAVE_TIM6
 	select STM32_HAVE_TIM7
-	select STM32_HAVE_TIM8
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_CAN1
 	select STM32_HAVE_CAN2
--- a/arch/arm/src/stm32/stm32_1wire.c
+++ b/arch/arm/src/stm32/stm32_1wire.c
@ -54,9 +54,9 @@

 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
-#include <nuttx/1wire.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/clock.h>
+#include <nuttx/drivers/1wire.h>

 #include <arch/board/board.h>

--- a/arch/arm/src/stm32/stm32_can.c
+++ b/arch/arm/src/stm32/stm32_can.c
@ -53,7 +53,7 @@
 #include <arch/board/board.h>
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #include "up_internal.h"
 #include "up_arch.h"
--- a/arch/arm/src/stm32/stm32_can.h
+++ b/arch/arm/src/stm32/stm32_can.h
@ -45,7 +45,7 @@
 #include "chip.h"
 #include "chip/stm32_can.h"

-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 /************************************************************************************
 * Pre-processor Definitions
--- a/arch/arm/src/stm32/stm32_exti_alarm.c
+++ b/arch/arm/src/stm32/stm32_exti_alarm.c
@ -53,10 +53,6 @@
 #include "stm32_gpio.h"
 #include "stm32_exti.h"

-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
 /****************************************************************************
 * Private Data
 ****************************************************************************/
@ -65,10 +61,6 @@

 static xcpt_t stm32_exti_callback;

-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@ -253,15 +253,9 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,

  if (irq >= STM32_IRQ_FIRST)
    {
-      n = irq - STM32_IRQ_FIRST;
+      n        = irq - STM32_IRQ_FIRST;
      *regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
-      while (n >= 32)
-        {
-          n -= 32;
-        }
-
-      *bit     = 1 << n;
+      *bit     = (uint32_t)1 << (n & 0x1f);
    }

  /* Handle processor exceptions.  Only a few can be disabled */
--- a/arch/arm/src/stm32/stm32_oneshot.c
+++ b/arch/arm/src/stm32/stm32_oneshot.c
@ -95,9 +95,10 @@ static int stm32_oneshot_handler(int irq, void *context)
   * Disable the TC now and disable any further interrupts.
   */

+  STM32_TIM_SETISR(oneshot->tch, NULL, 0);
+  STM32_TIM_DISABLEINT(oneshot->tch, 0);
  STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
  STM32_TIM_ACKINT(oneshot->tch, 0);
-  STM32_TIM_DISABLEINT(oneshot->tch, 0);

  /* The timer is no longer running */

@ -351,6 +352,7 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot,
  /* Now we can disable the interrupt and stop the timer. */

  STM32_TIM_DISABLEINT(oneshot->tch, 0);
+  STM32_TIM_SETISR(oneshot->tch, NULL, 0);
  STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);

  oneshot->running = false;
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@ -48,7 +48,7 @@
 #include <debug.h>

 #include <nuttx/arch.h>
-#include <nuttx/pwm.h>
+#include <nuttx/drivers/pwm.h>
 #include <arch/board/board.h>

 #include "up_internal.h"
--- a/arch/arm/src/stm32/stm32_pwm.h
+++ b/arch/arm/src/stm32/stm32_pwm.h
@ -41,7 +41,7 @@
 /* The STM32 does not have dedicated PWM hardware.  Rather, pulsed output control
 * is a capabilitiy of the STM32 timers.  The logic in this file implements the
 * lower half of the standard, NuttX PWM interface using the STM32 timers.  That
- * interface is described in include/nuttx/pwm.h.
+ * interface is described in include/nuttx/drivers/pwm.h.
 */

 /************************************************************************************
--- a/arch/arm/src/stm32/stm32_rng.c
+++ b/arch/arm/src/stm32/stm32_rng.c
@ -46,16 +46,21 @@

 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/drivers/drivers.h>

 #include "up_arch.h"
 #include "chip/stm32_rng.h"
 #include "up_internal.h"

+#if defined(CONFIG_STM32_RNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
 /****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/

-static int stm32_rnginitialize(void);
+static int stm32_rng_initialize(void);
 static int stm32_interrupt(int irq, void *context);
 static void stm32_enable(void);
 static void stm32_disable(void);
@ -98,7 +103,7 @@ static const struct file_operations g_rngops =
 * Private functions
 ****************************************************************************/

-static int stm32_rnginitialize()
+static int stm32_rng_initialize()
 {
  uint32_t regval;

@ -258,8 +263,52 @@ static ssize_t stm32_read(struct file *filep, char *buffer, size_t buflen)
 * Public Functions
 ****************************************************************************/

-void up_rnginitialize()
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ *   Initialize the RNG hardware and register the /dev/random driver.
+ *   Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
 {
-  stm32_rnginitialize();
-  register_driver("/dev/random", &g_rngops, 0444, NULL);
+  stm32_rng_initialize();
+  (void)register_driver("/dev/random", &g_rngops, 0444, NULL);
 }
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ *   Register /dev/urandom
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+#ifndef CONFIG_DEV_RANDOM
+  stm32_rng_initialize();
+#endif
+  (void)register_driver("/dev/urandom", &g_rngops, 0444, NULL);
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
+#endif /* CONFIG_STM32_RNG */
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@ -282,6 +282,12 @@ void __start(void)

  showprogress('C');

+#ifdef CONFIG_ARMV7M_ITMSYSLOG
+  /* Perform ARMv7-M ITM SYSLOG initialization */
+
+  itm_syslog_initialize();
+#endif
+
  /* Perform early serial initialization */

 #ifdef USE_EARLYSERIALINIT
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@ -919,7 +919,6 @@ static inline void rcc_itm_syslog(void)
  modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH |
              DBGMCU_CR_TRACEIOEN);

-  itm_syslog_initialize();
 }
 #else
 #  define rcc_itm_syslog()
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@ -136,6 +136,7 @@ struct alm_cbinfo_s
 /* Callback to use when an EXTI is activated  */

 static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST];
+static bool g_alarm_enabled;  /* True: Alarm interrupts are enabled */
 #endif

 /****************************************************************************
@ -157,6 +158,7 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg);
 static int rtchw_check_alrbwf(void);
 static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
 #endif
+static inline void rtc_enable_alarm(void);
 #endif

 /****************************************************************************
@ -811,6 +813,46 @@ rtchw_set_alrmbr_exit:
 }
 #endif

+/****************************************************************************
+ * Name: rtc_enable_alarm
+ *
+ * Description:
+ *   Enable ALARM interrupts
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static inline void rtc_enable_alarm(void)
+{
+  /* Is the alarm already enabled? */
+
+  if (!g_alarm_enabled)
+    {
+      /* Configure RTC interrupt to catch alarm interrupts. All RTC
+       * interrupts are connected to the EXTI controller.  To enable the
+       * RTC Alarm interrupt, the following sequence is required:
+       *
+       * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt
+       *    mode and select the rising edge sensitivity.
+       *    For STM32F4xx
+       *    EXTI line 21 RTC Tamper & Timestamp
+       *    EXTI line 22 RTC Wakeup
+       * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
+       * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
+       */
+
+      stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
+      g_alarm_enabled = true;
+    }
+}
+#endif
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@ -1010,25 +1052,7 @@ int up_rtc_initialize(void)
      return -ETIMEDOUT;
    }

-#ifdef CONFIG_RTC_ALARM
-  /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts
-   * are connected to the EXTI controller.  To enable the RTC Alarm
-   * interrupt, the following sequence is required:
-   *
-   * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode
-   *    and select the rising edge sensitivity.
-   *    For STM32F4xx
-   *    EXTI line 21 RTC Tamper & Timestamp
-   *    EXTI line 22 RTC Wakeup
-   * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
-   * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
-   */
-
-  stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
-  rtc_dumpregs("After InitExtiAlarm");
-#else
  rtc_dumpregs("After Initialization");
-#endif

  g_rtc_enabled = true;
  return OK;
@ -1321,6 +1345,10 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
  ASSERT(alminfo != NULL);
  DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);

+  /* Make sure the the alarm interrupt is enabled at the NVIC */
+
+  rtc_enable_alarm();
+
  /* REVISIT:  Should test that the time is in the future */

  rtc_dumptime(&alminfo->as_time, "New alarm time");
@ -1335,7 +1363,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
             (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) |
             (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT);
 
-  /* Set the alarm in hardware and enable interrupts */
+  /* Set the alarm in hardware and enable interrupts from the RTC */

  switch (alminfo->as_id)
    {
--- a/arch/arm/src/stm32l4/stm32l4_can.c
+++ b/arch/arm/src/stm32l4/stm32l4_can.c
@ -57,7 +57,7 @@
 #include <arch/board/board.h>
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 #include "up_internal.h"
 #include "up_arch.h"
--- a/arch/arm/src/stm32l4/stm32l4_can.h
+++ b/arch/arm/src/stm32l4/stm32l4_can.h
@ -49,7 +49,7 @@
 #include "chip.h"
 #include "chip/stm32l4_can.h"

-#include <nuttx/can.h>
+#include <nuttx/drivers/can.h>

 /************************************************************************************
 * Pre-processor Definitions
--- a/arch/arm/src/stm32l4/stm32l4_irq.c
+++ b/arch/arm/src/stm32l4/stm32l4_irq.c
@ -1,8 +1,7 @@
 /****************************************************************************
 * arch/arm/src/stm32l4/stm32l4_irq.c
- * arch/arm/src/chip/stm32l4_irq.c
 *
- *   Copyright (C) 2009-2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2016 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@ -90,10 +89,6 @@ volatile uint32_t *g_current_regs[1];

 extern uint32_t _vectors[];

-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
@ -252,15 +247,9 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,

  if (irq >= STM32L4_IRQ_FIRST)
    {
-      n = irq - STM32L4_IRQ_FIRST;
+      n        = irq - STM32L4_IRQ_FIRST;
      *regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
-      while (n >= 32)
-        {
-          n -= 32;
-        }
-
-      *bit     = 1 << n;
+      *bit     = (uint32_t)1 << (n & 0x1f);
    }

  /* Handle processor exceptions.  Only a few can be disabled */
--- a/arch/arm/src/stm32l4/stm32l4_oneshot.c
+++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c
@ -96,9 +96,10 @@ static int stm32l4_oneshot_handler(int irq, FAR void *context)
   * Disable the TC now and disable any further interrupts.
   */

+  STM32L4_TIM_SETISR(oneshot->tch, NULL, 0);
+  STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
  STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
  STM32L4_TIM_ACKINT(oneshot->tch, 0);
-  STM32L4_TIM_DISABLEINT(oneshot->tch, 0);

  /* The timer is no longer running */

@ -353,6 +354,7 @@ int stm32l4_oneshot_cancel(FAR struct stm32l4_oneshot_s *oneshot,
  /* Now we can disable the interrupt and stop the timer. */

  STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
+  STM32L4_TIM_SETISR(oneshot->tch, NULL, 0);
  STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);

  oneshot->running = false;
--- a/Show more
+++ b/Show more