From 0bf4893b2cfda701bc221ef0efcb4f399ba65206 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Tue, 20 Jun 2017 11:56:54 -0600 Subject: [PATCH] STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need to enable the power overdrive for this case. This patch allows the required bits to be set in proper sequence. It also modifies the local register access operations to allow more than 16-bit registers. --- arch/arm/src/stm32/stm32_pwr.c | 52 ++++++++++++++++++++++++++++++---- arch/arm/src/stm32/stm32_pwr.h | 14 +++++++++ 2 files changed, 60 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c index b2aee60177d..2b0ed2a14cf 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/stm32/stm32_pwr.c @@ -64,19 +64,20 @@ static uint16_t g_bkp_writable_counter = 0; * Private Functions ************************************************************************************/ -static inline uint16_t stm32_pwr_getreg(uint8_t offset) +static inline uint32_t stm32_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); + return getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint32_t value) { - putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); + putreg32(value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) +static inline void stm32_pwr_modifyreg(uint8_t offset, uint32_t clearbits, + uint32_t setbits) { - modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); } /************************************************************************************ @@ -372,4 +373,43 @@ void stm32_pwr_disablepvd(void) #endif /* CONFIG_STM32_ENERGYLITE */ +/************************************************************************************ + * Name: stm32_pwr_enableoverdrive + * + * Description: + * Enable or disable the overdrive mode, allowing clock rates up to 180 MHz. + * If not enabled, the max allowed frequency is 168 MHz. + * + ************************************************************************************/ + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +void stm32_pwr_enableoverdrive(bool state) +{ + + /* Switch overdrive state */ + + if (state) + { + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_ODEN); + } + else + { + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, PWR_CR_ODEN, 0); + } + + /* Wait for overdrive ready */ + + while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_ODRDY) == 0); + + /* Set ODSWEN to switch to this new state*/ + + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_ODSWEN); + + /* Wait for completion */ + + while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_ODSWRDY) == 0); +} +#endif + #endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h index ab33eb9b2cd..19af928f145 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/stm32/stm32_pwr.h @@ -215,6 +215,20 @@ void stm32_pwr_disablepvd(void); #endif /* CONFIG_STM32_ENERGYLITE */ +/************************************************************************************ + * Name: stm32_pwr_enableoverdrive + * + * Description: + * Enable or disable the overdrive mode, allowing clock rates up to 180 MHz. + * If not enabled, the max allowed frequency is 168 MHz. + * + ************************************************************************************/ + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +void stm32_pwr_enableoverdrive(bool state); +#endif + #undef EXTERN #if defined(__cplusplus) }