From be99e773cfbd8b355b90ab46a6d2026dafb7c68f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Dec 2015 08:47:12 -0600 Subject: [PATCH 01/22] TMS570: Return serial status when a byte is read --- arch/arm/src/tms570/Kconfig | 2 ++ arch/arm/src/tms570/tms570_serial.c | 13 ++++++------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/tms570/Kconfig b/arch/arm/src/tms570/Kconfig index 9c9edbdb1de..f69ee4181e9 100644 --- a/arch/arm/src/tms570/Kconfig +++ b/arch/arm/src/tms570/Kconfig @@ -89,12 +89,14 @@ config TMS570_SCI1 bool "Serial Communication Interface 1 (SCI1)" default n select ARCH_HAVE_SCI1 + select ARCH_HAVE_SERIAL_TERMIOS config TMS570_SCI2 bool "Serial Communication Interface 2 (SCI2)" default n depends on TMS570_HAVE_SCI2 select ARCH_HAVE_SCI1 + select ARCH_HAVE_SERIAL_TERMIOS endmenu # TMS570 Peripheral Support diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c index ab176f91bc7..b4850ae1e4a 100644 --- a/arch/arm/src/tms570/tms570_serial.c +++ b/arch/arm/src/tms570/tms570_serial.c @@ -735,12 +735,9 @@ static int tms570_receive(struct uart_dev_s *dev, uint32_t *status) { struct tms570_dev_s *priv = (struct tms570_dev_s *)dev->priv; - /* Return the error information in the saved status. - * - * REVISIT: RX error information is not currently retained. - */ + /* Return the error information in the saved status. */ - *status = 0; + *status = tms570_serialin(priv, TMS570_SCI_FLR_OFFSET); /* Then return the actual received byte */ @@ -892,9 +889,11 @@ void up_serialinit(void) tms570_disableallints(TTYS1_DEV.priv, NULL); #endif - /* Configuration whichever one is the console */ - #ifdef HAVE_SERIAL_CONSOLE + /* Configure whichever one is the console. NOTE: This was already done + * in tms570_lowsetup(). + */ + CONSOLE_DEV.isconsole = true; tms570_setup(&CONSOLE_DEV); From 2563663a454e7347b01d85e2408d63f887c497e9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Dec 2015 10:39:04 -0600 Subject: [PATCH 02/22] TMS570: Add GIO header file --- arch/arm/src/tms570/chip/tms570_gio.h | 303 ++++++++++++++++++++++++++ arch/arm/src/tms570/chip/tms570_sci.h | 2 +- arch/arm/src/tms570/tms570_boot.c | 2 +- arch/arm/src/tms570/tms570_boot.h | 2 +- arch/arm/src/tms570/tms570_irq.c | 6 +- 5 files changed, 309 insertions(+), 6 deletions(-) create mode 100644 arch/arm/src/tms570/chip/tms570_gio.h diff --git a/arch/arm/src/tms570/chip/tms570_gio.h b/arch/arm/src/tms570/chip/tms570_gio.h new file mode 100644 index 00000000000..d2ccf7d437e --- /dev/null +++ b/arch/arm/src/tms570/chip/tms570_gio.h @@ -0,0 +1,303 @@ +/**************************************************************************************************** + * arch/arm/src/tms570/chip/tms570_gio.h + * Secondary System Control Register Definitions + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * + * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas + * Instruments, Literature Number: SPNU517A, September 2013 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H +#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/tms570_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +#define TMS570_GIOA 0 +#define TMS570_GIOB 1 +#define TMS570_GIOC 2 +#define TMS570_GIOD 3 +#define TMS570_GIOE 4 +#define TMS570_GIOF 5 +#define TMS570_GIOG 6 +#define TMS570_GIOH 7 + +/* Register Offsets *********************************************************************************/ + +#define TMS570_GIO_GCR0_OFFSET 0x0000 /* GIO Global Control Register */ +#define TMS570_GIO_INTDET_OFFSET 0x0008 /* GIO Interrupt Detect Register */ +#define TMS570_GIO_POL_OFFSET 0x000c /* GIO Interrupt Polarity Register */ +#define TMS570_GIO_ENASET_OFFSET 0x0010 /* GIO Interrupt Enable Set Register */ +#define TMS570_GIO_ENACLR_OFFSET 0x0014 /* GIO Interrupt Enable Clear Register */ +#define TMS570_GIO_LVLSET_OFFSET 0x0018 /* GIO Interrupt Priority Set Register */ +#define TMS570_GIO_LVLCLR_OFFSET 0x001c /* GIO Interrupt Priority Clear Register */ +#define TMS570_GIO_FLG_OFFSET 0x0020 /* GIO Interrupt Flag Register */ +#define TMS570_GIO_OFF1_OFFSET 0x0024 /* GIO Offset 1 Register */ +#define TMS570_GIO_OFF2_OFFSET 0x0028 /* GIO Offset 2 Register */ +#define TMS570_GIO_EMU1_OFFSET 0x002c /* GIO Emulation 1 Register */ +#define TMS570_GIO_EMU2_OFFSET 0x0030 /* GIO Emulation 2 Register */ + +#define TMS570_GIO_OFFSET(n) (0x0034 + ((n) << 5)) +#define TMS570_GIO_DIR_OFFSET 0x0000 /* GIO Data Direction Register */ +#define TMS570_GIO_DIN_OFFSET 0x0004 /* GIO Data Input Register */ +#define TMS570_GIO_DOUT_OFFSET 0x0008 /* GIO Data Output Register */ +#define TMS570_GIO_DSET_OFFSET 0x000c /* GIO Data Set Register */ +#define TMS570_GIO_DCLR_OFFSET 0x0010 /* GIO Data Clear Register */ +#define TMS570_GIO_PDR_OFFSET 0x0014 /* GIO Open Drain Register */ +#define TMS570_GIO_PULDIS_OFFSET 0x0018 /* GIO Pull Disable Register */ +#define TMS570_GIO_PSL_OFFSET 0x001c /* GIO Pull Select Register */ + +#define TMS570_GIOA_DIR_OFFSET 0x0034 /* GIOA Data Direction Register */ +#define TMS570_GIOA_DIN_OFFSET 0x0038 /* GIOA Data Input Register */ +#define TMS570_GIOA_DOUT_OFFSET 0x003c /* GIOA Data Output Register */ +#define TMS570_GIOA_DSET_OFFSET 0x0040 /* GIOA Data Set Register */ +#define TMS570_GIOA_DCLR_OFFSET 0x0044 /* GIOA Data Clear Register */ +#define TMS570_GIOA_PDR_OFFSET 0x0048 /* GIOA Open Drain Register */ +#define TMS570_GIOA_PULDIS_OFFSET 0x004c /* GIOA Pull Disable Register */ +#define TMS570_GIOA_PSL_OFFSET 0x0050 /* GIOA Pull Select Register */ + +#define TMS570_GIOB_DIR_OFFSET 0x0054 /* GIOB Data Direction Register */ +#define TMS570_GIOB_DIN_OFFSET 0x0058 /* GIOB Data Input Register */ +#define TMS570_GIOB_DOUT_OFFSET 0x005c /* GIOB Data Output Register */ +#define TMS570_GIOB_DSET_OFFSET 0x0060 /* GIOB Data Set Register */ +#define TMS570_GIOB_DCLR_OFFSET 0x0064 /* GIOB Data Clear Register */ +#define TMS570_GIOB_PDR_OFFSET 0x0068 /* GIOB Open Drain Register */ +#define TMS570_GIOB_PULDIS_OFFSET 0x006c /* GIOB Pull Disable Register */ +#define TMS570_GIOB_PSL_OFFSET 0x0070 /* GIOB Pull Select Register */ + +#define TMS570_GIOC_DIR_OFFSET 0x0074 /* GIOC Data Direction Register */ +#define TMS570_GIOC_DIN_OFFSET 0x0078 /* GIOC Data Input Register */ +#define TMS570_GIOC_DOUT_OFFSET 0x007c /* GIOC Data Output Register */ +#define TMS570_GIOC_DSET_OFFSET 0x0080 /* GIOC Data Set Register */ +#define TMS570_GIOC_DCLR_OFFSET 0x0084 /* GIOC Data Clear Register */ +#define TMS570_GIOC_PDR_OFFSET 0x0088 /* GIOC Open Drain Register */ +#define TMS570_GIOC_PULDIS_OFFSET 0x008c /* GIOC Pull Disable Register */ +#define TMS570_GIOC_PSL_OFFSET 0x0090 /* GIOC Pull Select Register */ + +#define TMS570_GIOD_DIR_OFFSET 0x0094 /* GIOD Data Direction Register */ +#define TMS570_GIOD_DIN_OFFSET 0x0098 /* GIOD Data Input Register */ +#define TMS570_GIOD_DOUT_OFFSET 0x009c /* GIOD Data Output Register */ +#define TMS570_GIOD_DSET_OFFSET 0x00a0 /* GIOD Data Set Register */ +#define TMS570_GIOD_DCLR_OFFSET 0x00a4 /* GIOD Data Clear Register */ +#define TMS570_GIOD_PDR_OFFSET 0x00a8 /* GIOD Open Drain Register */ +#define TMS570_GIOD_PULDIS_OFFSET 0x00ac /* GIOD Pull Disable Register */ +#define TMS570_GIOD_PSL_OFFSET 0x00b0 /* GIOD Pull Select Register */ + +#define TMS570_GIOE_DIR_OFFSET 0x00b4 /* GIOE Data Direction Register */ +#define TMS570_GIOE_DIN_OFFSET 0x00b8 /* GIOE Data Input Register */ +#define TMS570_GIOE_DOUT_OFFSET 0x00bc /* GIOE Data Output Register */ +#define TMS570_GIOE_DSET_OFFSET 0x00c0 /* GIOE Data Set Register */ +#define TMS570_GIOE_DCLR_OFFSET 0x00c4 /* GIOE Data Clear Register */ +#define TMS570_GIOE_PDR_OFFSET 0x00c8 /* GIOE Open Drain Register */ +#define TMS570_GIOE_PULDIS_OFFSET 0x00cc /* GIOE Pull Disable Register */ +#define TMS570_GIOE_PSL_OFFSET 0x00d0 /* GIOE Pull Select Register */ + +#define TMS570_GIOF_DIR_OFFSET 0x00d4 /* GIOF Data Direction Register */ +#define TMS570_GIOF_DIN_OFFSET 0x00d8 /* GIOF Data Input Register */ +#define TMS570_GIOF_DOUT_OFFSET 0x00dc /* GIOF Data Output Register */ +#define TMS570_GIOF_DSET_OFFSET 0x00e0 /* GIOF Data Set Register */ +#define TMS570_GIOF_DCLR_OFFSET 0x00e4 /* GIOF Data Clear Register */ +#define TMS570_GIOF_PDR_OFFSET 0x00e8 /* GIOF Open Drain Register */ +#define TMS570_GIOF_PULDIS_OFFSET 0x00ec /* GIOF Pull Disable Register */ +#define TMS570_GIOF_PSL_OFFSET 0x00f0 /* GIOF Pull Select Register */ + +#define TMS570_GIOG_DIR_OFFSET 0x00f4 /* GIOG Data Direction Register */ +#define TMS570_GIOG_DIN_OFFSET 0x00f8 /* GIOG Data Input Register */ +#define TMS570_GIOG_DOUT_OFFSET 0x00fc /* GIOG Data Output Register */ +#define TMS570_GIOG_DSET_OFFSET 0x0100 /* GIOG Data Set Register */ +#define TMS570_GIOG_DCLR_OFFSET 0x0104 /* GIOG Data Clear Register */ +#define TMS570_GIOG_PDR_OFFSET 0x0108 /* GIOG Open Drain Register */ +#define TMS570_GIOG_PULDIS_OFFSET 0x010c /* GIOG Pull Disable Register */ +#define TMS570_GIOG_PSL_OFFSET 0x0110 /* GIOG Pull Select Register */ + +#define TMS570_GIOH_DIR_OFFSET 0x0114 /* GIOH Data Direction Register */ +#define TMS570_GIOH_DIN_OFFSET 0x0118 /* GIOH Data Input Register */ +#define TMS570_GIOH_DOUT_OFFSET 0x011c /* GIOH Data Output Register */ +#define TMS570_GIOH_DSET_OFFSET 0x0120 /* GIOH Data Set Register */ +#define TMS570_GIOH_DCLR_OFFSET 0x0124 /* GIOH Data Clear Register */ +#define TMS570_GIOH_PDR_OFFSET 0x0128 /* GIOH Open Drain Register */ +#define TMS570_GIOH_PULDIS_OFFSET 0x012c /* GIOH Pull Disable Register */ +#define TMS570_GIOH_PSL_OFFSET 0x0130 /* GIOH Pull Select Register */ + +/* Register Addresses *******************************************************************************/ + +#define TMS570_GIO_GCR0 (TMS570_GIO_BASE+TMS570_GIO_GCR0_OFFSET) +#define TMS570_GIO_INTDET (TMS570_GIO_BASE+TMS570_GIO_INTDET_OFFSET) +#define TMS570_GIO_POL (TMS570_GIO_BASE+TMS570_GIO_POL_OFFSET) +#define TMS570_GIO_ENASET (TMS570_GIO_BASE+TMS570_GIO_ENASET_OFFSET) +#define TMS570_GIO_ENACLR (TMS570_GIO_BASE+TMS570_GIO_ENACLR_OFFSET) +#define TMS570_GIO_LVLSET (TMS570_GIO_BASE+TMS570_GIO_LVLSET_OFFSET) +#define TMS570_GIO_LVLCLR (TMS570_GIO_BASE+TMS570_GIO_LVLCLR_OFFSET) +#define TMS570_GIO_FLG (TMS570_GIO_BASE+TMS570_GIO_FLG_OFFSET) +#define TMS570_GIO_OFF1 (TMS570_GIO_BASE+TMS570_GIO_OFF1_OFFSET) +#define TMS570_GIO_OFF2 (TMS570_GIO_BASE+TMS570_GIO_OFF2_OFFSET) +#define TMS570_GIO_EMU1 (TMS570_GIO_BASE+TMS570_GIO_EMU1_OFFSET) +#define TMS570_GIO_EMU2 (TMS570_GIO_BASE+TMS570_GIO_EMU2_OFFSET) + +#define TMS570_GIO(n) (TMS570_GIO_BASE+TMS570_GIO_OFFSET(n)) +#define TMS570_GIO_DIR(n) (TMS570_GIO(n)+TMS570_GIO_DIR_OFFSET) +#define TMS570_GIO_DIN(n) (TMS570_GIO(n)+TMS570_GIO_DIN_OFFSET) +#define TMS570_GIO_DOUT(n) (TMS570_GIO(n)+TMS570_GIO_DOUT_OFFSET) +#define TMS570_GIO_DSET(n) (TMS570_GIO(n)+TMS570_GIO_DSET_OFFSET) +#define TMS570_GIO_DCLR(n) (TMS570_GIO(n)+TMS570_GIO_DCLR_OFFSET) +#define TMS570_GIO_PDR(n) (TMS570_GIO(n)+TMS570_GIO_PDR_OFFSET) +#define TMS570_GIO_PULDIS(n) (TMS570_GIO(n)+TMS570_GIO_PULDIS_OFFSET) +#define TMS570_GIO_PSL(n) (TMS570_GIO(n)+TMS570_GIO_PSL_OFFSET) + +#define TMS570_GIOA_DIR (TMS570_GIO_BASE+TMS570_GIOA_DIR_OFFSET) +#define TMS570_GIOA_DIN (TMS570_GIO_BASE+TMS570_GIOA_DIN_OFFSET) +#define TMS570_GIOA_DOUT (TMS570_GIO_BASE+TMS570_GIOA_DOUT_OFFSET) +#define TMS570_GIOA_DSET (TMS570_GIO_BASE+TMS570_GIOA_DSET_OFFSET) +#define TMS570_GIOA_DCLR (TMS570_GIO_BASE+TMS570_GIOA_DCLR_OFFSET) +#define TMS570_GIOA_PDR (TMS570_GIO_BASE+TMS570_GIOA_PDR_OFFSET) +#define TMS570_GIOA_PULDIS (TMS570_GIO_BASE+TMS570_GIOA_PULDIS_OFFSET) +#define TMS570_GIOA_PSL (TMS570_GIO_BASE+TMS570_GIOA_PSL_OFFSET) + +#define TMS570_GIOB_DIR (TMS570_GIO_BASE+TMS570_GIOB_DIR_OFFSET) +#define TMS570_GIOB_DIN (TMS570_GIO_BASE+TMS570_GIOB_DIN_OFFSET) +#define TMS570_GIOB_DOUT (TMS570_GIO_BASE+TMS570_GIOB_DOUT_OFFSET) +#define TMS570_GIOB_DSET (TMS570_GIO_BASE+TMS570_GIOB_DSET_OFFSET) +#define TMS570_GIOB_DCLR (TMS570_GIO_BASE+TMS570_GIOB_DCLR_OFFSET) +#define TMS570_GIOB_PDR (TMS570_GIO_BASE+TMS570_GIOB_PDR_OFFSET) +#define TMS570_GIOB_PULDIS (TMS570_GIO_BASE+TMS570_GIOB_PULDIS_OFFSET) +#define TMS570_GIOB_PSL (TMS570_GIO_BASE+TMS570_GIOB_PSL_OFFSET) + +#define TMS570_GIOC_DIR (TMS570_GIO_BASE+TMS570_GIOC_DIR_OFFSET) +#define TMS570_GIOC_DIN (TMS570_GIO_BASE+TMS570_GIOC_DIN_OFFSET) +#define TMS570_GIOC_DOUT (TMS570_GIO_BASE+TMS570_GIOC_DOUT_OFFSET) +#define TMS570_GIOC_DSET (TMS570_GIO_BASE+TMS570_GIOC_DSET_OFFSET) +#define TMS570_GIOC_DCLR (TMS570_GIO_BASE+TMS570_GIOC_DCLR_OFFSET) +#define TMS570_GIOC_PDR (TMS570_GIO_BASE+TMS570_GIOC_PDR_OFFSET) +#define TMS570_GIOC_PULDIS (TMS570_GIO_BASE+TMS570_GIOC_PULDIS_OFFSET) +#define TMS570_GIOC_PSL (TMS570_GIO_BASE+TMS570_GIOC_PSL_OFFSET) + +#define TMS570_GIOD_DIR (TMS570_GIO_BASE+TMS570_GIOD_DIR_OFFSET) +#define TMS570_GIOD_DIN (TMS570_GIO_BASE+TMS570_GIOD_DIN_OFFSET) +#define TMS570_GIOD_DOUT (TMS570_GIO_BASE+TMS570_GIOD_DOUT_OFFSET) +#define TMS570_GIOD_DSET (TMS570_GIO_BASE+TMS570_GIOD_DSET_OFFSET) +#define TMS570_GIOD_DCLR (TMS570_GIO_BASE+TMS570_GIOD_DCLR_OFFSET) +#define TMS570_GIOD_PDR (TMS570_GIO_BASE+TMS570_GIOD_PDR_OFFSET) +#define TMS570_GIOD_PULDIS (TMS570_GIO_BASE+TMS570_GIOD_PULDIS_OFFSET) +#define TMS570_GIOD_PSL (TMS570_GIO_BASE+TMS570_GIOD_PSL_OFFSET) + +#define TMS570_GIOE_DIR (TMS570_GIO_BASE+TMS570_GIOE_DIR_OFFSET) +#define TMS570_GIOE_DIN (TMS570_GIO_BASE+TMS570_GIOE_DIN_OFFSET) +#define TMS570_GIOE_DOUT (TMS570_GIO_BASE+TMS570_GIOE_DOUT_OFFSET) +#define TMS570_GIOE_DSET (TMS570_GIO_BASE+TMS570_GIOE_DSET_OFFSET) +#define TMS570_GIOE_DCLR (TMS570_GIO_BASE+TMS570_GIOE_DCLR_OFFSET) +#define TMS570_GIOE_PDR (TMS570_GIO_BASE+TMS570_GIOE_PDR_OFFSET) +#define TMS570_GIOE_PULDIS (TMS570_GIO_BASE+TMS570_GIOE_PULDIS_OFFSET) +#define TMS570_GIOE_PSL (TMS570_GIO_BASE+TMS570_GIOE_PSL_OFFSET) + +#define TMS570_GIOF_DIR (TMS570_GIO_BASE+TMS570_GIOF_DIR_OFFSET) +#define TMS570_GIOF_DIN (TMS570_GIO_BASE+TMS570_GIOF_DIN_OFFSET) +#define TMS570_GIOF_DOUT (TMS570_GIO_BASE+TMS570_GIOF_DOUT_OFFSET) +#define TMS570_GIOF_DSET (TMS570_GIO_BASE+TMS570_GIOF_DSET_OFFSET) +#define TMS570_GIOF_DCLR (TMS570_GIO_BASE+TMS570_GIOF_DCLR_OFFSET) +#define TMS570_GIOF_PDR (TMS570_GIO_BASE+TMS570_GIOF_PDR_OFFSET) +#define TMS570_GIOF_PULDIS (TMS570_GIO_BASE+TMS570_GIOF_PULDIS_OFFSET) +#define TMS570_GIOF_PSL (TMS570_GIO_BASE+TMS570_GIOF_PSL_OFFSET) + +#define TMS570_GIOG_DIR (TMS570_GIO_BASE+TMS570_GIOG_DIR_OFFSET) +#define TMS570_GIOG_DIN (TMS570_GIO_BASE+TMS570_GIOG_DIN_OFFSET) +#define TMS570_GIOG_DOUT (TMS570_GIO_BASE+TMS570_GIOG_DOUT_OFFSET) +#define TMS570_GIOG_DSET (TMS570_GIO_BASE+TMS570_GIOG_DSET_OFFSET) +#define TMS570_GIOG_DCLR (TMS570_GIO_BASE+TMS570_GIOG_DCLR_OFFSET) +#define TMS570_GIOG_PDR (TMS570_GIO_BASE+TMS570_GIOG_PDR_OFFSET) +#define TMS570_GIOG_PULDIS (TMS570_GIO_BASE+TMS570_GIOG_PULDIS_OFFSET) +#define TMS570_GIOG_PSL (TMS570_GIO_BASE+TMS570_GIOG_PSL_OFFSET) + +#define TMS570_GIOH_DIR (TMS570_GIO_BASE+TMS570_GIOH_DIR_OFFSET) +#define TMS570_GIOH_DIN (TMS570_GIO_BASE+TMS570_GIOH_DIN_OFFSET) +#define TMS570_GIOH_DOUT (TMS570_GIO_BASE+TMS570_GIOH_DOUT_OFFSET) +#define TMS570_GIOH_DSET (TMS570_GIO_BASE+TMS570_GIOH_DSET_OFFSET) +#define TMS570_GIOH_DCLR (TMS570_GIO_BASE+TMS570_GIOH_DCLR_OFFSET) +#define TMS570_GIOH_PDR (TMS570_GIO_BASE+TMS570_GIOH_PDR_OFFSET) +#define TMS570_GIOH_PULDIS (TMS570_GIO_BASE+TMS570_GIOH_PULDIS_OFFSET) +#define TMS570_GIOH_PSL (TMS570_GIO_BASE+TMS570_GIOH_PSL_OFFSET) + +/* Register Bit-Field Definitions *******************************************************************/ + +/* GIO Global Control Register */ +#define GIO_GCR0_ +/* GIO Interrupt Detect Register */ +#define GIO_INTDET_ +/* GIO Interrupt Polarity Register */ +#define GIO_POL_ +/* GIO Interrupt Enable Set Register */ +#define GIO_ENASET_ +/* GIO Interrupt Enable Clear Register */ +#define GIO_ENACLR_ +/* GIO Interrupt Priority Set Register */ +#define GIO_LVLSET_ +/* GIO Interrupt Priority Clear Register */ +#define GIO_LVLCLR_ +/* GIO Interrupt Flag Register */ +#define GIO_FLG_ +/* GIO Offset 1 Register */ +#define GIO_OFF1_ +/* GIO Offset 2 Register */ +#define GIO_OFF2_ +/* GIO Emulation 1 Register */ +#define GIO_EMU1_ +/* GIO Emulation 2 Register */ +#define GIO_EMU2_ + +/* GIO Data Direction Register */ +#define GIO_DIR_ +/* GIO Data Input Register */ +#define GIO_DIN_ +/* GIO Data Output Register */ +#define GIO_DOUT_ +/* GIO Data Set Register */ +#define GIO_DSET_ +/* GIO Data Clear Register */ +#define GIO_DCLR_ +/* GIO Open Drain Register */ +#define GIO_PDR_ +/* GIO Pull Disable Register */ +#define GIO_PULDIS_ +/* GIO Pull Select Register */ +#define GIO_PSL_ + +#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H */ diff --git a/arch/arm/src/tms570/chip/tms570_sci.h b/arch/arm/src/tms570/chip/tms570_sci.h index 1cbfdb77185..71c4857c68b 100644 --- a/arch/arm/src/tms570/chip/tms570_sci.h +++ b/arch/arm/src/tms570/chip/tms570_sci.h @@ -260,7 +260,7 @@ #define SCI_FLR_BRKDT (1 << 0) /* Bit 0: Break detect flag */ #define SCI_FLR_WAKEUP (1 << 1) /* Bit 1: Wake-up flag */ #define SCI_FLR_IDLE (1 << 2) /* Bit 2: SCI receiver in idle state */ -#define SCI_FLR_BUSY (1 << 3) /* Bit 3: Bus busy flag */ +#define SCI_FLR_BUSY (1 << 3) /* Bit 3: Bus busy flag */ #define SCI_FLR_TIMEOUT (1 << 4) /* Bit 4: Timeout flag */ #define SCI_FLR_TOAWUS (1 << 6) /* Bit 6: Timeout after wakeup signal flag */ #define SCI_FLR_TOA3WUS (1 << 7) /* Bit 7: Timeout after 2 Wakeup signls flag */ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index cd789c48a9e..3130ed122b8 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -319,7 +319,7 @@ void arm_boot(void) /* Perform board-specific initialization, This must include: * * - Initialization of board-specific memory resources (e.g., SDRAM) - * - Configuration of board specific resources (GPIOs, LEDs, etc). + * - Configuration of board specific resources (GIOs, LEDs, etc). * * NOTE: We must use caution prior to this point to make sure that * the logic does not access any global variables that might lie diff --git a/arch/arm/src/tms570/tms570_boot.h b/arch/arm/src/tms570/tms570_boot.h index 55bc565626a..ae3611144ee 100644 --- a/arch/arm/src/tms570/tms570_boot.h +++ b/arch/arm/src/tms570/tms570_boot.h @@ -117,7 +117,7 @@ void tms570_lowsetup(void); * This function must perform low level initialization including * * - Initialization of board-specific memory resources (e.g., SDRAM) - * - Configuration of board specific resources (GPIOs, LEDs, etc). + * - Configuration of board specific resources (GIOs, LEDs, etc). * - Setup of the console SCI. This SCI done early so that the serial console * is available for debugging very early in the boot sequence. * diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index f5c342991ae..847eda87253 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -173,12 +173,12 @@ void up_irqinitialize(void) #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS -#ifdef CONFIG_TMS570_GPIO_IRQ +#ifdef CONFIG_TMS570_GIO_IRQ /* Initialize logic to support a second level of interrupt decoding for - * GPIO pins. + * GIO pins. */ - tms570_gpioirqinitialize(); + tms570_gioirqinitialize(); #endif /* And finally, enable interrupts */ From 0a936e7fa723c36031496b7894073069072b1878 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Dec 2015 11:28:01 -0600 Subject: [PATCH 03/22] TMS570: More GIO definitions --- arch/arm/src/tms570/chip/tms570_gio.h | 189 +++++++++++---- arch/arm/src/tms570/tms570_gio.h | 325 ++++++++++++++++++++++++++ 2 files changed, 475 insertions(+), 39 deletions(-) create mode 100644 arch/arm/src/tms570/tms570_gio.h diff --git a/arch/arm/src/tms570/chip/tms570_gio.h b/arch/arm/src/tms570/chip/tms570_gio.h index d2ccf7d437e..23ba434d8a8 100644 --- a/arch/arm/src/tms570/chip/tms570_gio.h +++ b/arch/arm/src/tms570/chip/tms570_gio.h @@ -259,45 +259,156 @@ /* Register Bit-Field Definitions *******************************************************************/ /* GIO Global Control Register */ -#define GIO_GCR0_ -/* GIO Interrupt Detect Register */ -#define GIO_INTDET_ -/* GIO Interrupt Polarity Register */ -#define GIO_POL_ -/* GIO Interrupt Enable Set Register */ -#define GIO_ENASET_ -/* GIO Interrupt Enable Clear Register */ -#define GIO_ENACLR_ -/* GIO Interrupt Priority Set Register */ -#define GIO_LVLSET_ -/* GIO Interrupt Priority Clear Register */ -#define GIO_LVLCLR_ -/* GIO Interrupt Flag Register */ -#define GIO_FLG_ -/* GIO Offset 1 Register */ -#define GIO_OFF1_ -/* GIO Offset 2 Register */ -#define GIO_OFF2_ -/* GIO Emulation 1 Register */ -#define GIO_EMU1_ -/* GIO Emulation 2 Register */ -#define GIO_EMU2_ -/* GIO Data Direction Register */ -#define GIO_DIR_ -/* GIO Data Input Register */ -#define GIO_DIN_ -/* GIO Data Output Register */ -#define GIO_DOUT_ -/* GIO Data Set Register */ -#define GIO_DSET_ -/* GIO Data Clear Register */ -#define GIO_DCLR_ -/* GIO Open Drain Register */ -#define GIO_PDR_ -/* GIO Pull Disable Register */ -#define GIO_PULDIS_ -/* GIO Pull Select Register */ -#define GIO_PSL_ +#define GIO_GCR0_RESET (1 << 0) /* Bit 0: GIO reset */ + +/* GIO Interrupt Detect Register */ + +#define GIO_INTDET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt detection select for pins GIOA[7:0] */ +#define GIO_INTDET_GIOA_MASK (0xff << GIO_INTDET_GIOA_SHIFT) +# define GIO_INTDET_GIOA_PIN(n) (1 << (GIO_INTDET_GIOA_SHIFT + (n))) +#define GIO_INTDET_GIOB_SHIFT (8) /* Bits 8-15: Interrupt detection select for pins GIOB[7:0] */ +#define GIO_INTDET_GIOB_MASK (0xff << GIO_INTDET_GIOB_SHIFT) +# define GIO_INTDET_GIOB_PIN(n) (1 << (GIO_INTDET_GIOB_SHIFT + (n))) +#define GIO_INTDET_GIOC_SHIFT (16) /* Bits 16-23: Interrupt detection select for pins GIOC[7:0] */ +#define GIO_INTDET_GIOC_MASK (0xff << GIO_INTDET_GIOC_SHIFT) +# define GIO_INTDET_GIOC_PIN(n) (1 << (GIO_INTDET_GIOC_SHIFT + (n))) +#define GIO_INTDET_GIOD_SHIFT (24) /* Bits 24-31: Interrupt detection select for pins GIOD[7:0] */ +#define GIO_INTDET_GIOD_MASK (0xff << GIO_INTDET_GIOD_SHIFT) +# define GIO_INTDET_GIOD_PIN(n) (1 << (GIO_INTDET_GIOD_SHIFT + (n))) + +/* GIO Interrupt Polarity Register */ + +#define GIO_POL_GIOA_SHIFT (0) /* Bits 0-7: Interrupt polarity select for pins GIOA[7:0] */ +#define GIO_POL_GIOA_MASK (0xff << GIO_POL_GIOA_SHIFT) +# define GIO_POL_GIOA_PIN(n) (1 << (GIO_POL_GIOA_SHIFT + (n))) +#define GIO_POL_GIOB_SHIFT (8) /* Bits 8-15: Interrupt polarity select for pins GIOB[7:0] */ +#define GIO_POL_GIOB_MASK (0xff << GIO_POL_GIOB_SHIFT) +# define GIO_POL_GIOB_PIN(n) (1 << (GIO_POL_GIOB_SHIFT + (n))) +#define GIO_POL_GIOC_SHIFT (16) /* Bits 16-23: Interrupt polarity select for pins GIOC[7:0] */ +#define GIO_POL_GIOC_MASK (0xff << GIO_POL_GIOC_SHIFT) +# define GIO_POL_GIOC_PIN(n) (1 << (GIO_POL_GIOC_SHIFT + (n))) +#define GIO_POL_GIOD_SHIFT (24) /* Bits 24-31: Interrupt polarity select for pins GIOD[7:0] */ +#define GIO_POL_GIOD_MASK (0xff << GIO_POL_GIOD_SHIFT) +# define GIO_POL_GIOD_PIN(n) (1 << (GIO_POL_GIOD_SHIFT + (n))) + +/* GIO Interrupt Enable Set Register */ + +#define GIO_ENASET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt enable for pins GIOA[7:0] */ +#define GIO_ENASET_GIOA_MASK (0xff << GIO_ENASET_GIOA_SHIFT) +# define GIO_ENASET_GIOA_PIN(n) (1 << (GIO_ENASET_GIOA_SHIFT + (n))) +#define GIO_ENASET_GIOB_SHIFT (8) /* Bits 8-15: Interrupt enable for pins GIOB[7:0] */ +#define GIO_ENASET_GIOB_MASK (0xff << GIO_ENASET_GIOB_SHIFT) +# define GIO_ENASET_GIOB_PIN(n) (1 << (GIO_ENASET_GIOB_SHIFT + (n))) +#define GIO_ENASET_GIOC_SHIFT (16) /* Bits 16-23: Interrupt enable for pins GIOC[7:0] */ +#define GIO_ENASET_GIOC_MASK (0xff << GIO_ENASET_GIOC_SHIFT) +# define GIO_ENASET_GIOC_PIN(n) (1 << (GIO_ENASET_GIOC_SHIFT + (n))) +#define GIO_ENASET_GIOD_SHIFT (24) /* Bits 24-31: Interrupt enable for pins GIOD[7:0] */ +#define GIO_ENASET_GIOD_MASK (0xff << GIO_ENASET_GIOD_SHIFT) +# define GIO_ENASET_GIOD_PIN(n) (1 << (GIO_ENASET_GIOD_SHIFT + (n))) + +/* GIO Interrupt Enable Clear Register */ + +#define GIO_ENACLR_GIOA_SHIFT (0) /* Bits 0-7: Interrupt disable for pins GIOA[7:0] */ +#define GIO_ENACLR_GIOA_MASK (0xff << GIO_ENACLR_GIOA_SHIFT) +# define GIO_ENACLR_GIOA_PIN(n) (1 << (GIO_ENACLR_GIOA_SHIFT + (n))) +#define GIO_ENACLR_GIOB_SHIFT (8) /* Bits 8-15: Interrupt disable for pins GIOB[7:0] */ +#define GIO_ENACLR_GIOB_MASK (0xff << GIO_ENACLR_GIOB_SHIFT) +# define GIO_ENACLR_GIOB_PIN(n) (1 << (GIO_ENACLR_GIOB_SHIFT + (n))) +#define GIO_ENACLR_GIOC_SHIFT (16) /* Bits 16-23: Interrupt disable for pins GIOC[7:0] */ +#define GIO_ENACLR_GIOC_MASK (0xff << GIO_ENACLR_GIOC_SHIFT) +# define GIO_ENACLR_GIOC_PIN(n) (1 << (GIO_ENACLR_GIOC_SHIFT + (n))) +#define GIO_ENACLR_GIOD_SHIFT (24) /* Bits 24-31: Interrupt disable for pins GIOD[7:0] */ +#define GIO_ENACLR_GIOD_MASK (0xff << GIO_ENACLR_GIOD_SHIFT) +# define GIO_ENACLR_GIOD_PIN(n) (1 << (GIO_ENACLR_GIOD_SHIFT + (n))) + +/* GIO Interrupt Priority Set Register */ + +#define GIO_LVLSET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt high level select for pins GIOA[7:0] */ +#define GIO_LVLSET_GIOA_MASK (0xff << GIO_LVLSET_GIOA_SHIFT) +# define GIO_LVLSET_GIOA_PIN(n) (1 << (GIO_LVLSET_GIOA_SHIFT + (n))) +#define GIO_LVLSET_GIOB_SHIFT (8) /* Bits 8-15: Interrupt high level select for pins GIOB[7:0] */ +#define GIO_LVLSET_GIOB_MASK (0xff << GIO_LVLSET_GIOB_SHIFT) +# define GIO_LVLSET_GIOB_PIN(n) (1 << (GIO_LVLSET_GIOB_SHIFT + (n))) +#define GIO_LVLSET_GIOC_SHIFT (16) /* Bits 16-23: Interrupt high level select for pins GIOC[7:0] */ +#define GIO_LVLSET_GIOC_MASK (0xff << GIO_LVLSET_GIOC_SHIFT) +# define GIO_LVLSET_GIOC_PIN(n) (1 << (GIO_LVLSET_GIOC_SHIFT + (n))) +#define GIO_LVLSET_GIOD_SHIFT (24) /* Bits 24-31: Interrupt high level select for pins GIOD[7:0] */ +#define GIO_LVLSET_GIOD_MASK (0xff << GIO_LVLSET_GIOD_SHIFT) +# define GIO_LVLSET_GIOD_PIN(n) (1 << (GIO_LVLSET_GIOD_SHIFT + (n))) + +/* GIO Interrupt Priority Clear Register */ + +#define GIO_LVLCLR_GIOA_SHIFT (0) /* Bits 0-7: Interrupt low level select for pins GIOA[7:0] */ +#define GIO_LVLCLR_GIOA_MASK (0xff << GIO_LVLCLR_GIOA_SHIFT) +# define GIO_LVLCLR_GIOA_PIN(n) (1 << (GIO_LVLCLR_GIOA_SHIFT + (n))) +#define GIO_LVLCLR_GIOB_SHIFT (8) /* Bits 8-15: Interrupt low level select for pins GIOB[7:0] */ +#define GIO_LVLCLR_GIOB_MASK (0xff << GIO_LVLCLR_GIOB_SHIFT) +# define GIO_LVLCLR_GIOB_PIN(n) (1 << (GIO_LVLCLR_GIOB_SHIFT + (n))) +#define GIO_LVLCLR_GIOC_SHIFT (16) /* Bits 16-23: Interrupt low level select for pins GIOC[7:0] */ +#define GIO_LVLCLR_GIOC_MASK (0xff << GIO_LVLCLR_GIOC_SHIFT) +# define GIO_LVLCLR_GIOC_PIN(n) (1 << (GIO_LVLCLR_GIOC_SHIFT + (n))) +#define GIO_LVLCLR_GIOD_SHIFT (24) /* Bits 24-31: Interrupt low level select for pins GIOD[7:0] */ +#define GIO_LVLCLR_GIOD_MASK (0xff << GIO_LVLCLR_GIOD_SHIFT) +# define GIO_LVLCLR_GIOD_PIN(n) (1 << (GIO_LVLCLR_GIOD_SHIFT + (n))) + +/* GIO Interrupt Flag Register */ + +#define GIO_FLG_GIOA_SHIFT (0) /* Bits 0-7: Interrupt flag for pins GIOA[7:0] */ +#define GIO_FLG_GIOA_MASK (0xff << GIO_FLG_GIOA_SHIFT) +# define GIO_FLG_GIOA_PIN(n) (1 << (GIO_FLG_GIOA_SHIFT + (n))) +#define GIO_FLG_GIOB_SHIFT (8) /* Bits 8-15: Interrupt flag for pins GIOB[7:0] */ +#define GIO_FLG_GIOB_MASK (0xff << GIO_FLG_GIOB_SHIFT) +# define GIO_FLG_GIOB_PIN(n) (1 << (GIO_FLG_GIOB_SHIFT + (n))) +#define GIO_FLG_GIOC_SHIFT (16) /* Bits 16-23: Interrupt flag for pins GIOC[7:0] */ +#define GIO_FLG_GIOC_MASK (0xff << GIO_FLG_GIOC_SHIFT) +# define GIO_FLG_GIOC_PIN(n) (1 << (GIO_FLG_GIOC_SHIFT + (n))) +#define GIO_FLG_GIOD_SHIFT (24) /* Bits 24-31: Interrupt flag for pins GIOD[7:0] */ +#define GIO_FLG_GIOD_MASK (0xff << GIO_FLG_GIOD_SHIFT) +# define GIO_FLG_GIOD_PIN(n) (1 << (GIO_FLG_GIOD_SHIFT + (n))) + +/* GIO Offset 1/2 Register and GIO Emulation 1/2 Register */ + +#define GIO_OFF_MASK (0x3f) /* Bits 0-5: GIO offset */ +# define GIO_OFF_NONE (0x00) /* No interrupt pending */ +# define GIO_OFF_GIOA0 (0x01) /* GIOA0 interrupt pending */ +# define GIO_OFF_GIOA1 (0x02) /* GIOA1 interrupt pending */ +# define GIO_OFF_GIOA2 (0x03) /* GIOA2 interrupt pending */ +# define GIO_OFF_GIOA3 (0x04) /* GIOA3 interrupt pending */ +# define GIO_OFF_GIOA4 (0x05) /* GIOA4 interrupt pending */ +# define GIO_OFF_GIOA5 (0x06) /* GIOA5 interrupt pending */ +# define GIO_OFF_GIOA6 (0x07) /* GIOA6 interrupt pending */ +# define GIO_OFF_GIOA7 (0x08) /* GIOA7 interrupt pending */ +# define GIO_OFF_GIOB0 (0x09) /* GIOB0 interrupt pending */ +# define GIO_OFF_GIOB1 (0x0a) /* GIOB1 interrupt pending */ +# define GIO_OFF_GIOB2 (0x0b) /* GIOB2 interrupt pending */ +# define GIO_OFF_GIOB3 (0x0c) /* GIOB3 interrupt pending */ +# define GIO_OFF_GIOB4 (0x0d) /* GIOB4 interrupt pending */ +# define GIO_OFF_GIOB5 (0x0e) /* GIOB5 interrupt pending */ +# define GIO_OFF_GIOB6 (0x0f) /* GIOB6 interrupt pending */ +# define GIO_OFF_GIOB7 (0x10) /* GIOB7 interrupt pending */ +# define GIO_OFF_GIOC0 (0x11) /* GIOC0 interrupt pending */ +# define GIO_OFF_GIOC1 (0x12) /* GIOC1 interrupt pending */ +# define GIO_OFF_GIOC2 (0x13) /* GIOC2 interrupt pending */ +# define GIO_OFF_GIOC3 (0x14) /* GIOC3 interrupt pending */ +# define GIO_OFF_GIOC4 (0x15) /* GIOC4 interrupt pending */ +# define GIO_OFF_GIOC5 (0x16) /* GIOC5 interrupt pending */ +# define GIO_OFF_GIOC6 (0x17) /* GIOC6 interrupt pending */ +# define GIO_OFF_GIOC7 (0x18) /* GIOC7 interrupt pending */ +# define GIO_OFF_GIOD0 (0x19) /* GIOD0 interrupt pending */ +# define GIO_OFF_GIOD1 (0x1a) /* GIOD1 interrupt pending */ +# define GIO_OFF_GIOD2 (0x1b) /* GIOD2 interrupt pending */ +# define GIO_OFF_GIOD3 (0x1c) /* GIOD3 interrupt pending */ +# define GIO_OFF_GIOD4 (0x1d) /* GIOD4 interrupt pending */ +# define GIO_OFF_GIOD5 (0x1e) /* GIOD5 interrupt pending */ +# define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */ +# define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */ + +/* GIO Data Direction Register, GIO Data Input Register, GIO Data Output Register, + * GIO Data Set Register, GIO Data Clear Register, GIO Open Drain Register, + * GIO Pull Disable Register, and GIO Pull Select Register + */ + +#define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */ #endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H */ diff --git a/arch/arm/src/tms570/tms570_gio.h b/arch/arm/src/tms570/tms570_gio.h new file mode 100644 index 00000000000..dadb759363e --- /dev/null +++ b/arch/arm/src/tms570/tms570_gio.h @@ -0,0 +1,325 @@ +/************************************************************************************ + * arch/arm/src/tms570/tms570_gio.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_TMS570_GIO_H +#define __ARCH_ARM_SRC_TMS570_TMS570_GIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Bit-encoded input to tms570_configgio() ********************************************/ + +/* 32-bit Encoding: + * + * .... .... .... .... MCCC .IIV PPP. .BBB + */ + +/* Input/Output mode: + * + * .... .... .... .... M... .... .... .... + */ + +#define GIO_MODE_SHIFT (15) /* Bit 15: GIO mode */ +#define GIO_MODE_MASK (1 << GIO_MODE_SHIFT) +# define GIO_INPUT (0 << GIO_MODE_SHIFT) /* GIO Input */ +# define GIO_OUTPUT (1 << GIO_MODE_SHIFT) /* GIO Output */ + +/* These bits set the configuration of the pin: + * NOTE: No definitions for parallel capture mode + * + * .... .... .... .... .CCC .... .... .... + */ + +#define GIO_CFG_SHIFT (12) /* Bits 12-14: GIO configuration bits */ +#define GIO_CFG_MASK (7 << GIO_CFG_SHIFT) +# define GIO_CFG_DEFAULT (0 << GIO_CFG_SHIFT) /* Default, no attribute */ +# define GIO_CFG_PULLUP (1 << GIO_CFG_SHIFT) /* Bit 16: Internal pull-up */ +# define GIO_CFG_PULLDOWN (2 << GIO_CFG_SHIFT) /* Bit 17: Internal pull-down */ +# define GIO_CFG_OPENDRAIN (4 << GIO_CFG_SHIFT) /* Bit 19: Open drain */ + +/* Interrupt modes: + * + * .... .... .... .... .... .II. .... .... + */ + +#define GIO_INT_SHIFT (9) /* Bits 9-10: GIO interrupt bits */ +#define GIO_INT_MASK (3 << GIO_INT_SHIFT) +# define GIO_INT_NONE (0 << GIO_INT_SHIFT) +# define GIO_INT_RISING (1 << GIO_INT_SHIFT) +# define GIO_INT_FALLING (2 << GIO_INT_SHIFT) +# define GIO_INT_BOTHEDGES (3 << GIO_INT_SHIFT) + +/* If the pin is an GIO output, then this identifies the initial output value: + * + * .... .... .... .... .... ...V .... .... + */ + +#define GIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */ +#define GIO_OUTPUT_CLEAR (0) + +/* This identifies the GIO port: + * + * .... .... .... .... .... .... PPP. .... + */ + +#define GIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GIO_PORT_MASK (7 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOA (0 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOB (1 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOC (2 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOD (3 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOE (4 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOF (5 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOG (6 << GIO_PORT_SHIFT) +# define GIO_PORT_GIOH (7 << GIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * + * .... .... .... .... .... .... .... .BBB + */ + +#define GIO_PIN_SHIFT (0) /* Bits 0-2: GIO number: 0-7 */ +#define GIO_PIN_MASK (7 << GIO_PIN_SHIFT) +# define GIO_PIN0 (0 << GIO_PIN_SHIFT) +# define GIO_PIN1 (1 << GIO_PIN_SHIFT) +# define GIO_PIN2 (2 << GIO_PIN_SHIFT) +# define GIO_PIN3 (3 << GIO_PIN_SHIFT) +# define GIO_PIN4 (4 << GIO_PIN_SHIFT) +# define GIO_PIN5 (5 << GIO_PIN_SHIFT) +# define GIO_PIN6 (6 << GIO_PIN_SHIFT) +# define GIO_PIN7 (7 << GIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Must be big enough to hold the 32-bit encoding */ + +typedef uint16_t gio_pinset_t; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: tms570_gio_base + * + * Description: + * Return the base address of the GIO register set + * + ****************************************************************************/ + +static inline uintptr_t tms570_gio_base(gio_pinset_t cfgset) +{ + int port = (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT; + return TMS570_GIO_PORTBASE(n); +} + +/**************************************************************************** + * Name: tms570_gio_port + * + * Description: + * Return the GIO port number + * + ****************************************************************************/ + +static inline int tms570_gio_port(gio_pinset_t cfgset) +{ + return (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT; +} + +/**************************************************************************** + * Name: tms570_gio_pin + * + * Description: + * Return the GIO pin number + * + ****************************************************************************/ + +static inline int tms570_gio_pin(gio_pinset_t cfgset) +{ + return (cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT; +} + +/**************************************************************************** + * Name: tms570_gio_pinmask + * + * Description: + * Return the GIO pin bit maskt + * + ****************************************************************************/ + +static inline int tms570_gio_pinmask(gio_pinset_t cfgset) +{ + return 1 << ((cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT); +} + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: tms570_gioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GIO pins. + * + ************************************************************************************/ + +#ifdef CONFIG_TMS570_GIO_IRQ +void tms570_gioirqinitialize(void); +#else +# define tms570_gioirqinitialize() +#endif + +/************************************************************************************ + * Name: tms570_configgio + * + * Description: + * Configure a GIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int tms570_configgio(gio_pinset_t cfgset); + +/************************************************************************************ + * Name: tms570_giowrite + * + * Description: + * Write one or zero to the selected GIO pin + * + ************************************************************************************/ + +void tms570_giowrite(gio_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: tms570_gioread + * + * Description: + * Read one or zero from the selected GIO pin + * + ************************************************************************************/ + +bool tms570_gioread(gio_pinset_t pinset); + +/************************************************************************************ + * Name: tms570_gioirq + * + * Description: + * Configure an interrupt for the specified GIO pin. + * + ************************************************************************************/ + +#ifdef CONFIG_TMS570_GIO_IRQ +void tms570_gioirq(gio_pinset_t pinset); +#else +# define tms570_gioirq(pinset) +#endif + +/************************************************************************************ + * Name: tms570_gioirqenable + * + * Description: + * Enable the interrupt for specified GIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_TMS570_GIO_IRQ +void tms570_gioirqenable(int irq); +#else +# define tms570_gioirqenable(irq) +#endif + +/************************************************************************************ + * Name: tms570_gioirqdisable + * + * Description: + * Disable the interrupt for specified GIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_TMS570_GIO_IRQ +void tms570_gioirqdisable(int irq); +#else +# define tms570_gioirqdisable(irq) +#endif + +/************************************************************************************ + * Function: tms570_dumpgio + * + * Description: + * Dump all GIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GIO +int tms570_dumpgio(uint32_t pinset, const char *msg); +#else +# define tms570_dumpgio(p,m) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_TMS570_TMS570_GIO_H */ From f539d331c54e55dd26963ff0aeeb99f613cb2c95 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Dec 2015 11:30:08 -0600 Subject: [PATCH 04/22] TMS570: A few more GIO definitions --- arch/arm/src/tms570/chip/tms570_gio.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/tms570/chip/tms570_gio.h b/arch/arm/src/tms570/chip/tms570_gio.h index 23ba434d8a8..c179718bba5 100644 --- a/arch/arm/src/tms570/chip/tms570_gio.h +++ b/arch/arm/src/tms570/chip/tms570_gio.h @@ -174,15 +174,15 @@ #define TMS570_GIO_EMU1 (TMS570_GIO_BASE+TMS570_GIO_EMU1_OFFSET) #define TMS570_GIO_EMU2 (TMS570_GIO_BASE+TMS570_GIO_EMU2_OFFSET) -#define TMS570_GIO(n) (TMS570_GIO_BASE+TMS570_GIO_OFFSET(n)) -#define TMS570_GIO_DIR(n) (TMS570_GIO(n)+TMS570_GIO_DIR_OFFSET) -#define TMS570_GIO_DIN(n) (TMS570_GIO(n)+TMS570_GIO_DIN_OFFSET) -#define TMS570_GIO_DOUT(n) (TMS570_GIO(n)+TMS570_GIO_DOUT_OFFSET) -#define TMS570_GIO_DSET(n) (TMS570_GIO(n)+TMS570_GIO_DSET_OFFSET) -#define TMS570_GIO_DCLR(n) (TMS570_GIO(n)+TMS570_GIO_DCLR_OFFSET) -#define TMS570_GIO_PDR(n) (TMS570_GIO(n)+TMS570_GIO_PDR_OFFSET) -#define TMS570_GIO_PULDIS(n) (TMS570_GIO(n)+TMS570_GIO_PULDIS_OFFSET) -#define TMS570_GIO_PSL(n) (TMS570_GIO(n)+TMS570_GIO_PSL_OFFSET) +#define TMS570_GIO_PORTBASE(n) (TMS570_GIO_BASE+TMS570_GIO_OFFSET(n)) +#define TMS570_GIO_DIR(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_DIR_OFFSET) +#define TMS570_GIO_DIN(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_DIN_OFFSET) +#define TMS570_GIO_DOUT(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_DOUT_OFFSET) +#define TMS570_GIO_DSET(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_DSET_OFFSET) +#define TMS570_GIO_DCLR(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_DCLR_OFFSET) +#define TMS570_GIO_PDR(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_PDR_OFFSET) +#define TMS570_GIO_PULDIS(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_PULDIS_OFFSET) +#define TMS570_GIO_PSL(n) (TMS570_GIO_PORTBASE(n)+TMS570_GIO_PSL_OFFSET) #define TMS570_GIOA_DIR (TMS570_GIO_BASE+TMS570_GIOA_DIR_OFFSET) #define TMS570_GIOA_DIN (TMS570_GIO_BASE+TMS570_GIOA_DIN_OFFSET) From ccc691338319182f2185b96509d0cb5ec026a798 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Dec 2015 11:43:38 -0600 Subject: [PATCH 05/22] TMS570: Add definitions to support GIO second level interrupts --- arch/arm/include/tms570/irq.h | 6 +-- arch/arm/include/tms570/tms570ls04x03x_irq.h | 43 ++++++++++++++++++++ arch/arm/src/tms570/Kconfig | 5 +++ 3 files changed, 51 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/tms570/irq.h b/arch/arm/include/tms570/irq.h index 2820105100e..f83fad69def 100644 --- a/arch/arm/include/tms570/irq.h +++ b/arch/arm/include/tms570/irq.h @@ -76,11 +76,11 @@ # error "Unrecognized Hercules chip" #endif -/* Total number of IRQ numbers. Excluds the phantom vector. Zero corresponds to - * channel 0, vector 1. +/* Total number of IRQ numbers. Includes all channels plus GIO second-level interrupts + * (if enabled). Excluds the phantom vector. Zero corresponds to channel 0, vector 1. */ -#define NR_IRQS (TMS570_IRQ_NCHANNELS) +#define NR_IRQS (TMS570_IRQ_NCHANNELS + TMS570_NGIO_IRQS) /**************************************************************************************** * Public Types diff --git a/arch/arm/include/tms570/tms570ls04x03x_irq.h b/arch/arm/include/tms570/tms570ls04x03x_irq.h index 6e19a7bfaf2..b190dcfe48b 100644 --- a/arch/arm/include/tms570/tms570ls04x03x_irq.h +++ b/arch/arm/include/tms570/tms570ls04x03x_irq.h @@ -97,6 +97,49 @@ #define TMS570_REQ_PBIST 85 /* PBIST Done Interrupt */ #define TMS570_REQ_HWAGL 88 /* HWA_INT_REQ_L */ +#ifdef CONFIG_TMS570_GIO_IRQ +# define TMS570_IRQ_GIOA0 (TMS570_IRQ_NCHANNELS+1) +# define TMS570_IRQ_GIOA1 (TMS570_IRQ_NCHANNELS+2) +# define TMS570_IRQ_GIOA2 (TMS570_IRQ_NCHANNELS+3) +# define TMS570_IRQ_GIOA3 (TMS570_IRQ_NCHANNELS+4) +# define TMS570_IRQ_GIOA4 (TMS570_IRQ_NCHANNELS+5) +# define TMS570_IRQ_GIOA5 (TMS570_IRQ_NCHANNELS+6) +# define TMS570_IRQ_GIOA6 (TMS570_IRQ_NCHANNELS+7) +# define TMS570_IRQ_GIOA7 (TMS570_IRQ_NCHANNELS+8) + +# define TMS570_IRQ_GIOB0 (TMS570_IRQ_NCHANNELS+9) +# define TMS570_IRQ_GIOB1 (TMS570_IRQ_NCHANNELS+10) +# define TMS570_IRQ_GIOB2 (TMS570_IRQ_NCHANNELS+11) +# define TMS570_IRQ_GIOB3 (TMS570_IRQ_NCHANNELS+12) +# define TMS570_IRQ_GIOB4 (TMS570_IRQ_NCHANNELS+13) +# define TMS570_IRQ_GIOB5 (TMS570_IRQ_NCHANNELS+14) +# define TMS570_IRQ_GIOB6 (TMS570_IRQ_NCHANNELS+15) +# define TMS570_IRQ_GIOB7 (TMS570_IRQ_NCHANNELS+16) + +# define TMS570_IRQ_GIOC0 (TMS570_IRQ_NCHANNELS+17) +# define TMS570_IRQ_GIOC1 (TMS570_IRQ_NCHANNELS+18) +# define TMS570_IRQ_GIOC2 (TMS570_IRQ_NCHANNELS+19) +# define TMS570_IRQ_GIOC3 (TMS570_IRQ_NCHANNELS+20) +# define TMS570_IRQ_GIOC4 (TMS570_IRQ_NCHANNELS+21) +# define TMS570_IRQ_GIOC5 (TMS570_IRQ_NCHANNELS+22) +# define TMS570_IRQ_GIOC6 (TMS570_IRQ_NCHANNELS+23) +# define TMS570_IRQ_GIOC7 (TMS570_IRQ_NCHANNELS+24) + +# define TMS570_IRQ_GIOD0 (TMS570_IRQ_NCHANNELS+25) +# define TMS570_IRQ_GIOD1 (TMS570_IRQ_NCHANNELS+26) +# define TMS570_IRQ_GIOD2 (TMS570_IRQ_NCHANNELS+27) +# define TMS570_IRQ_GIOD3 (TMS570_IRQ_NCHANNELS+28) +# define TMS570_IRQ_GIOD4 (TMS570_IRQ_NCHANNELS+29) +# define TMS570_IRQ_GIOD5 (TMS570_IRQ_NCHANNELS+30) +# define TMS570_IRQ_GIOD6 (TMS570_IRQ_NCHANNELS+31) +# define TMS570_IRQ_GIOD7 (TMS570_IRQ_NCHANNELS+32) + +# define TMS570_NGIO_IRQS 32 +#else +# define TMS570_NGIO_IRQS 0 +#endif + + /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/arch/arm/src/tms570/Kconfig b/arch/arm/src/tms570/Kconfig index f69ee4181e9..81136d3e339 100644 --- a/arch/arm/src/tms570/Kconfig +++ b/arch/arm/src/tms570/Kconfig @@ -100,6 +100,11 @@ config TMS570_SCI2 endmenu # TMS570 Peripheral Support +config TMS570_GIO_IRQ + bool "GIO pin interrupts" + ---help--- + Build in support for interrupting GIO pins + config TMS570_SELFTEST bool "Power-on Selftest" default n From c58393cb4d87e9dc4942c788981ef13a1a0df790 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Dec 2015 13:44:49 -0600 Subject: [PATCH 06/22] TMS570: Add GIO drivrs and GIO interrupt support --- arch/arm/include/tms570/tms570ls04x03x_irq.h | 18 +- arch/arm/src/tms570/Make.defs | 8 +- arch/arm/src/tms570/chip/tms570_gio.h | 101 ++++-- arch/arm/src/tms570/tms570_boot.c | 5 + arch/arm/src/tms570/tms570_gio.c | 330 +++++++++++++++++++ arch/arm/src/tms570/tms570_gio.h | 40 ++- arch/arm/src/tms570/tms570_gioirq.c | 256 ++++++++++++++ arch/arm/src/tms570/tms570_irq.c | 2 +- 8 files changed, 702 insertions(+), 58 deletions(-) create mode 100644 arch/arm/src/tms570/tms570_gio.c create mode 100644 arch/arm/src/tms570/tms570_gioirq.c diff --git a/arch/arm/include/tms570/tms570ls04x03x_irq.h b/arch/arm/include/tms570/tms570ls04x03x_irq.h index b190dcfe48b..9a7543215cd 100644 --- a/arch/arm/include/tms570/tms570ls04x03x_irq.h +++ b/arch/arm/include/tms570/tms570ls04x03x_irq.h @@ -58,14 +58,14 @@ /* Default request to channel assignments. Undefined requests are reserved */ -#define TMS570_REQ_ESMHIGH 0 /* ESM High level interrupt (NMI) */ -#define TMS570_REQ_RTICMP0 2 /* RTI compare interrupt 0 */ -#define TMS570_REQ_RTICMP1 3 /* RTI compare interrupt 1 */ -#define TMS570_REQ_RTICMP2 4 /* RTI compare interrupt 2 */ -#define TMS570_REQ_RTICMP3 5 /* RTI compare interrupt 3 */ -#define TMS570_REQ_RTIOVF0 6 /* RTI overflow interrupt 0 */ -#define TMS570_REQ_RTIOVF1 7 /* RTI overflow interrupt 1 */ -#define TMS570_REQ_GIOA 9 /* GIO interrupt A */ +#define TMS570_REQ_ESMHIGH 0 /* ESM High level interrupt (NMI) */ +#define TMS570_REQ_RTICMP0 2 /* RTI compare interrupt 0 */ +#define TMS570_REQ_RTICMP1 3 /* RTI compare interrupt 1 */ +#define TMS570_REQ_RTICMP2 4 /* RTI compare interrupt 2 */ +#define TMS570_REQ_RTICMP3 5 /* RTI compare interrupt 3 */ +#define TMS570_REQ_RTIOVF0 6 /* RTI overflow interrupt 0 */ +#define TMS570_REQ_RTIOVF1 7 /* RTI overflow interrupt 1 */ +#define TMS570_REQ_GIO_0 9 /* GIO level 0 interrupt */ #define TMS570_REQ_N2HET_0 10 /* N2HET level 0 interrupt */ #define TMS570_REQ_HTU_0 11 /* HTU level 0 interrupt */ #define TMS570_REQ_MIBSPI1_0 12 /* MIBSPI1 level 0 interrupt */ @@ -77,7 +77,7 @@ #define TMS570_REQ_ESMLO 20 /* ESM Low level interrupt */ #define TMS570_REQ_SYSTEM 21 /* Software interrupt (SSI) */ #define TMS570_REQ_CPU 22 /* PMU interrupt */ -#define TMS570_REQ_GIOB 23 /* GIO interrupt B */ +#define TMS570_REQ_GIO_1 23 /* GIO level 1 interrupt */ #define TMS570_REQ_N2HET_1 24 /* N2HET level 1 interrupt */ #define TMS570_REQ_HTU_1 25 /* HTU level 1 interrupt */ #define TMS570_REQ_MIBSPI1_1 26 /* MIBSPI1 level 1 interrupt */ diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index 6083ef9ba48..f6303268288 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -104,7 +104,7 @@ CHIP_ASRCS = # SAMA5-specific C source files -CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_irq.c +CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_gio.c tms570_irq.c CHIP_CSRCS += tms570_lowputc.c tms570_serial.c # Configuration dependent C and assembly language files @@ -113,6 +113,10 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += tms570_timerisr.c endif -ifneq ($(CONFIG_TMS570_SELFTEST),y) +ifeq ($(CONFIG_TMS570_SELFTEST),y) CHIP_CSRCS += tms570_selftest.c endif + +ifeq ($(CONFIG_TMS570_GIO_IRQ),y) +CHIP_CSRCS += tms570_gioirq.c +endif diff --git a/arch/arm/src/tms570/chip/tms570_gio.h b/arch/arm/src/tms570/chip/tms570_gio.h index c179718bba5..1599e58ff5a 100644 --- a/arch/arm/src/tms570/chip/tms570_gio.h +++ b/arch/arm/src/tms570/chip/tms570_gio.h @@ -62,6 +62,9 @@ #define TMS570_GIOG 6 #define TMS570_GIOH 7 +#define TMS570_NPORTS 8 +#define TMS570_NIRQPORTS 4 + /* Register Offsets *********************************************************************************/ #define TMS570_GIO_GCR0_OFFSET 0x0000 /* GIO Global Control Register */ @@ -264,6 +267,10 @@ /* GIO Interrupt Detect Register */ +#define GIO_INTDET_PORT_SHIFT(p) ((p) << 3) +#define GIO_INTDET_PORT_MASK(p) (0xff << GIO_INTDET_PORT_SHIFT(p)) +# define GIO_INTDET_PORT_PIN(p,n) (1 << (GIO_INTDET_PORT_SHIFT(p) + (n))) + #define GIO_INTDET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt detection select for pins GIOA[7:0] */ #define GIO_INTDET_GIOA_MASK (0xff << GIO_INTDET_GIOA_SHIFT) # define GIO_INTDET_GIOA_PIN(n) (1 << (GIO_INTDET_GIOA_SHIFT + (n))) @@ -279,6 +286,10 @@ /* GIO Interrupt Polarity Register */ +#define GIO_POL_PORT_SHIFT(p) ((p) << 3) +#define GIO_POL_PORT_MASK(p) (0xff << GIO_POL_PORT_SHIFT(p)) +# define GIO_POL_PORT_PIN(p,n) (1 << (GIO_POL_PORT_SHIFT(p) + (n))) + #define GIO_POL_GIOA_SHIFT (0) /* Bits 0-7: Interrupt polarity select for pins GIOA[7:0] */ #define GIO_POL_GIOA_MASK (0xff << GIO_POL_GIOA_SHIFT) # define GIO_POL_GIOA_PIN(n) (1 << (GIO_POL_GIOA_SHIFT + (n))) @@ -294,6 +305,10 @@ /* GIO Interrupt Enable Set Register */ +#define GIO_ENASET_PORT_SHIFT(p) ((p) << 3) +#define GIO_ENASET_PORT_MASK(p) (0xff << GIO_ENASET_PORT_SHIFT(p)) +# define GIO_ENASET_PORT_PIN(p,n) (1 << (GIO_ENASET_PORT_SHIFT(p) + (n))) + #define GIO_ENASET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt enable for pins GIOA[7:0] */ #define GIO_ENASET_GIOA_MASK (0xff << GIO_ENASET_GIOA_SHIFT) # define GIO_ENASET_GIOA_PIN(n) (1 << (GIO_ENASET_GIOA_SHIFT + (n))) @@ -309,6 +324,10 @@ /* GIO Interrupt Enable Clear Register */ +#define GIO_ENACLR_PORT_SHIFT(p) ((p) << 3) +#define GIO_ENACLR_PORT_MASK(p) (0xff << GIO_ENACLR_PORT_SHIFT(p)) +# define GIO_ENACLR_PORT_PIN(p,n) (1 << (GIO_ENACLR_PORT_SHIFT(p) + (n))) + #define GIO_ENACLR_GIOA_SHIFT (0) /* Bits 0-7: Interrupt disable for pins GIOA[7:0] */ #define GIO_ENACLR_GIOA_MASK (0xff << GIO_ENACLR_GIOA_SHIFT) # define GIO_ENACLR_GIOA_PIN(n) (1 << (GIO_ENACLR_GIOA_SHIFT + (n))) @@ -324,6 +343,10 @@ /* GIO Interrupt Priority Set Register */ +#define GIO_LVLSET_PORT_SHIFT(p) ((p) << 3) +#define GIO_LVLSET_PORT_MASK(p) (0xff << GIO_LVLSET_PORT_SHIFT(p)) +# define GIO_LVLSET_PORT_PIN(p,n) (1 << (GIO_LVLSET_PORT_SHIFT(p) + (n))) + #define GIO_LVLSET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt high level select for pins GIOA[7:0] */ #define GIO_LVLSET_GIOA_MASK (0xff << GIO_LVLSET_GIOA_SHIFT) # define GIO_LVLSET_GIOA_PIN(n) (1 << (GIO_LVLSET_GIOA_SHIFT + (n))) @@ -339,6 +362,10 @@ /* GIO Interrupt Priority Clear Register */ +#define GIO_LVLCLR_PORT_SHIFT(p) ((p) << 3) +#define GIO_LVLCLR_PORT_MASK(p) (0xff << GIO_LVLCLR_PORT_SHIFT(p)) +# define GIO_LVLCLR_PORT_PIN(p,n) (1 << (GIO_LVLCLR_PORT_SHIFT(p) + (n))) + #define GIO_LVLCLR_GIOA_SHIFT (0) /* Bits 0-7: Interrupt low level select for pins GIOA[7:0] */ #define GIO_LVLCLR_GIOA_MASK (0xff << GIO_LVLCLR_GIOA_SHIFT) # define GIO_LVLCLR_GIOA_PIN(n) (1 << (GIO_LVLCLR_GIOA_SHIFT + (n))) @@ -354,6 +381,10 @@ /* GIO Interrupt Flag Register */ +#define GIO_FLG_PORT_SHIFT(p) ((p) << 3) +#define GIO_FLG_PORT_MASK(p) (0xff << GIO_FLG_PORT_SHIFT(p)) +# define GIO_FLG_PORT_PIN(p,n) (1 << (GIO_FLG_PORT_SHIFT(p) + (n))) + #define GIO_FLG_GIOA_SHIFT (0) /* Bits 0-7: Interrupt flag for pins GIOA[7:0] */ #define GIO_FLG_GIOA_MASK (0xff << GIO_FLG_GIOA_SHIFT) # define GIO_FLG_GIOA_PIN(n) (1 << (GIO_FLG_GIOA_SHIFT + (n))) @@ -369,46 +400,46 @@ /* GIO Offset 1/2 Register and GIO Emulation 1/2 Register */ -#define GIO_OFF_MASK (0x3f) /* Bits 0-5: GIO offset */ -# define GIO_OFF_NONE (0x00) /* No interrupt pending */ -# define GIO_OFF_GIOA0 (0x01) /* GIOA0 interrupt pending */ -# define GIO_OFF_GIOA1 (0x02) /* GIOA1 interrupt pending */ -# define GIO_OFF_GIOA2 (0x03) /* GIOA2 interrupt pending */ -# define GIO_OFF_GIOA3 (0x04) /* GIOA3 interrupt pending */ -# define GIO_OFF_GIOA4 (0x05) /* GIOA4 interrupt pending */ -# define GIO_OFF_GIOA5 (0x06) /* GIOA5 interrupt pending */ -# define GIO_OFF_GIOA6 (0x07) /* GIOA6 interrupt pending */ -# define GIO_OFF_GIOA7 (0x08) /* GIOA7 interrupt pending */ -# define GIO_OFF_GIOB0 (0x09) /* GIOB0 interrupt pending */ -# define GIO_OFF_GIOB1 (0x0a) /* GIOB1 interrupt pending */ -# define GIO_OFF_GIOB2 (0x0b) /* GIOB2 interrupt pending */ -# define GIO_OFF_GIOB3 (0x0c) /* GIOB3 interrupt pending */ -# define GIO_OFF_GIOB4 (0x0d) /* GIOB4 interrupt pending */ -# define GIO_OFF_GIOB5 (0x0e) /* GIOB5 interrupt pending */ -# define GIO_OFF_GIOB6 (0x0f) /* GIOB6 interrupt pending */ -# define GIO_OFF_GIOB7 (0x10) /* GIOB7 interrupt pending */ -# define GIO_OFF_GIOC0 (0x11) /* GIOC0 interrupt pending */ -# define GIO_OFF_GIOC1 (0x12) /* GIOC1 interrupt pending */ -# define GIO_OFF_GIOC2 (0x13) /* GIOC2 interrupt pending */ -# define GIO_OFF_GIOC3 (0x14) /* GIOC3 interrupt pending */ -# define GIO_OFF_GIOC4 (0x15) /* GIOC4 interrupt pending */ -# define GIO_OFF_GIOC5 (0x16) /* GIOC5 interrupt pending */ -# define GIO_OFF_GIOC6 (0x17) /* GIOC6 interrupt pending */ -# define GIO_OFF_GIOC7 (0x18) /* GIOC7 interrupt pending */ -# define GIO_OFF_GIOD0 (0x19) /* GIOD0 interrupt pending */ -# define GIO_OFF_GIOD1 (0x1a) /* GIOD1 interrupt pending */ -# define GIO_OFF_GIOD2 (0x1b) /* GIOD2 interrupt pending */ -# define GIO_OFF_GIOD3 (0x1c) /* GIOD3 interrupt pending */ -# define GIO_OFF_GIOD4 (0x1d) /* GIOD4 interrupt pending */ -# define GIO_OFF_GIOD5 (0x1e) /* GIOD5 interrupt pending */ -# define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */ -# define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */ +#define GIO_OFF_MASK (0x3f) /* Bits 0-5: GIO offset */ +# define GIO_OFF_NONE (0x00) /* No interrupt pending */ +# define GIO_OFF_GIOA0 (0x01) /* GIOA0 interrupt pending */ +# define GIO_OFF_GIOA1 (0x02) /* GIOA1 interrupt pending */ +# define GIO_OFF_GIOA2 (0x03) /* GIOA2 interrupt pending */ +# define GIO_OFF_GIOA3 (0x04) /* GIOA3 interrupt pending */ +# define GIO_OFF_GIOA4 (0x05) /* GIOA4 interrupt pending */ +# define GIO_OFF_GIOA5 (0x06) /* GIOA5 interrupt pending */ +# define GIO_OFF_GIOA6 (0x07) /* GIOA6 interrupt pending */ +# define GIO_OFF_GIOA7 (0x08) /* GIOA7 interrupt pending */ +# define GIO_OFF_GIOB0 (0x09) /* GIOB0 interrupt pending */ +# define GIO_OFF_GIOB1 (0x0a) /* GIOB1 interrupt pending */ +# define GIO_OFF_GIOB2 (0x0b) /* GIOB2 interrupt pending */ +# define GIO_OFF_GIOB3 (0x0c) /* GIOB3 interrupt pending */ +# define GIO_OFF_GIOB4 (0x0d) /* GIOB4 interrupt pending */ +# define GIO_OFF_GIOB5 (0x0e) /* GIOB5 interrupt pending */ +# define GIO_OFF_GIOB6 (0x0f) /* GIOB6 interrupt pending */ +# define GIO_OFF_GIOB7 (0x10) /* GIOB7 interrupt pending */ +# define GIO_OFF_GIOC0 (0x11) /* GIOC0 interrupt pending */ +# define GIO_OFF_GIOC1 (0x12) /* GIOC1 interrupt pending */ +# define GIO_OFF_GIOC2 (0x13) /* GIOC2 interrupt pending */ +# define GIO_OFF_GIOC3 (0x14) /* GIOC3 interrupt pending */ +# define GIO_OFF_GIOC4 (0x15) /* GIOC4 interrupt pending */ +# define GIO_OFF_GIOC5 (0x16) /* GIOC5 interrupt pending */ +# define GIO_OFF_GIOC6 (0x17) /* GIOC6 interrupt pending */ +# define GIO_OFF_GIOC7 (0x18) /* GIOC7 interrupt pending */ +# define GIO_OFF_GIOD0 (0x19) /* GIOD0 interrupt pending */ +# define GIO_OFF_GIOD1 (0x1a) /* GIOD1 interrupt pending */ +# define GIO_OFF_GIOD2 (0x1b) /* GIOD2 interrupt pending */ +# define GIO_OFF_GIOD3 (0x1c) /* GIOD3 interrupt pending */ +# define GIO_OFF_GIOD4 (0x1d) /* GIOD4 interrupt pending */ +# define GIO_OFF_GIOD5 (0x1e) /* GIOD5 interrupt pending */ +# define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */ +# define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */ /* GIO Data Direction Register, GIO Data Input Register, GIO Data Output Register, * GIO Data Set Register, GIO Data Clear Register, GIO Open Drain Register, * GIO Pull Disable Register, and GIO Pull Select Register */ -#define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */ +#define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */ #endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H */ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 3130ed122b8..8b1cfb2cf84 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -63,6 +63,7 @@ #include "chip/tms570_sys.h" #include "chip/tms570_esm.h" #include "tms570_clockconfig.h" +#include "tms570_gio.h" #include "tms570_boot.h" /**************************************************************************** @@ -316,6 +317,10 @@ void arm_boot(void) arm_data_initialize(); #endif + /* Initialize GIO for use by board initialization logic */ + + tms570_gio_initialize(); + /* Perform board-specific initialization, This must include: * * - Initialization of board-specific memory resources (e.g., SDRAM) diff --git a/arch/arm/src/tms570/tms570_gio.c b/arch/arm/src/tms570/tms570_gio.c new file mode 100644 index 00000000000..e84cbdde3ea --- /dev/null +++ b/arch/arm/src/tms570/tms570_gio.c @@ -0,0 +1,330 @@ +/**************************************************************************** + * arch/arm/src/tms570/tms570_gio.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip/tms570_gio.h" +#include "tms570_gio.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +static const char g_portchar[TMS570_NPORTS] = +{ + 'A' +#if TMS570_NPORTS > 1 + , 'B' +#endif +#if TMS570_NPORTS > 2 + , 'C' +#endif +#if TMS570_NPORTS > 3 + , 'D' +#endif +#if TMS570_NPORTS > 4 + , 'E' +#endif +#if TMS570_NPORTS > 5 + , 'F' +#endif +#if TMS570_NPORTS > 6 + , 'G' +#endif +#if TMS570_NPORTS > 7 + , 'H' +#endif +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tms570_gio_initialize + * + * Description: + * Take the GIO block out of reset and assure that it is ready for use. + * + ****************************************************************************/ + +int tms570_gio_initialize(void) +{ + /* Take the GIO block out of reset */ + + putreg32(GIO_GCR0_RESET, TMS570_GIO_GCR0); + + /* Disable all pin interrupts on the pin. Make sure they are all level 0. */ + + putreg32(0xffffffff, TMS570_GIO_ENACLR); + putreg32(0xffffffff, TMS570_GIO_LVLCLR); + return OK; +} + +/**************************************************************************** + * Name: tms570_configgio + * + * Description: + * Configure a GIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int tms570_configgio(gio_pinset_t cfgset) +{ + uint32_t port = tms570_gio_port(cfgset); + uintptr_t base = tms570_gio_base(cfgset); + uint32_t pin = tms570_gio_pin(cfgset); + uint32_t pinmask = tms570_gio_pinmask(cfgset); + uint32_t regval; + irqstate_t flags; + + /* Disable interrupts to prohibit re-entrance. */ + + flags = irqsave(); + + /* Force the pin to be an input for now */ + + regval = getreg32(base + TMS570_GIO_DIR_OFFSET); + regval &= ~pinmask; + putreg32(regval, base + TMS570_GIO_DIR_OFFSET); + + /* Disable interrupts on the pin. Make sure this is a level 0 pin. */ + + putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENACLR); + putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR); + + /* Setup settings common to both input and output pins */ + /* Enable/disable the pull-up/down as requested */ + + switch (cfgset & GIO_CFG_MASK) + { + case GIO_CFG_DEFAULT: /* Default, no attribute */ + default: + { + /* Disable pull functionality */ + + regval = getreg32(base + TMS570_GIO_PULDIS_OFFSET); + regval &= ~pinmask; + putreg32(regval, base + TMS570_GIO_PULDIS_OFFSET); + } + break; + + case GIO_CFG_PULLUP: /* Internal pull-up */ + { + /* Select pull-up */ + + regval = getreg32(base + TMS570_GIO_PSL_OFFSET); + regval |= pinmask; + putreg32(regval, base + TMS570_GIO_PSL_OFFSET); + + /* Enable pull functionality */ + + regval = getreg32(base + TMS570_GIO_PULDIS_OFFSET); + regval |= pinmask; + putreg32(regval, base + TMS570_GIO_PULDIS_OFFSET); + } + break; + + case GIO_CFG_PULLDOWN: /* Internal pull-down */ + { + /* Select pull-down */ + + regval = getreg32(base + TMS570_GIO_PSL_OFFSET); + regval |= pinmask; + putreg32(regval, base + TMS570_GIO_PSL_OFFSET); + + /* Enable pull functionality */ + + regval = getreg32(base + TMS570_GIO_DIR_OFFSET); + regval |= pinmask; + putreg32(regval, base + TMS570_GIO_DIR_OFFSET); + } + break; + } + + /* Then do unique operations for an output pin */ + + if ((cfgset & GIO_MODE_MASK) == GIO_OUTPUT) + { + /* Enable the open drain driver if requested */ + + regval = getreg32(base + TMS570_GIO_PDR_OFFSET); + if ((cfgset & GIO_OPENDRAIN) != 0) + { + regval |= pinmask; + } + else + { + regval &= ~pinmask; + } + + putreg32(regval, base + TMS570_GIO_PDR_OFFSET); + + /* Set default output value */ + + if ((cfgset & GIO_OUTPUT_SET) != 0) + { + putreg32(pinmask, base + TMS570_GIO_DSET_OFFSET); + } + else + { + putreg32(pinmask, base + TMS570_GIO_DCLR_OFFSET); + } + + /* Finally, configure the pin as an output */ + + regval = getreg32(base + TMS570_GIO_DIR_OFFSET); + regval |= pinmask; + putreg32(regval, base + TMS570_GIO_DIR_OFFSET); + } + + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Name: tms570_giowrite + * + * Description: + * Write one or zero to the selected GIO pin + * + ****************************************************************************/ + +void tms570_giowrite(gio_pinset_t pinset, bool value) +{ + uintptr_t base = tms570_gio_base(pinset); + uint32_t pinmask = tms570_gio_pinmask(pinset); + + if (value) + { + putreg32(pinmask, base + TMS570_GIO_DSET_OFFSET); + } + else + { + putreg32(pinmask, base + TMS570_GIO_DCLR_OFFSET); + } +} + +/**************************************************************************** + * Name: tms570_gioread + * + * Description: + * Read one or zero from the selected GIO pin + * + ****************************************************************************/ + +bool tms570_gioread(gio_pinset_t pinset) +{ + uintptr_t base = tms570_gio_base(pinset); + uint32_t pinmask = tms570_gio_pinmask(pinset); + uint32_t regval; + + if ((pinset & GIO_MODE_MASK) == GIO_OUTPUT) + { + regval = getreg32(base + TMS570_GIO_DOUT_OFFSET); + } + else + { + regval = getreg32(base + TMS570_GIO_DIN_OFFSET); + } + + return (regval & pinmask) != 0; +} + +/************************************************************************************ + * Function: tms570_dumpgio + * + * Description: + * Dump all GIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int tms570_dumpgio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + uintptr_t base; + unsigned int port; + + lldbg("GIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + + /* Get the base address associated with the GIO port */ + + port = (pinset & GIO_PORT_MASK) >> GIO_PORT_SHIFT; + base = TMS570_GIO_PORTBASE(port); + + /* The following requires exclusive access to the GIO registers */ + + flags = irqsave(); + + /* Show global GIO registers */ + + lldbg(" GCR0: %08x INTDET: %08x POL: %08x ENA: %08x\n", + getreg32(TMS570_GIO_GCR0), getreg32(TMS570_GIO_INTDET), + getreg32(TMS570_GIO_POL), getreg32(TMS570_GIO_ENASET)); + lldbg(" LVL: %08x FLG: %08x EMU1: %08x EMU2: %08x\n", + getreg32(TMS570_GIO_LVLSET), getreg32(TMS570_GIO_FLG), + getreg32(TMS570_GIO_EMU1), getreg32(TMS570_GIO_EMU2)); + + /* Port specific registers */ + + lldbg(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n", + getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET), + getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET)); + lldbg(" PULDIS: %08x PSL: %08x\n", + getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET)); + + irqrestore(flags); + return OK; +} +#endif diff --git a/arch/arm/src/tms570/tms570_gio.h b/arch/arm/src/tms570/tms570_gio.h index dadb759363e..bc59e8b1e22 100644 --- a/arch/arm/src/tms570/tms570_gio.h +++ b/arch/arm/src/tms570/tms570_gio.h @@ -46,6 +46,8 @@ #include #include +#include "chip/tms570_gio.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -54,7 +56,7 @@ /* 32-bit Encoding: * - * .... .... .... .... MCCC .IIV PPP. .BBB + * .... .... .... .... M.CC IIOV PPP. .BBB */ /* Input/Output mode: @@ -70,28 +72,34 @@ /* These bits set the configuration of the pin: * NOTE: No definitions for parallel capture mode * - * .... .... .... .... .CCC .... .... .... + * .... .... .... .... ..CC .... .... .... */ #define GIO_CFG_SHIFT (12) /* Bits 12-14: GIO configuration bits */ -#define GIO_CFG_MASK (7 << GIO_CFG_SHIFT) +#define GIO_CFG_MASK (3 << GIO_CFG_SHIFT) # define GIO_CFG_DEFAULT (0 << GIO_CFG_SHIFT) /* Default, no attribute */ # define GIO_CFG_PULLUP (1 << GIO_CFG_SHIFT) /* Bit 16: Internal pull-up */ # define GIO_CFG_PULLDOWN (2 << GIO_CFG_SHIFT) /* Bit 17: Internal pull-down */ -# define GIO_CFG_OPENDRAIN (4 << GIO_CFG_SHIFT) /* Bit 19: Open drain */ /* Interrupt modes: * - * .... .... .... .... .... .II. .... .... + * .... .... .... .... .... II.. .... .... */ -#define GIO_INT_SHIFT (9) /* Bits 9-10: GIO interrupt bits */ +#define GIO_INT_SHIFT (10) /* Bits 10-11: GIO interrupt bits */ #define GIO_INT_MASK (3 << GIO_INT_SHIFT) # define GIO_INT_NONE (0 << GIO_INT_SHIFT) # define GIO_INT_RISING (1 << GIO_INT_SHIFT) # define GIO_INT_FALLING (2 << GIO_INT_SHIFT) # define GIO_INT_BOTHEDGES (3 << GIO_INT_SHIFT) +/* If the pin is an GIO output, then this selects the open drain output + * + * .... .... .... .... .... ..O. .... .... + */ + +#define GIO_OPENDRAIN (1 << 9) /* Bit 9: Open drain mode */ + /* If the pin is an GIO output, then this identifies the initial output value: * * .... .... .... .... .... ...V .... .... @@ -170,7 +178,7 @@ extern "C" static inline uintptr_t tms570_gio_base(gio_pinset_t cfgset) { int port = (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT; - return TMS570_GIO_PORTBASE(n); + return TMS570_GIO_PORTBASE(port); } /**************************************************************************** @@ -216,8 +224,18 @@ static inline int tms570_gio_pinmask(gio_pinset_t cfgset) * Public Function Prototypes ************************************************************************************/ +/**************************************************************************** + * Name: tms570_gio_initialize + * + * Description: + * Take the GIO block out of reset and assure that it is ready for use. + * + ****************************************************************************/ + +int tms570_gio_initialize(void); + /************************************************************************************ - * Name: tms570_gioirqinitialize + * Name: tms570_gioirq_initialize * * Description: * Initialize logic to support a second level of interrupt decoding for GIO pins. @@ -225,9 +243,9 @@ static inline int tms570_gio_pinmask(gio_pinset_t cfgset) ************************************************************************************/ #ifdef CONFIG_TMS570_GIO_IRQ -void tms570_gioirqinitialize(void); +void tms570_gioirq_initialize(void); #else -# define tms570_gioirqinitialize() +# define tms570_gioirq_initialize() #endif /************************************************************************************ @@ -310,7 +328,7 @@ void tms570_gioirqdisable(int irq); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_GIO +#ifdef CONFIG_DEBUG_GPIO int tms570_dumpgio(uint32_t pinset, const char *msg); #else # define tms570_dumpgio(p,m) diff --git a/arch/arm/src/tms570/tms570_gioirq.c b/arch/arm/src/tms570/tms570_gioirq.c new file mode 100644 index 00000000000..1da8d21d1fb --- /dev/null +++ b/arch/arm/src/tms570/tms570_gioirq.c @@ -0,0 +1,256 @@ +/**************************************************************************** + * arch/arm/src/tms570/tms570_gioirq.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "tms570_gio.h" +#include "chip/tms570_gio.h" + +#ifdef CONFIG_TMS570_GIO_IRQ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tms570_gio_interrupt + * + * Description: + * Receive GIO interrupts + * + ****************************************************************************/ + +static int tms3570_gio_interrupt(int irq, void *context) +{ + uint32_t off1; + int irq2; + + /* Loop until all pending GIO interrupts have been processed */ + + while ((off1 = getreg32(TMS570_GIO_OFF1)) != GIO_OFF_NONE) + { + /* Convert the offset value to the second-level IRQ number */ + + irq2 = off1 + TMS570_IRQ_GIOA0 - 1; + + /* And dispatch the second-level GIO IRQ */ + + irq_dispatch(irq2, context); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tms570_gioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GIO pins. + * + ****************************************************************************/ + +void tms570_gioirqinitialize(void) +{ + /* Disable all pin interrupts on the pin. Make sure they are all level 0. */ + + putreg32(0xffffffff, TMS570_GIO_ENACLR); + putreg32(0xffffffff, TMS570_GIO_LVLCLR); + + /* Attach and enable the GIO level 0 interrupt */ + + DEBUGVERIFY(irq_attach(TMS570_REQ_GIO_0, tms3570_gio_interrupt)); + up_enable_irq(TMS570_REQ_GIO_0); +} + +/************************************************************************************ + * Name: tms570_gioirq + * + * Description: + * Configure an interrupt for the specified GIO pin. + * + ************************************************************************************/ + +void tms570_gioirq(gio_pinset_t pinset) +{ + uint32_t port = tms570_gio_port(pinset); + uint32_t pin = tms570_gio_pin(pinset); + irqstate_t flags; + uint32_t regval; + + /* Start with the pin interrupts disabled. Make sure that level 0 is selected. */ + + putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENACLR); + putreg32(GIO_LVLCLR_PORT_PIN(port, pin), TMS570_GIO_LVLCLR); + + /* Make sure that the pin is configured as an input and that interrupts can e + * supported on this port. + */ + + if ((pinset & GIO_MODE_MASK) == GIO_INPUT && port < TMS570_NIRQPORTS) + { + flags = irqsave(); + switch (pinset & GIO_INT_MASK) + { + case GIO_INT_NONE: + default: + break; + + case GIO_INT_RISING: + { + /* Enable rising edge detectioni */ + + regval = getreg32(TMS570_GIO_POL); + regval |= GIO_POL_PORT_PIN(port, pin); + putreg32(regval, TMS570_GIO_POL); + + /* Disable both rising and falling edge detection */ + + regval = getreg32(TMS570_GIO_INTDET); + regval &= ~GIO_INTDET_PORT_PIN(port, pin); + putreg32(regval, TMS570_GIO_INTDET); + } + break; + + case GIO_INT_FALLING: + { + /* Enable falling edge detectioni */ + + regval = getreg32(TMS570_GIO_POL); + regval &= ~GIO_POL_PORT_PIN(port, pin); + putreg32(regval, TMS570_GIO_POL); + + /* Disable both rising and falling edge detection */ + + regval = getreg32(TMS570_GIO_INTDET); + regval &= ~GIO_INTDET_PORT_PIN(port, pin); + putreg32(regval, TMS570_GIO_INTDET); + } + break; + + case GIO_INT_BOTHEDGES: + { + /* Enable both rising and falling edge detection */ + + regval = getreg32(TMS570_GIO_INTDET); + regval |= GIO_INTDET_PORT_PIN(port, pin); + putreg32(regval, TMS570_GIO_INTDET); + } + break; + } + + irqrestore(flags); + } +} + +/************************************************************************************ + * Name: tms570_gioirqenable + * + * Description: + * Enable the interrupt for specified GIO IRQ + * + ************************************************************************************/ + +void tms570_gioirqenable(int irq) +{ + int offset; + int port; + int pin; + + offset = irq - TMS570_IRQ_GIOA0; + if (offset < TMS570_NGIO_IRQS) + { + /* Convert the offset IRQ number to a port and pin number */ + + pin = offset & 7; + port = offset >> 3; + + /* Enable this pin interrupt */ + + putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENASET); + } +} + +/************************************************************************************ + * Name: tms570_gioirqdisable + * + * Description: + * Disable the interrupt for specified GIO IRQ + * + ************************************************************************************/ + +void tms570_gioirqdisable(int irq) +{ + int offset; + int port; + int pin; + + offset = irq - TMS570_IRQ_GIOA0; + if (offset < TMS570_NGIO_IRQS) + { + /* Convert the offset IRQ number to a port and pin number */ + + pin = offset & 7; + port = offset >> 3; + + /* Enable this pin interrupt */ + + putreg32(GIO_ENACLR_PORT_PIN(port, pin), TMS570_GIO_ENACLR); + } +} + +#endif /* CONFIG_TMS570_GIO_IRQ */ diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index 847eda87253..3a6fdb295d7 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -178,7 +178,7 @@ void up_irqinitialize(void) * GIO pins. */ - tms570_gioirqinitialize(); + tms570_gioirq_initialize(); #endif /* And finally, enable interrupts */ From 9c1b677bd5400e81a4479408fc91667c221a4353 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 08:18:52 -0600 Subject: [PATCH 07/22] TMS570: Clean up misc. build issues --- arch/arm/src/tms570/tms570_boot.c | 4 +++- arch/arm/src/tms570/tms570_gioirq.c | 2 +- arch/arm/src/tms570/tms570_irq.c | 13 ++++--------- arch/arm/src/tms570/tms570_selftest.c | 2 ++ arch/arm/src/tms570/tms570_selftest.h | 2 ++ 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 8b1cfb2cf84..f4abd925e8d 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -62,7 +62,9 @@ #include "chip/tms570_sys.h" #include "chip/tms570_esm.h" +#include "chip/tms570_pbist.h" #include "tms570_clockconfig.h" +#include "tms570_selftest.h" #include "tms570_gio.h" #include "tms570_boot.h" @@ -231,7 +233,7 @@ void arm_boot(void) /* Run the memory selftest on CPU RAM. */ - tms570_memtest_start(PBIST_RINFOL_ESRAM1_RAM) + tms570_memtest_start(PBIST_RINFOL_ESRAM1_RAM); ASSERT(tms570_memtest_complete() == 0); #endif /* CONFIG_TMS570_SELFTEST */ diff --git a/arch/arm/src/tms570/tms570_gioirq.c b/arch/arm/src/tms570/tms570_gioirq.c index 1da8d21d1fb..c20300e0b60 100644 --- a/arch/arm/src/tms570/tms570_gioirq.c +++ b/arch/arm/src/tms570/tms570_gioirq.c @@ -104,7 +104,7 @@ static int tms3570_gio_interrupt(int irq, void *context) * ****************************************************************************/ -void tms570_gioirqinitialize(void) +void tms570_gioirq_initialize(void) { /* Disable all pin interrupts on the pin. Make sure they are all level 0. */ diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index 3a6fdb295d7..dad8c10fd0f 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -52,6 +52,7 @@ #include "up_internal.h" #include "chip/tms570_vim.h" +#include "tms570_gio.h" #include "tms570_irq.h" /**************************************************************************** @@ -207,7 +208,7 @@ uint32_t *arm_decodeirq(uint32_t *regs) int vector; /* Check for a VRAM parity error. This is not to critical in this - * implementatin since VIM RAM is not used. + * implementation since VIM RAM is not used. */ #warning Missing logic @@ -225,9 +226,6 @@ uint32_t *arm_decodeirq(uint32_t *regs) regs = arm_doirq(vector - 1, regs); } - /* Acknowledge interrupt */ -#warning Verify not needed - return regs; } @@ -252,7 +250,7 @@ uint32_t *arm_decodefiq(FAR uint32_t *regs) int vector; /* Check for a VRAM parity error. This is not to critical in this - * implementatin since VIM RAM is not used. + * implementation since VIM RAM is not used. */ #warning Missing logic @@ -267,12 +265,9 @@ uint32_t *arm_decodefiq(FAR uint32_t *regs) * number offset by one to skip over the "phantom" vector. */ - regs = arm_doirq(vector - 1, regs) + regs = arm_doirq(vector - 1, regs); } - /* Acknowledge interrupt */ -#warning Verify not needed - return regs; } #endif diff --git a/arch/arm/src/tms570/tms570_selftest.c b/arch/arm/src/tms570/tms570_selftest.c index 16cee512115..eba0f3deed6 100644 --- a/arch/arm/src/tms570/tms570_selftest.c +++ b/arch/arm/src/tms570/tms570_selftest.c @@ -45,6 +45,8 @@ #include +#include + #include "tms570_selftest.h" #ifdef CONFIG_TMS570_SELFTEST diff --git a/arch/arm/src/tms570/tms570_selftest.h b/arch/arm/src/tms570/tms570_selftest.h index 783928043f3..bfc2bd41308 100644 --- a/arch/arm/src/tms570/tms570_selftest.h +++ b/arch/arm/src/tms570/tms570_selftest.h @@ -42,6 +42,8 @@ #include +#include + #ifdef CONFIG_TMS570_SELFTEST /**************************************************************************** From a27cd8e54e8c4574b73ae5e1a9803ec18e9ba2fb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 10:01:53 -0600 Subject: [PATCH 08/22] TMS570: Add the beginning of some selftest logic --- arch/arm/src/tms570/chip/tms570_pbist.h | 253 +++++++++++++++-------- arch/arm/src/tms570/chip/tms570_sys.h | 96 +++++---- arch/arm/src/tms570/tms570_boot.c | 4 +- arch/arm/src/tms570/tms570_clockconfig.c | 2 +- arch/arm/src/tms570/tms570_selftest.c | 192 ++++++++++++++++- 5 files changed, 405 insertions(+), 142 deletions(-) diff --git a/arch/arm/src/tms570/chip/tms570_pbist.h b/arch/arm/src/tms570/chip/tms570_pbist.h index 1cc8387428b..2e4cfb5d725 100644 --- a/arch/arm/src/tms570/chip/tms570_pbist.h +++ b/arch/arm/src/tms570/chip/tms570_pbist.h @@ -54,118 +54,195 @@ ****************************************************************************************************/ /* PBIST RAM Groups */ -#define PBIST_PBIST_ROM_GROUP 1 /* ROM */ -#define PBIST_STC_ROM_GROUP 2 /* ROM */ -#define PBIST_DCAN1_RAM_GROUP 3 /* Dual-port */ -#define PBIST_DCAN2_RAM_GROUP 4 /* Dual-port */ -#define PBIST_ESRAM1_RAM_GROUP 6 /* Single-port */ -#define PBIST_MIBSPI1_RAM_GROUP 7 /* Dual-port */ -#define PBIST_VIM_RAM_GROUP 10 /* Dual-port */ -#define PBIST_MIBADC_RAM_GROUP 11 /* Dual-port */ -#define PBIST_N2HET_RAM_GROUP 13 /* Dual-port */ -#define PBIST_HET_TU_RAM_GROUP 14 /* Dual-port */ +#define PBIST_PBIST_ROM_GROUP 1 /* ROM */ +#define PBIST_STC_ROM_GROUP 2 /* ROM */ +#define PBIST_DCAN1_RAM_GROUP 3 /* Dual-port */ +#define PBIST_DCAN2_RAM_GROUP 4 /* Dual-port */ +#define PBIST_ESRAM1_RAM_GROUP 6 /* Single-port */ +#define PBIST_MIBSPI1_RAM_GROUP 7 /* Dual-port */ +#define PBIST_VIM_RAM_GROUP 10 /* Dual-port */ +#define PBIST_MIBADC_RAM_GROUP 11 /* Dual-port */ +#define PBIST_N2HET_RAM_GROUP 13 /* Dual-port */ +#define PBIST_HET_TU_RAM_GROUP 14 /* Dual-port */ /* RAM Group Select */ -#define PBIST_PBIST_ROM_RGS 1 /* ROM */ -#define PBIST_STC_ROM_RGS 2 /* ROM */ -#define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */ -#define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */ -#define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */ -#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ -#define PBIST_VIM_RAM_RGS 8 /* Dual-port */ -#define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */ -#define PBIST_N2HET_RAM_RGS 11 /* Dual-port */ -#define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */ +#define PBIST_PBIST_ROM_RGS 1 /* ROM */ +#define PBIST_STC_ROM_RGS 2 /* ROM */ +#define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */ +#define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */ +#define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */ +#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ +#define PBIST_VIM_RAM_RGS 8 /* Dual-port */ +#define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */ +#define PBIST_N2HET_RAM_RGS 11 /* Dual-port */ +#define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */ /* Register Offsets *********************************************************************************/ -#define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */ -#define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */ -#define TMS570_PBIST_PCR_OFFSET 0x016c /* Program Control Register */ -#define TMS570_PBIST_PACT_OFFSET 0x0180 /* PBIST Activate/ROM Clock Enable Register */ -#define TMS570_PBIST_PBISTID_OFFSET 0x0184 /* PBIST ID Register */ -#define TMS570_PBIST_OVER_OFFSET 0x0188 /* Override Register */ -#define TMS570_PBIST_FSRF0_OFFSET 0x0190 /* Fail Status Fail Register 0 */ -#define TMS570_PBIST_FSRC0_OFFSET 0x0198 /* Fail Status Count Register 0 */ -#define TMS570_PBIST_FSRC1_OFFSET 0x019c /* Fail Status Count Register 1 */ -#define TMS570_PBIST_FSRA0_OFFSET 0x01a0 /* Fail Status Address 0 Register */ -#define TMS570_PBIST_FSRA1_OFFSET 0x01a4 /* Fail Status Address 1 Register */ -#define TMS570_PBIST_FSRDL0_OFFSET 0x01a8 /* Fail Status Data Register 0 */ -#define TMS570_PBIST_FSRDL1_OFFSET 0x01b0 /* Fail Status Data Register 1 */ -#define TMS570_PBIST_ROM_OFFSET 0x01c0 /* ROM Mask Register */ -#define TMS570_PBIST_ALGO_OFFSET 0x01c4 /* ROM Algorithm Mask Register */ -#define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */ -#define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */ +#define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */ +#define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */ +#define TMS570_PBIST_PCR_OFFSET 0x016c /* Program Control Register */ +#define TMS570_PBIST_PACT_OFFSET 0x0180 /* PBIST Activate/ROM Clock Enable Register */ +#define TMS570_PBIST_PBISTID_OFFSET 0x0184 /* PBIST ID Register */ +#define TMS570_PBIST_OVER_OFFSET 0x0188 /* Override Register */ +#define TMS570_PBIST_FSRF0_OFFSET 0x0190 /* Fail Status Fail Register 0 */ +#define TMS570_PBIST_FSRF1_OFFSET 0x0194 /* Fail Status Fail Register 1 */ +#define TMS570_PBIST_FSRC0_OFFSET 0x0198 /* Fail Status Count Register 0 */ +#define TMS570_PBIST_FSRC1_OFFSET 0x019c /* Fail Status Count Register 1 */ +#define TMS570_PBIST_FSRA0_OFFSET 0x01a0 /* Fail Status Address 0 Register */ +#define TMS570_PBIST_FSRA1_OFFSET 0x01a4 /* Fail Status Address 1 Register */ +#define TMS570_PBIST_FSRDL0_OFFSET 0x01a8 /* Fail Status Data Register 0 */ +#define TMS570_PBIST_FSRDL1_OFFSET 0x01b0 /* Fail Status Data Register 1 */ +#define TMS570_PBIST_ROM_OFFSET 0x01c0 /* ROM Mask Register */ +#define TMS570_PBIST_ALGO_OFFSET 0x01c4 /* ROM Algorithm Mask Register */ +#define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */ +#define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */ /* Register Addresses *******************************************************************************/ -#define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET) -#define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET) -#define TMS570_PBIST_PCR (TMS570_PBIST_BASE+TMS570_PBIST_PCR_OFFSET) -#define TMS570_PBIST_PACT (TMS570_PBIST_BASE+TMS570_PBIST_PACT_OFFSET) -#define TMS570_PBIST_PBISTID (TMS570_PBIST_BASE+TMS570_PBIST_PBISTID_OFFSET) -#define TMS570_PBIST_OVER (TMS570_PBIST_BASE+TMS570_PBIST_OVER_OFFSET) -#define TMS570_PBIST_FSRF0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF0_OFFSET) -#define TMS570_PBIST_FSRC0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC0_OFFSET) -#define TMS570_PBIST_FSRC1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC1_OFFSET) -#define TMS570_PBIST_FSRA0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA0_OFFSET) -#define TMS570_PBIST_FSRA1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA1_OFFSET) -#define TMS570_PBIST_FSRDL0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL0_OFFSET) -#define TMS570_PBIST_FSRDL1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL1_OFFSET) -#define TMS570_PBIST_ROM (TMS570_PBIST_BASE+TMS570_PBIST_ROM_OFFSET) -#define TMS570_PBIST_ALGO (TMS570_PBIST_BASE+TMS570_PBIST_ALGO_OFFSET) -#define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET) -#define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET) +#define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET) +#define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET) +#define TMS570_PBIST_PCR (TMS570_PBIST_BASE+TMS570_PBIST_PCR_OFFSET) +#define TMS570_PBIST_PACT (TMS570_PBIST_BASE+TMS570_PBIST_PACT_OFFSET) +#define TMS570_PBIST_PBISTID (TMS570_PBIST_BASE+TMS570_PBIST_PBISTID_OFFSET) +#define TMS570_PBIST_OVER (TMS570_PBIST_BASE+TMS570_PBIST_OVER_OFFSET) +#define TMS570_PBIST_FSRF0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF0_OFFSET) +#define TMS570_PBIST_FSRF1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF1_OFFSET) +#define TMS570_PBIST_FSRC0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC0_OFFSET) +#define TMS570_PBIST_FSRC1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC1_OFFSET) +#define TMS570_PBIST_FSRA0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA0_OFFSET) +#define TMS570_PBIST_FSRA1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA1_OFFSET) +#define TMS570_PBIST_FSRDL0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL0_OFFSET) +#define TMS570_PBIST_FSRDL1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL1_OFFSET) +#define TMS570_PBIST_ROM (TMS570_PBIST_BASE+TMS570_PBIST_ROM_OFFSET) +#define TMS570_PBIST_ALGO (TMS570_PBIST_BASE+TMS570_PBIST_ALGO_OFFSET) +#define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET) +#define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET) /* Register Bit-Field Definitions *******************************************************************/ /* RAM Configuration Register */ -#define PBIST_RAMT_ + +#define PBIST_RAMT_RLS_SHIFT (0) /* Bits 0-1: RAM Latency Select */ +#define PBIST_RAMT_RLS_MASK (3 << PBIST_RAMT_RLS_SHIFT) +# define PBIST_RAMT_RLS(n) ((uint32_t)(n) << PBIST_RAMT_RLS_SHIFT) +#define PBIST_RAMT_PLS_SHIFT (2) /* Bits 2-5: Pipeline Latency Select */ +#define PBIST_RAMT_PLS_MASK (15 << PBIST_RAMT_PLS_SHIFT) +# define PBIST_RAMT_PLS(n) ((uint32_t)(n) << PBIST_RAMT_PLS_SHIFT) +#define PBIST_RAMT_SMS_SHIFT (6) /* Bits 6-7: Sense Margin Select Register */ +#define PBIST_RAMT_SMS_MASK (3 << PBIST_RAMT_SMS_SHIFT) +# define PBIST_RAMT_SMS(n) ((uint32_t)(n) << PBIST_RAMT_SMS_SHIFT) +#define PBIST_RAMT_DWR_SHIFT (8) /* Bits 8-15: Data Width Register */ +#define PBIST_RAMT_DWR_MASK (0xff << PBIST_RAMT_DWR_SHIFT) +# define PBIST_RAMT_DWR(n) ((uint32_t)(n) << PBIST_RAMT_DWR_SHIFT) +#define PBIST_RAMT_RDS_SHIFT (16) /* Bits 16-23: Return Data Select */ +#define PBIST_RAMT_RDS_MASK (0xff << PBIST_RAMT_RDS_SHIFT) +# define PBIST_RAMT_RDS(n) ((uint32_t)(n) << PBIST_RAMT_RDS_SHIFT) +#define PBIST_RAMT_RGS_SHIFT (14) /* Bits 24-31: Ram Group Select */ +#define PBIST_RAMT_RGS_MASK (0xff << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS(n) ((uint32_t)(n) << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_PBIST_ROM (PBIST_PBIST_ROM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_STC_ROM (PBIST_STC_ROM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_DCAN1_RAM (PBIST_DCAN1_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_DCAN2_RAM (PBIST_DCAN2_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_ESRAM1_RAM (PBIST_ESRAM1_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_MIBSPI1_RAM (PBIST_MIBSPI1_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_VIM_RAM (PBIST_VIM_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_MIBADC_RAM (PBIST_MIBADC_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_N2HET_RAM (PBIST_N2HET_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_HET_TU_RAM (PBIST_HET_TU_RAM_RGS << PBIST_RAMT_RGS_SHIFT) + /* Datalogger Register */ -#define PBIST_DLR_ + +#define PBIST_DLR_DLR2 (1 << 2) /* Bit 2: ROM-based testing */ +#define PBIST_DLR_DLR4 (1 << 4) /* Bit 4: Configuration access */ + /* Program Control Register */ -#define PBIST_PCR_ + +#define PBIST_PCR_STR_SHIFT (0) /* Bits 0-4: PBIST Controller Mode */ +#define PBIST_PCR_STR_MASK (0x1f << PBIST_PCR_STR_SHIFT) +# define PBIST_PCR_STR_START (1 << PBIST_PCR_STR_SHIFT) /* Start / Time Stamp mode restart */ +# define PBIST_PCR_STR_RESUME (2 << PBIST_PCR_STR_SHIFT) /* Resume / Emulation read */ +# define PBIST_PCR_STR_STOP (4 << PBIST_PCR_STR_SHIFT) /* Stop */ +# define PBIST_PCR_STR_STEP (8 << PBIST_PCR_STR_SHIFT) /* Step / Step for emulation mode */ +# define PBIST_PCR_STR_MISR (16 << PBIST_PCR_STR_SHIFT) /* Check MISR mode */ + /* PBIST Activate/ROM Clock Enable Register */ -#define PBIST_PACT_ + +#define PBIST_PACT_PACT0 (1 << 0) /* Bit 0: ROM Clock Enable */ +#define PBIST_PACT_PACT1 (1 << 1) /* Bit 1: PBIST Activate */ + /* PBIST ID Register */ -#define PBIST_PBISTID_ + +#define PBIST_PBISTID_SHIFT (0) /* Bits 0-7: PBIST controller ID */ +#define PBIST_PBISTID_MASK (0xff << PBIST_PBISTID_SHIFT) +# define PBIST_PBISTID(n) ((uint32_t)(n) << PBIST_PBISTID_SHIFT) + /* Override Register */ -#define PBIST_OVER_ -/* Fail Status Fail Register 0 */ -#define PBIST_FSRF0_ -/* Fail Status Count Register 0 */ -#define PBIST_FSRC0_ -/* Fail Status Count Register 1 */ -#define PBIST_FSRC1_ -/* Fail Status Address 0 Register */ -#define PBIST_FSRA0_ -/* Fail Status Address 1 Register */ -#define PBIST_FSRA1_ -/* Fail Status Data Register 0 */ -#define PBIST_FSRDL0_ -/* Fail Status Data Register 1 */ -#define PBIST_FSRDL1_ + +#define PBIST_OVER_OVER0 (1 << 0) /* Bit 0: RINFO Override Bit */ + +/* Fail Status Fail Register 0/1 */ + +#define PBIST_FSRF (1 << 0) /* Bit 0: Fail Status */ + +/* Fail Status Count Register 0/1 */ + +#define PBIST_FSRC_SHIFT (0) /* Bits 0-7: Failure status count */ +#define PBIST_FSRC_MASK (0xff << PBIST_FSRC0_SHIFT) + +/* Fail Status Address 0/1 Register */ + +#define PBIST_FSRA_SHIFT (0) /* Bits 0-15: Failure status address */ +#define PBIST_FSRA_MASK (0xffff << PBIST_FSRA_SHIFT) + +/* Fail Status Data Register 0/1 (32-bit data) */ + /* ROM Mask Register */ -#define PBIST_ROM_ + +#define PBIST_ROM_SHIFT (0) /* Bits 0-1: ROM Mask */ +#define PBIST_ROM_MASK (3 << PBIST_ROM_SHIFT) +# define PBIST_ROM_NONE (0 << PBIST_ROM_SHIFT) /* No information used from ROM */ +# define PBIST_ROM_RAMINFO (1 << PBIST_ROM_SHIFT) /* Only RAM Group information from ROM */ +# define PBIST_ROM_ALGOINFO (2 << PBIST_ROM_SHIFT) /* Only Algorithm information from ROM */ +# define PBIST_ROM_BOTH (3 << PBIST_ROM_SHIFT) /* Both Algorithm and RAM information from ROM */ + /* ROM Algorithm Mask Register */ -#define PBIST_ALGO_ + +#define PBIST_ALGO_TripleReadSlow (1 << 0) +#define PBIST_ALGO_TripleReadFast (1 << 1) +#define PBIST_ALGO_March13N_DP (1 << 2) +#define PBIST_ALGO_March13N_SP (1 << 3) +#define PBIST_ALGO_DOWN1a_DP (1 << 4) +#define PBIST_ALGO_DOWN1a_SP (1 << 5) +#define PBIST_ALGO_MapColumn_DP (1 << 6) +#define PBIST_ALGO_MapColumn_SP (1 << 7) +#define PBIST_ALGO_Precharge_DP (1 << 8) +#define PBIST_ALGO_Precharge_SP (1 << 9) +#define PBIST_ALGO_DTXN2a_DP (1 << 10) +#define PBIST_ALGO_DTXN2a_SP (1 << 11) +#define PBIST_ALGO_PMOSOpen_DP (1 << 12) +#define PBIST_ALGO_PMOSOpen_SP (1 << 13) +#define PBIST_ALGO_PPMOSOpenSlice1_DP (1 << 14) +#define PBIST_ALGO_PPMOSOpenSlice1_SP (1 << 15) +#define PBIST_ALGO_PPMOSOpenSlice2_DP (1 << 16) +#define PBIST_ALGO_PPMOSOpenSlice2_SP (1 << 17) /* RAM Info Mask Lower Register */ -#define PBIST_RINFOL(n) (1 << ((n)-1)) /* Bit n: Select RAM group n+1 */ -# define PBIST_RINFOL_PBIST_ROM PBIST_RINFOL(PBIST_PBIST_ROM_GROUP) -# define PBIST_RINFOL_STC_ROM PBIST_RINFOL(PBIST_STC_ROM_GROUP) -# define PBIST_RINFOL_DCAN1_RAM PBIST_RINFOL(PBIST_DCAN1_RAM_GROUP) -# define PBIST_RINFOL_DCAN2_RAM PBIST_RINFOL(PBIST_DCAN2_RAM_GROUP) -# define PBIST_RINFOL_ESRAM1_RAM PBIST_RINFOL(PBIST_ESRAM1_RAM_GROUP) -# define PBIST_RINFOL_MIBSPI1_RAM PBIST_RINFOL(PBIST_MIBSPI1_RAM_GROUP) -# define PBIST_RINFOL_VIM_RAM PBIST_RINFOL(PBIST_VIM_RAM_GROUP) -# define PBIST_RINFOL_MIBADC_RAM PBIST_RINFOL(PBIST_MIBADC_RAM_GROUP) -# define PBIST_RINFOL_N2HET_RAM PBIST_RINFOL(PBIST_N2HET_RAM_GROUP) -# define PBIST_RINFOL_HET_TU_RAM PBIST_RINFOL(PBIST_HET_TU_RAM_GROUP) +#define PBIST_RINFOL(n) (1 << ((n)-1)) /* Bit n: Select RAM group n+1 */ +# define PBIST_RINFOL_PBIST_ROM PBIST_RINFOL(PBIST_PBIST_ROM_GROUP) +# define PBIST_RINFOL_STC_ROM PBIST_RINFOL(PBIST_STC_ROM_GROUP) +# define PBIST_RINFOL_DCAN1_RAM PBIST_RINFOL(PBIST_DCAN1_RAM_GROUP) +# define PBIST_RINFOL_DCAN2_RAM PBIST_RINFOL(PBIST_DCAN2_RAM_GROUP) +# define PBIST_RINFOL_ESRAM1_RAM PBIST_RINFOL(PBIST_ESRAM1_RAM_GROUP) +# define PBIST_RINFOL_MIBSPI1_RAM PBIST_RINFOL(PBIST_MIBSPI1_RAM_GROUP) +# define PBIST_RINFOL_VIM_RAM PBIST_RINFOL(PBIST_VIM_RAM_GROUP) +# define PBIST_RINFOL_MIBADC_RAM PBIST_RINFOL(PBIST_MIBADC_RAM_GROUP) +# define PBIST_RINFOL_N2HET_RAM PBIST_RINFOL(PBIST_N2HET_RAM_GROUP) +# define PBIST_RINFOL_HET_TU_RAM PBIST_RINFOL(PBIST_HET_TU_RAM_GROUP) /* RAM Info Mask Upper Register */ -#define PBIST_RINFOU_ #endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H */ diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/chip/tms570_sys.h index 02227702e80..af6f4c9752d 100644 --- a/arch/arm/src/tms570/chip/tms570_sys.h +++ b/arch/arm/src/tms570/chip/tms570_sys.h @@ -318,16 +318,16 @@ /* Peripheral Asynchronous Clock Source Register */ -#define SYS_VCLKASRC_VCLKA1S_SHIFT (0) /* Bits 0-3: Peripheral asynchronous clock1 source */ -#define SYS_VCLKASRC_VCLKA1S_MASK (15 << SYS_VCLKASRC_VCLKA1S_SHIFT) -# define SYS_VCLKASRC_VCLKA1S_SRC0 (0 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source0 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC1 (1 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source1 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC2 (2 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source2 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC3 (3 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source3 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC4 (4 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source4 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC5 (5 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source5 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC6 (6 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source6 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC7 (7 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source7 for RTICLK1 */ +#define SYS_VCLKASRC_VCLKA1S_SHIFT (0) /* Bits 0-3: Peripheral asynchronous clock1 source */ +#define SYS_VCLKASRC_VCLKA1S_MASK (15 << SYS_VCLKASRC_VCLKA1S_SHIFT) +# define SYS_VCLKASRC_VCLKA1S_SRC0 (0 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source0 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC1 (1 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source1 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC2 (2 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source2 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC3 (3 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source3 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC4 (4 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source4 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC5 (5 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source5 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC6 (6 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source6 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC7 (7 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source7 for RTICLK1 */ # define SYS_VCLKASRC_VCLKA1S(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA1S_SHIFT) # define SYS_VCLKASRC_VCLKA1S_OSC SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_OSC) @@ -341,45 +341,55 @@ /* RTI Clock Source Register */ -#define SYS_RCLKSRC_RTI1SRC_SHIFT (0) /* Bits 0-3: RTI clock1 source */ -#define SYS_RCLKSRC_RTI1SRC_MASK (15 << SYS_RCLKSRC_RTI1SRC_SHIFT) -# define SYS_RCLKSRC_RTI1SRC_SRC0 (0 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source0 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC1 (1 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source1 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC2 (2 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source2 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC3 (3 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source3 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC4 (4 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source4 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC5 (5 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source5 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC6 (6 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source6 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC7 (7 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source7 for RTICLK1 */ +#define SYS_RCLKSRC_RTI1SRC_SHIFT (0) /* Bits 0-3: RTI clock1 source */ +#define SYS_RCLKSRC_RTI1SRC_MASK (15 << SYS_RCLKSRC_RTI1SRC_SHIFT) +# define SYS_RCLKSRC_RTI1SRC_SRC0 (0 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source0 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC1 (1 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source1 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC2 (2 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source2 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC3 (3 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source3 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC4 (4 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source4 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC5 (5 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source5 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC6 (6 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source6 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC7 (7 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source7 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC(n) ((uint32_t)(n) << SYS_RCLKSRC_RTI1SRC_SHIFT) -# define SYS_RCLKSRC_RTI1SRC_OSC SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_OSC) -# define SYS_RCLKSRC_RTI1SRC_PLL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL1) -# define SYS_RCLKSRC_RTI1SRC_EXTERNAL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL1) -# define SYS_RCLKSRC_RTI1SRC_LPOLOW SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOLOW) -# define SYS_RCLKSRC_RTI1SRC_LPOHIGH SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOHIGH) -# define SYS_RCLKSRC_RTI1SRC_PLL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL2) -# define SYS_RCLKSRC_RTI1SRC_EXTERNAL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL2) -# define SYS_RCLKSRC_RTI1SRC_VCLK SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_VCLK) +# define SYS_RCLKSRC_RTI1SRC(n) ((uint32_t)(n) << SYS_RCLKSRC_RTI1SRC_SHIFT) +# define SYS_RCLKSRC_RTI1SRC_OSC SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_OSC) +# define SYS_RCLKSRC_RTI1SRC_PLL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL1) +# define SYS_RCLKSRC_RTI1SRC_EXTERNAL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL1) +# define SYS_RCLKSRC_RTI1SRC_LPOLOW SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOLOW) +# define SYS_RCLKSRC_RTI1SRC_LPOHIGH SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOHIGH) +# define SYS_RCLKSRC_RTI1SRC_PLL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL2) +# define SYS_RCLKSRC_RTI1SRC_EXTERNAL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL2) +# define SYS_RCLKSRC_RTI1SRC_VCLK SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_VCLK) -#define SYS_RCLKSRC_RTI1DIV_SHIFT (8) /* Bits 8-9: RTI clock 1 divider */ -#define SYS_RCLKSRC_RTI1DIV_MASK (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) -# define SYS_RCLKSRC_RTI1DIV_DIV1 (0 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 1 */ -# define SYS_RCLKSRC_RTI1DIV_DIV2 (1 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 2 */ -# define SYS_RCLKSRC_RTI1DIV_DIV4 (2 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 4 */ -# define SYS_RCLKSRC_RTI1DIV_DIV8 (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 8 */ +#define SYS_RCLKSRC_RTI1DIV_SHIFT (8) /* Bits 8-9: RTI clock 1 divider */ +#define SYS_RCLKSRC_RTI1DIV_MASK (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) +# define SYS_RCLKSRC_RTI1DIV_DIV1 (0 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 1 */ +# define SYS_RCLKSRC_RTI1DIV_DIV2 (1 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 2 */ +# define SYS_RCLKSRC_RTI1DIV_DIV4 (2 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 4 */ +# define SYS_RCLKSRC_RTI1DIV_DIV8 (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 8 */ /* Clock Source Valid Status Register */ -#define SYS_CSVSTAT_ + +#define SYS_CSVSTAT_CLKSR0V (1 << 0) /* Bit 0: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR1V (1 << 1) /* Bit 1: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR3V (1 << 3) /* Bit 3: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR4V (1 << 4) /* Bit 4: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR5V (1 << 5) /* Bit 5: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSRVALL (0x3b) /* Memory Self-Test Global Control Register */ -#define SYS_MSTGCR_CLKSR0V (1 << 0) /* Bit 0: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR1V (1 << 1) /* Bit 1: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR3V (1 << 3) /* Bit 3: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR4V (1 << 4) /* Bit 4: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR5V (1 << 5) /* Bit 5: Clock source xx valid */ -#define SYS_MSTGCR_CLKSRVALL (0x3b) +#define SYS_MSTGCR_MSTGENA_SHIFT (0) /* Bits 0-3: Memory self-test controller global enable key */ +#define SYS_MSTGCR_MSTGENA_MASK (15 << SYS_MSTGCR_MSTGENA_SHIFT) +# define SYS_MSTGCR_MSTGENA_ENABLE (10 << SYS_MSTGCR_MSTGENA_SHIFT) +# define SYS_MSTGCR_MSTGENA_DISABLE (5 << SYS_MSTGCR_MSTGENA_SHIFT) +#define SYS_MSTGCR_ROMDIV_SHIFT (8) /* Bits 8-9: Prescaler divider bits for ROM clock source */ +#define SYS_MSTGCR_ROMDIV_MASK (3 << SYS_MSTGCR_ROMDIV_SHIFT) +# define SYS_MSTGCR_ROMDIV_DIV1 (0 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCL/1; PBIST reset=16 VBUS cycles */ +# define SYS_MSTGCR_ROMDIV_DIV2 (1 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCLK/2; PBIST reset=32 VBUS cycles */ +# define SYS_MSTGCR_ROMDIV_DIV4 (2 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCLK/4. PBIST reset=64 VBUS cycles */ +# define SYS_MSTGCR_ROMDIV_DIV8 (3 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCLK/8. PBIST reset=96 VBUS cycles */ /* Memory Hardware Initialization Global Control Register */ @@ -389,8 +399,6 @@ /* Memory Self-Test/Initialization Enable Register */ -#define SYS_MSIENA_ - #if defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ) || defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ) /* From TMS570LS0x32 Data Sheet */ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index f4abd925e8d..fb893b8eece 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -234,7 +234,7 @@ void arm_boot(void) /* Run the memory selftest on CPU RAM. */ tms570_memtest_start(PBIST_RINFOL_ESRAM1_RAM); - ASSERT(tms570_memtest_complete() == 0); + ASSERT(tms570_memtest_complete() == OK); #endif /* CONFIG_TMS570_SELFTEST */ /* Initialize CPU RAM. */ @@ -272,7 +272,7 @@ void arm_boot(void) /* Wait for the memory test to complete */ - ASSERT(tms570_memtest_complete() == 0); + ASSERT(tms570_memtest_complete() == OK); #endif /* CONFIG_TMS570_SELFTEST */ /* Release the MibSPI1 modules from local reset. */ diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c index a92b2b60b8c..2e8b76a480f 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.c +++ b/arch/arm/src/tms570/tms570_clockconfig.c @@ -440,7 +440,7 @@ static void tms570_clocksrc_configure(void) { /* Get the set of valid clocks */ - csvstat = getreg32(TMS570_SYS_CSVSTAT) & SYS_MSTGCR_CLKSRVALL; + csvstat = getreg32(TMS570_SYS_CSVSTAT) & SYS_CSVSTAT_CLKSRVALL; /* Get the (inverted) state of each clock. Inverted so that '1' means * ON not OFF. diff --git a/arch/arm/src/tms570/tms570_selftest.c b/arch/arm/src/tms570/tms570_selftest.c index eba0f3deed6..2739ffd3dc4 100644 --- a/arch/arm/src/tms570/tms570_selftest.c +++ b/arch/arm/src/tms570/tms570_selftest.c @@ -20,9 +20,10 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * 3. Neither the name NuttX, Texas Instruments Incorporated, nor the + * names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -45,8 +46,14 @@ #include +#include #include +#include +#include "up_arch.h" + +#include "chip/tms570_sys.h" +#include "chip/tms570_pbist.h" #include "tms570_selftest.h" #ifdef CONFIG_TMS570_SELFTEST @@ -55,6 +62,157 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pbist_memtest_start + * + * Description: + * This function performs Memory Built-in Self test using PBIST module. + * + * Input Parameters: + * rinfol - The OR of each RAM grouping bit. See the PBIST_RINFOL* + * definitions in chip/tms570_pbist.h + * algomask - The list of algorithms to be run. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pbist_memtest_start(uint32_t rinfol, uint32_t algomask) +{ + uint32_t regval; + volatile int i; + + /* PBIST ROM clock frequency = HCLK frequency /2 */ + + regval = getreg32(TMS570_SYS_MSTGCR); + regval &= ~SYS_MSTGCR_ROMDIV_MASK; + regval |= SYS_MSTGCR_ROMDIV_DIV2; + putreg32(regval, TMS570_SYS_MSTGCR); + + /* Enable PBIST controller */ + + putreg32(SYS_MSIENA_RAM, TMS570_SYS_MSIENA); + + /* clear MSTGENA field */ + + regval = getreg32(TMS570_SYS_MSTGCR); + regval &= ~SYS_MSTGCR_MSTGENA_MASK; + putreg32(regval, TMS570_SYS_MSTGCR); + + /* Enable PBIST self-test */ + + regval |= SYS_MSTGCR_MSTGENA_ENABLE; + putreg32(regval, TMS570_SYS_MSTGCR); + + /* Wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + + for (i = 0; i < (32 + (32 * 0)); i++); + + /* Enable PBIST clocks and ROM clock */ + + regval = (PBIST_PACT_PACT0 | PBIST_PACT_PACT1); + putreg32(regval, TMS570_PBIST_PACT); + + /* Select all algorithms to be tested */ + + putreg32(algomask, TMS570_PBIST_ALGO); + + /* Select RAM groups */ + + putreg32(rinfol, TMS570_PBIST_RINFOL); + + /* Select all RAM groups */ + + putreg32(0, TMS570_PBIST_RINFOU); + + /* ROM contents will not override RINFOx settings */ + + putreg32(0, TMS570_PBIST_OVER); + + /* Algorithm code is loaded from ROM */ + + putreg32(PBIST_ROM_BOTH, TMS570_PBIST_ROM); + + /* Start PBIST */ + + regval = (PBIST_DLR_DLR2 | PBIST_DLR_DLR4); + putreg32(PBIST_ROM_BOTH, TMS570_PBIST_DLR); +} + +/**************************************************************************** + * Name: pbist_test_complete + * + * Description: + * Return true if the PBIST test is completed + * + * Input Parameters: + * None + * + * Returned Value: + * true if the PBIST test is compelte + * + ****************************************************************************/ + +static inline bool pbist_test_complete(void) +{ + return ((getreg32(TMS570_SYS_MSTCGSTAT) & SYS_MSTCGSTAT_MSTDONE) != 0); +} + +/**************************************************************************** + * Name: pbist_test_passed + * + * Description: + * Return true if the PBIST test passed + * + * Input Parameters: + * None + * + * Returned Value: + * true if the PBIST test passed + * + ****************************************************************************/ + +static inline bool pbist_test_passed(void) +{ + return ((getreg32(TMS570_PBIST_FSRF0) & PBIST_FSRF) == 0 && + (getreg32(TMS570_PBIST_FSRF1) & PBIST_FSRF) == 0); +} + +/**************************************************************************** + * Name: pbist_stop + * + * Description: + * This function is called to stop PBIST after test is performed. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pbist_stop(void) +{ + uint32_t regval; + + /* Disable PBIST clocks and ROM clock */ + + putreg32(0, TMS570_PBIST_PACT); + + regval = getreg32(TMS570_SYS_MSTGCR); + regval &= ~SYS_MSTGCR_MSTGENA_MASK; + putreg32(regval, TMS570_SYS_MSTGCR); + + regval |= SYS_MSTGCR_MSTGENA_DISABLE; + putreg32(regval, TMS570_SYS_MSTGCR); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -70,6 +228,9 @@ * that the PBIST controller is capable of detecting and indicating a * memory self-test failure. * + * Returned Value: + * None + * ****************************************************************************/ void tms570_memtest_selftest(void) @@ -84,15 +245,18 @@ void tms570_memtest_selftest(void) * Start the memory test on the selecte set of RAMs. This test does not * return until the memory test is completed. * - * Input Paramters: + * Input Parameters: * rinfol - The OR of each RAM grouping bit. See the PBIST_RINFOL* * definitions in chip/tms570_pbist.h * + * Returned Value: + * None + * ****************************************************************************/ void tms570_memtest_start(uint32_t rinfol) { -#warning Missing Logic + pbist_memtest_start(rinfol, PBIST_ALGO_March13N_SP); } /**************************************************************************** @@ -109,8 +273,22 @@ void tms570_memtest_start(uint32_t rinfol) int tms570_memtest_complete(void) { -#warning Missing Logic - return 0; + bool pass; + /* Wait for the test to complete */ + + while (!pbist_test_complete()); + + /* Get the test result */ + + pass = pbist_test_passed(); + + /* Disable PBIST clocks and disable memory self-test mode */ + + pbist_stop(); + + /* Then return the test result */ + + return pass ? OK : ERROR; } /**************************************************************************** From d592b2824ecdc47737edb624546446707547f50e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 12:05:32 -0600 Subject: [PATCH 09/22] TMS570: A little more selftest logic --- arch/arm/src/tms570/tms570_boot.c | 14 ++++++++++--- arch/arm/src/tms570/tms570_irq.c | 14 +++++++------ arch/arm/src/tms570/tms570_selftest.c | 29 ++++++++++++++++++++++++++- arch/arm/src/tms570/tms570_selftest.h | 21 +++++++++++++++++++ 4 files changed, 68 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index fb893b8eece..46008432f8e 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -268,15 +268,23 @@ void arm_boot(void) ); /* Test the CPU ECC mechanism for RAM accesses. */ -#warning Missing logic + + tms570_cpuecc_selftest(); /* Wait for the memory test to complete */ ASSERT(tms570_memtest_complete() == OK); #endif /* CONFIG_TMS570_SELFTEST */ - /* Release the MibSPI1 modules from local reset. */ -#warning Missing logic +#ifdef CONFIG_TMS570_MIBASPI1 + /* Release the MibSPI1 modules from local reset. + * + * This will cause the MibSPI1 RAMs to be initialized along with the + * parity memory. + */ + + putreg32(MIBSPI_GCR0_RESET, TMS570_MIBSPI_GCR0); +#endif /* Initialize all on-chip SRAMs except for MibSPIx RAMs. * diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index dad8c10fd0f..4ef3f0d2312 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -207,10 +207,11 @@ uint32_t *arm_decodeirq(uint32_t *regs) { int vector; - /* Check for a VRAM parity error. This is not to critical in this - * implementation since VIM RAM is not used. + /* Check for a VRAM parity error. + * + * REVISIT: This is not to critical in this implementation since VIM RAM + * is not used. */ -#warning Missing logic /* Get the interrupting vector number from the IRQINDEX register. Zero, * the "phantom" vector will returned. @@ -249,10 +250,11 @@ uint32_t *arm_decodefiq(FAR uint32_t *regs) { int vector; - /* Check for a VRAM parity error. This is not to critical in this - * implementation since VIM RAM is not used. + /* Check for a VRAM parity error. + * + * REVISIT: This is not to critical in this implementation since VIM RAM + * is not used. */ -#warning Missing logic /* Get the interrupting vector number from the FIQINDEX register. Zero, * the "phantom" vector will returned. diff --git a/arch/arm/src/tms570/tms570_selftest.c b/arch/arm/src/tms570/tms570_selftest.c index 2739ffd3dc4..3abb8d71224 100644 --- a/arch/arm/src/tms570/tms570_selftest.c +++ b/arch/arm/src/tms570/tms570_selftest.c @@ -321,7 +321,34 @@ void tms570_efc_selftest_start(void) int tms570_efc_selftest_complete(void) { #warning Missing Logic - return 0; + return OK; } +/**************************************************************************** + * Name: tms570_cpuecc_selftest + * + * Description: + * Test the CPU ECC mechanism for RAM accesses. + * + * Cause single-bit and double-bit errors in TCRAM accesses by corrupting + * 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit + * error in the ECC causes a data abort exception. The data abort handler + * must include logic written to look for deliberately caused exception and + * to return the code execution to the instruction following the one that + * caused the abort. + * + * Returned Value: + * Zero (OK) if the test passed; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +#if 0 /* Needs change to data abort handler */ +int tms570_cpuecc_selftest(void) +{ +#warning Missing Logic + return OK; +} +#endif + #endif /* CONFIG_TMS570_SELFTEST */ diff --git a/arch/arm/src/tms570/tms570_selftest.h b/arch/arm/src/tms570/tms570_selftest.h index bfc2bd41308..696bc54fe3b 100644 --- a/arch/arm/src/tms570/tms570_selftest.h +++ b/arch/arm/src/tms570/tms570_selftest.h @@ -138,6 +138,27 @@ void tms570_efc_selftest_start(void); int tms570_efc_selftest_complete(void); +/**************************************************************************** + * Name: tms570_cpuecc_selftest + * + * Description: + * Test the CPU ECC mechanism for RAM accesses. + * + * Cause single-bit and double-bit errors in TCRAM accesses by corrupting + * 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit + * error in the ECC causes a data abort exception. The data abort handler + * must include logic written to look for deliberately caused exception and + * to return the code execution to the instruction following the one that + * caused the abort. + * + * Returned Value: + * Zero (OK) if the test passed; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +#define tms570_cpuecc_selftest() + #undef EXTERN #if defined(__cplusplus) } From 1f2d9c9174f18457cd7b8e49e63e3594df7c600d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 12:26:57 -0600 Subject: [PATCH 10/22] TMS570: Does not have prioritized interrupts in the sense of other CPUs. Fix some compile errors when DEBUG is enabled --- arch/arm/Kconfig | 10 ++-------- arch/arm/src/tms570/tms570_boot.c | 2 +- arch/arm/src/tms570/tms570_irq.c | 25 +++---------------------- arch/arm/src/tms570/tms570_lowputc.c | 2 +- 4 files changed, 7 insertions(+), 32 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b3b4438c9ea..c71310194da 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARCH_CHIP_A1X select ARCH_HAVE_FPU select ARCH_HAVE_MMU select ARCH_USE_MMU + select ARCH_HAVE_IRQPRIO select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_SDRAM select BOOT_RUNFROMSDRAM @@ -157,6 +158,7 @@ config ARCH_CHIP_SAMA5 bool "Atmel SAMA5" select ARCH_CORTEXA5 select ARCH_HAVE_FPU + select ARCH_HAVE_IRQPRIO select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_I2CRESET select ARCH_HAVE_TICKLESS @@ -302,7 +304,6 @@ config ARCH_CORTEXM7 config ARCH_CORTEXA5 bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MMU select ARCH_USE_MMU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE @@ -310,7 +311,6 @@ config ARCH_CORTEXA5 config ARCH_CORTEXA8 bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MMU select ARCH_USE_MMU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE @@ -318,14 +318,12 @@ config ARCH_CORTEXA8 config ARCH_CORTEXR4 bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MPU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXR4F bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MPU select ARCH_HAVE_FPU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE @@ -333,14 +331,12 @@ config ARCH_CORTEXR4F config ARCH_CORTEXR5 bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MPU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEX5F bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MPU select ARCH_HAVE_FPU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE @@ -348,14 +344,12 @@ config ARCH_CORTEX5F config ARCH_CORTEXR7 bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MPU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXR7F bool default n - select ARCH_HAVE_IRQPRIO select ARCH_HAVE_MPU select ARCH_HAVE_FPU select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 46008432f8e..c41d1fb1b27 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -202,7 +202,7 @@ void arm_boot(void) * to do that. */ - DEBUGASSERT((getreg(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0); + DEBUGASSERT((getreg32(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0); /* Clear all reset status flags on successful power on reset */ diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index 4ef3f0d2312..ed569c74b3a 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -289,7 +289,7 @@ void up_disable_irq(int channel) uint32_t bitmask; unsigned int regndx; - DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS) + DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS); /* Offset to account for the "phantom" vector */ @@ -321,7 +321,7 @@ void up_enable_irq(int channel) uint32_t bitmask; unsigned int regndx; - DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS) + DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS); /* Offset to account for the "phantom" vector */ @@ -363,7 +363,7 @@ void up_enable_fiq(int channel) uint32_t bitmask; unsigned int regndx; - DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS) + DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS); /* Offset to account for the "phantom" vector */ @@ -398,23 +398,4 @@ void up_enable_fiq(int channel) void up_ack_irq(int irq) { -#warning Missing logic } - -/**************************************************************************** - * Name: up_prioritize_irq - * - * Description: - * Set the priority of an IRQ. - * - * Since this API is not supported on all architectures, it should be - * avoided in common implementations where possible. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int channel, int priority) -{ -#warning Missing logic -} -#endif diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c index b97468d06dc..5ba829ff147 100644 --- a/arch/arm/src/tms570/tms570_lowputc.c +++ b/arch/arm/src/tms570/tms570_lowputc.c @@ -323,7 +323,7 @@ int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config) gcr1 = (SCI_GCR1_TIMING | SCI_GCR1_CLOCK | SCI_GCR1_RXENA | SCI_GCR1_TXENA); - DEBUGASSERT(config->parity >= && config->parity <= 2); + DEBUGASSERT(config->parity >= 0 && config->parity <= 2); if (config->parity == 1) { gcr1 |= SCI_GCR1_PARENA; From 9bcf27d15baa4532edaa10614f25177acaa4f3c1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 14:47:54 -0600 Subject: [PATCH 11/22] TMS570 is big-endian --- arch/arm/Kconfig | 1 + arch/arm/src/armv7-a/arm_head.S | 11 ++++++++++- arch/arm/src/armv7-r/arm_head.S | 11 ++++++++++- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c71310194da..60d291a8c74 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -237,6 +237,7 @@ config ARCH_CHIP_STR71X config ARCH_CHIP_TMS570 bool "TI TMS570" + select ENDIAN_BIG select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_RAMFUNCS select ARMV7R_MEMINIT diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index da3f8d6f2ec..5af4f17ddf7 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -410,7 +410,7 @@ __start: * replacement strategy. * SCTLR_HA Bit 17: Not supported by A5 * - * SCTLR_EE Bit 25: Little endian (reset value). + * SCTLR_EE Bit 25: 0=Little endian (reset value). * SCTLR_TRE Bit 28: No memory region remapping (reset value) * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). * SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value). @@ -477,6 +477,15 @@ __start: orr r0, r0, #(SCTLR_A) #endif +#ifdef CONFIG_ENDIAN_BIG + /* Big endian mode + * + * SCTLR_EE Bit 25: 1=Big endian. + */ + + orr r0, r0, #(SCTLR_EE) +#endif + #ifdef CPU_AFE_ENABLE /* AP[0:2] Permissions model * diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index a4bff790749..755c700f9b0 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -217,7 +217,7 @@ __start: * SCTLR_U Bit 22: Unaligned access model (always one) * * SCTLR_VE Bit 24: Interrupt Vectors Enable bit - * SCTLR_EE Bit 25: Little endian. + * SCTLR_EE Bit 25: 0=Little endian. * SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support * SCTLR_TE Bit 30: All exceptions handled in ARM state. * SCTLR_IE Bit 31: Instruction endian-ness. @@ -322,6 +322,15 @@ __start: orr r0, r0, #(SCTLR_VE) #endif +#ifdef CONFIG_ENDIAN_BIG + /* Big endian mode + * + * SCTLR_EE Bit 25: 1=Big endian. + */ + + orr r0, r0, #(SCTLR_EE) +#endif + #ifdef CPU_NONMASKABLE_FIQ /* Non-maskable FIQ support * From 46da8a07ef7e136f0c7d98ead80a8c3b4ba3c366 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 16:39:51 -0600 Subject: [PATCH 12/22] Costmetic changes from review of merge request --- arch/avr/src/avr/excptmacros.h | 36 +++++++++++++++-------------- arch/avr/src/avr/up_switchcontext.S | 3 +-- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/arch/avr/src/avr/excptmacros.h b/arch/avr/src/avr/excptmacros.h index 1abc14273d2..de5e0094193 100644 --- a/arch/avr/src/avr/excptmacros.h +++ b/arch/avr/src/avr/excptmacros.h @@ -141,7 +141,7 @@ * * At completion: * Register state is saved on the stack; All registers are available for usage except sp and - * r24 which still contains the IRQ number as set by the HANDLER macro. + * r24 which still contains the IRQ number as set by the HANDLER macro. * ********************************************************************************************/ @@ -418,7 +418,7 @@ * On completion: * All registers restored except for the PC with now resides at the top of the new stack * so that ret can be used to switch to the new context. (ret, not reti, becaue ret - * will preserve the restored interrupt state). + * will preserve the restored interrupt state). * ********************************************************************************************/ @@ -514,22 +514,23 @@ ld r0, x+ - /* The following control flow split is required to eliminate non-atomic - interrupt_enable - return sequence. - - NOTE: since actual returning is handled by this macro it has been removed - from up_fullcontextrestore function (up_switchcontext.S) - */ + /* The following control flow split is required to eliminate non-atomic + * interrupt_enable - return sequence. + * + * NOTE: since actual returning is handled by this macro it has been removed + * from up_fullcontextrestore function (up_switchcontext.S) + */ + + /* If interrupts shall be enabled go to 'restore remaining and reti' code + * otherwise just do 'restore remaining and ret' + */ - /* if interrupts shall be enabled go to 'restore remaining and reti' code - otherwise just do 'restore remaining and ret' */ - ld r24, x+ bst r24, SREG_I brts go_reti /* Restore the status register, interrupts are disabled */ - + out _SFR_IO_ADDR(SREG), r24 /* Restore r24-r25 - The temporary and IRQ number registers */ @@ -547,20 +548,21 @@ ret go_reti: - /* restore the Status Register with interrupts disabled - and exit with reti (that will set the Interrupt Enable) */ - + /* restore the Status Register with interrupts disabled + * and exit with reti (that will set the Interrupt Enable) + */ + andi r24, ~(1 << SREG_I) out _SFR_IO_ADDR(SREG), r24 ld r25, x+ ld r24, x+ - pop r27 + pop r27 pop r26 reti - + .endm /******************************************************************************************** diff --git a/arch/avr/src/avr/up_switchcontext.S b/arch/avr/src/avr/up_switchcontext.S index da5f45e6171..0f13e232214 100755 --- a/arch/avr/src/avr/up_switchcontext.S +++ b/arch/avr/src/avr/up_switchcontext.S @@ -130,8 +130,7 @@ up_fullcontextrestore: TCB_RESTORE - /* Retruning from the function is handled in TCB_RESTORE */ + /* Returning from the function is handled in TCB_RESTORE */ .endfunc .end - From 6d0650349ad7115327a8bd1f719851b63e24e9ef Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Dec 2015 18:13:01 -0600 Subject: [PATCH 13/22] Add support for ARM big-endian toolchains with prefix armeb- --- arch/arm/src/armv7-a/Toolchain.defs | 34 +++++++++++++++++------------ arch/arm/src/armv7-r/Toolchain.defs | 34 +++++++++++++++++------------ 2 files changed, 40 insertions(+), 28 deletions(-) diff --git a/arch/arm/src/armv7-a/Toolchain.defs b/arch/arm/src/armv7-a/Toolchain.defs index 91b4d9790e7..80fc6778267 100644 --- a/arch/arm/src/armv7-a/Toolchain.defs +++ b/arch/arm/src/armv7-a/Toolchain.defs @@ -94,15 +94,21 @@ ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) endif +ifeq ($(CONFIG_ENDIAN_BIG),y) + TARGET_ARCH := armeb +else + TARGET_ARCH := arm +endif + # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),BUILDROOT) ifeq ($(CONFIG_ARMV7A_OABI_TOOLCHAIN),y) - CROSSDEV ?= arm-nuttx-elf- - ARCROSSDEV ?= arm-nuttx-elf- + CROSSDEV ?= $(TARGET_ARCH)-nuttx-elf- + ARCROSSDEV ?= $(TARGET_ARCH)-nuttx-elf- else - CROSSDEV ?= arm-nuttx-eabi- - ARCROSSDEV ?= arm-nuttx-eabi- + CROSSDEV ?= $(TARGET_ARCH)-nuttx-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-nuttx-eabi- endif MAXOPTIMIZATION ?= -Os endif @@ -110,16 +116,16 @@ endif # CodeSourcery under Linux ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),CODESOURCERYL) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -O2 endif # CodeSourcery under Windows ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),CODESOURCERYW) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -O2 ifneq ($(CONFIG_WINDOWS_NATIVE),y) WINTOOL = y @@ -129,8 +135,8 @@ endif # devkitARM under Windows ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),DEVKITARM) - CROSSDEV ?= arm-eabi- - ARCROSSDEV ?= arm-eabi- + CROSSDEV ?= $(TARGET_ARCH)-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-eabi- ifneq ($(CONFIG_WINDOWS_NATIVE),y) WINTOOL = y endif @@ -139,16 +145,16 @@ endif # Generic GNU EABI toolchain on OS X, Linux or any typical Posix system ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),GNU_EABIL) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain under Windows ifeq ($(CONFIG_ARMV7A_TOOLCHAIN),GNU_EABIW) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -Os ifneq ($(CONFIG_WINDOWS_NATIVE),y) WINTOOL = y diff --git a/arch/arm/src/armv7-r/Toolchain.defs b/arch/arm/src/armv7-r/Toolchain.defs index b902c139bce..419a30a19fa 100644 --- a/arch/arm/src/armv7-r/Toolchain.defs +++ b/arch/arm/src/armv7-r/Toolchain.defs @@ -94,15 +94,21 @@ ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) endif +ifeq ($(CONFIG_ENDIAN_BIG),y) + TARGET_ARCH := armeb +else + TARGET_ARCH := arm +endif + # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),BUILDROOT) ifeq ($(CONFIG_ARMV7R_OABI_TOOLCHAIN),y) - CROSSDEV ?= arm-nuttx-elf- - ARCROSSDEV ?= arm-nuttx-elf- + CROSSDEV ?= $(TARGET_ARCH)-nuttx-elf- + ARCROSSDEV ?= $(TARGET_ARCH)-nuttx-elf- else - CROSSDEV ?= arm-nuttx-eabi- - ARCROSSDEV ?= arm-nuttx-eabi- + CROSSDEV ?= $(TARGET_ARCH)-nuttx-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-nuttx-eabi- endif MAXOPTIMIZATION ?= -Os endif @@ -110,16 +116,16 @@ endif # CodeSourcery under Linux ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),CODESOURCERYL) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -O2 endif # CodeSourcery under Windows ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),CODESOURCERYW) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -O2 ifneq ($(CONFIG_WINDOWS_NATIVE),y) WINTOOL = y @@ -129,8 +135,8 @@ endif # devkitARM under Windows ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),DEVKITARM) - CROSSDEV ?= arm-eabi- - ARCROSSDEV ?= arm-eabi- + CROSSDEV ?= $(TARGET_ARCH)-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-eabi- ifneq ($(CONFIG_WINDOWS_NATIVE),y) WINTOOL = y endif @@ -139,16 +145,16 @@ endif # Generic GNU EABI toolchain on OS X, Linux or any typical Posix system ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),GNU_EABIL) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -Os endif # Generic GNU EABI toolchain under Windows ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),GNU_EABIW) - CROSSDEV ?= arm-none-eabi- - ARCROSSDEV ?= arm-none-eabi- + CROSSDEV ?= $(TARGET_ARCH)-none-eabi- + ARCROSSDEV ?= $(TARGET_ARCH)-none-eabi- MAXOPTIMIZATION ?= -Os ifneq ($(CONFIG_WINDOWS_NATIVE),y) WINTOOL = y From e1b1f8023762a662e0790fa70b44fc02642d8944 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Dec 2015 07:54:43 -0600 Subject: [PATCH 14/22] TMS570: Add ESM initialization logic --- arch/arm/src/tms570/Make.defs | 4 +- arch/arm/src/tms570/chip/tms570_esm.h | 14 ++- arch/arm/src/tms570/tms570_boot.c | 5 + arch/arm/src/tms570/tms570_esm.c | 136 ++++++++++++++++++++++++++ arch/arm/src/tms570/tms570_esm.h | 80 +++++++++++++++ 5 files changed, 235 insertions(+), 4 deletions(-) create mode 100644 arch/arm/src/tms570/tms570_esm.c create mode 100644 arch/arm/src/tms570/tms570_esm.h diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index f6303268288..e33fa43c60d 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -104,8 +104,8 @@ CHIP_ASRCS = # SAMA5-specific C source files -CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_gio.c tms570_irq.c -CHIP_CSRCS += tms570_lowputc.c tms570_serial.c +CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_esm.c tms570_gio.c +CHIP_CSRCS += tms570_irq.c tms570_lowputc.c tms570_serial.c # Configuration dependent C and assembly language files diff --git a/arch/arm/src/tms570/chip/tms570_esm.h b/arch/arm/src/tms570/chip/tms570_esm.h index 450c469fdf7..cd1ac9877c6 100644 --- a/arch/arm/src/tms570/chip/tms570_esm.h +++ b/arch/arm/src/tms570/chip/tms570_esm.h @@ -65,7 +65,7 @@ #define TMS570_ESM_IECR1_OFFSET 0x000c /* ESM Interrupt Enable Clear/Status Register 1 */ #define TMS570_ESM_ILSR1_OFFSET 0x0010 /* Interrupt Level Set/Status Register 1 */ #define TMS570_ESM_ILCR1_OFFSET 0x0014 /* Interrupt Level Clear/Status Register 1 */ -#define TMS570_ESM_SR_OFFSET(n) (0x0018 + ((n) << 2)) /* n=0, 1, 2 */ +#define TMS570_ESM_SRA_OFFSET(n) (0x0018 + ((n) << 2)) /* n=0, 1, 2 */ # define TMS570_ESM_SR1_OFFSET 0x0018 /* ESM Status Register for group 1 */ # define TMS570_ESM_SR2_OFFSET 0x001c /* ESM Status Register for group 2 */ # define TMS570_ESM_SR3_OFFSET 0x0020 /* ESM Status Register for group 3 */ @@ -83,6 +83,11 @@ #define TMS570_ESM_ILSR4_OFFSET 0x0050 /* Interrupt Level Set/Status Register 4 */ #define TMS570_ESM_ILCR4_OFFSET 0x0054 /* Interrupt Level Clear/Status Register 4 */ #define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register 4 */ +#define TMS570_ESM_SRB_OFFSET(n) (0x0058 + (((n)-4) << 2)) /* n=4, 5, 6 */ +# define TMS570_ESM_SR4_OFFSET 0x0058 /* ESM Status Register for group 4 */ +# define TMS570_ESM_SR5_OFFSET 0x005c /* ESM Status Register for group 5 */ +# define TMS570_ESM_SR6_OFFSET 0x0060 /* ESM Status Register for group 6 */ +#define TMS570_ESM_SSR5_OFFSET 0x0064 /* ESM Status Shadow Register 5 */ /* Register Addresses *******************************************************************************/ @@ -92,7 +97,7 @@ #define TMS570_ESM_IECR1 (TMS570_ESM_BASE+TMS570_ESM_IECR1_OFFSET) #define TMS570_ESM_ILSR1 (TMS570_ESM_BASE+TMS570_ESM_ILSR1_OFFSET) #define TMS570_ESM_ILCR1 (TMS570_ESM_BASE+TMS570_ESM_ILCR1_OFFSET) -#define TMS570_ESM_SR(n) (TMS570_ESM_BASE+TMS570_ESM_SR_OFFSET(n)) +#define TMS570_ESM_SRA(n) (TMS570_ESM_BASE+TMS570_ESM_SRA_OFFSET(n)) # define TMS570_ESM_SR1 (TMS570_ESM_BASE+TMS570_ESM_SR1_OFFSET) # define TMS570_ESM_SR2 (TMS570_ESM_BASE+TMS570_ESM_SR2_OFFSET) # define TMS570_ESM_SR3 (TMS570_ESM_BASE+TMS570_ESM_SR3_OFFSET) @@ -110,6 +115,11 @@ #define TMS570_ESM_ILSR4 (TMS570_ESM_BASE+TMS570_ESM_ILSR4_OFFSET) #define TMS570_ESM_ILCR4 (TMS570_ESM_BASE+TMS570_ESM_ILCR4_OFFSET) #define TMS570_ESM_SR4 (TMS570_ESM_BASE+TMS570_ESM_SR4_OFFSET) +#define TMS570_ESM_SRB(n) (TMS570_ESM_BASE+TMS570_ESM_SRB_OFFSET(n)) +# define TMS570_ESM_SR4 (TMS570_ESM_BASE+TMS570_ESM_SR4_OFFSET) +# define TMS570_ESM_SR5 (TMS570_ESM_BASE+TMS570_ESM_SR5_OFFSET) +# define TMS570_ESM_SR6 (TMS570_ESM_BASE+TMS570_ESM_SR6_OFFSET) +#define TMS570_ESM_SSR5 (TMS570_ESM_BASE+TMS570_ESM_SSR5_OFFSET) /* Register Bit-Field Definitions *******************************************************************/ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index c41d1fb1b27..3b4102451d2 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -66,6 +66,7 @@ #include "tms570_clockconfig.h" #include "tms570_selftest.h" #include "tms570_gio.h" +#include "tms570_esm.h" #include "tms570_boot.h" /**************************************************************************** @@ -310,6 +311,10 @@ void arm_boot(void) #endif ); + /* Configure system response to error conditions */ + + tms570_esm_initialize(); + #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c new file mode 100644 index 00000000000..cbbaa1e4f27 --- /dev/null +++ b/arch/arm/src/tms570/tms570_esm.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/src/tms570/tms570_esm.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from the TI "Project0" sample code which has a compatible 3- + * clause BSD license: + * + * Copyright (c) 2012, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX, Texas Instruments Incorporated, nor the + * names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "up_arch.h" + +#include "chip/tms570_esm.h" +#include "tms570_esm.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tms570_esm_initialize + * + * Description: + * Initialize the ESM. + * + ****************************************************************************/ + +int tms570_esm_initialize(void) +{ + uint32_t regval; + + /* Disable error pin channels */ + + putreg32(0xffffffff, TMS570_ESM_DEPAPR1); + putreg32(0xffffffff, TMS570_ESM_IEPCR4); + + /* Disable interrupts */ + + putreg32(0xffffffff, TMS570_ESM_IECR1); + putreg32(0xffffffff, TMS570_ESM_IECR4); + + /* Clear error status flags */ + + putreg32(0xffffffff, TMS570_ESM_SR1); + putreg32(0xffffffff, TMS570_ESM_SR2); + putreg32(0xffffffff, TMS570_ESM_SSR2); + putreg32(0xffffffff, TMS570_ESM_SR3); + putreg32(0xffffffff, TMS570_ESM_SR4); + putreg32(0xffffffff, TMS570_ESM_SR5); + putreg32(0xffffffff, TMS570_ESM_SSR5); + putreg32(0xffffffff, TMS570_ESM_SR6); + + /* Setup LPC preload */ + + putreg32(16384 - 1, TMS570_ESM_LTCPR); + + /* Reset error pin */ + + regval = getreg32(TMS570_ESM_EPSR); + if (regval == 0) + { + putreg32(5, TMS570_ESM_EKR); + } + else + { + putreg32(0, TMS570_ESM_EKR); + } + + /* Clear interrupt level */ + + putreg32(0xffffffff, TMS570_ESM_ILCR1); + putreg32(0xffffffff, TMS570_ESM_ILCR4); + + /* Set interrupt level */ + + putreg32(0, TMS570_ESM_ILSR1); + putreg32(0, TMS570_ESM_ILSR4); + + /* Enable error pin channels */ + + putreg32(0, TMS570_ESM_EEPAPR1); + putreg32(0, TMS570_ESM_IEPSR4); + + /* Enable interrupts */ + + putreg32(0, TMS570_ESM_IESR1); + putreg32(0, TMS570_ESM_IESR4); + return OK; +} diff --git a/arch/arm/src/tms570/tms570_esm.h b/arch/arm/src/tms570/tms570_esm.h new file mode 100644 index 00000000000..b5fd706c8e8 --- /dev/null +++ b/arch/arm/src/tms570/tms570_esm.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/tms570/tms570_esm.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_TMS570_ESM_H +#define __ARCH_ARM_SRC_TMS570_TMS570_ESM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: tms570_esm_initialize + * + * Description: + * Initialize the ESM. + * + ****************************************************************************/ + +int tms570_esm_initialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_TMS570_TMS570_ESM_H */ From e0214f9d626397c7185a0f398745925cd11b2378 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Dec 2015 08:32:53 -0600 Subject: [PATCH 15/22] ARMv7-R: Remove some CONFIG_PAGING logic left over from ARMv7-A leverage --- arch/arm/src/armv7-r/arm_dataabort.c | 106 ----------------------- arch/arm/src/armv7-r/arm_prefetchabort.c | 74 ---------------- 2 files changed, 180 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c index 86280e10e8d..e48c4c9afa0 100644 --- a/arch/arm/src/armv7-r/arm_dataabort.c +++ b/arch/arm/src/armv7-r/arm_dataabort.c @@ -58,23 +58,6 @@ #include "sched/sched.h" #include "up_internal.h" -#ifdef CONFIG_PAGING -# include -# include "arm.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -84,10 +67,6 @@ * * Input parameters: * regs - The standard, ARM register save array. - * - * If CONFIG_PAGING is selected in the NuttX configuration file, then these - * additional input values are expected: - * * dfar - Fault address register. * dfsr - Fault status register. * @@ -97,89 +76,6 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING - -uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) -{ - DFAR struct tcb_s *tcb = (DFAR struct tcb_s *)g_readytorun.head; - uint32_t *savestate; - - /* Save the saved processor context in current_regs where it can be accessed - * for register dumps and possibly context switching. - */ - - savestate = (uint32_t *)current_regs; - current_regs = regs; - - /* In the NuttX on-demand paging implementation, only the read-only, .text - * section is paged. However, the ARM compiler generated PC-relative data - * fetches from within the .text sections. Also, it is customary to locate - * read-only data (.rodata) within the same section as .text so that it - * does not require copying to RAM. Misses in either of these case should - * cause a data abort. - * - * We are only interested in data aborts due to page translations faults. - * Sections should already be in place and permissions should already be - * be set correctly (to read-only) so any other data abort reason is a - * fatal error. - */ - - pglldbg("DFSR: %08x DFAR: %08x\n", dfsr, dfar); - if ((dfsr & FSR_MASK) != FSR_PAGE) - { - goto segfault; - } - - /* Check the (virtual) address of data that caused the data abort. When - * the exception occurred, this address was provided in the DFAR register. - * (It has not yet been saved in the register context save area). - */ - - pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND); - if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND) - { - goto segfault; - } - - /* Save the offending data address as the fault address in the TCB of - * the currently task. This fault address is also used by the prefetch - * abort handling; this will allow common paging logic for both - * prefetch and data aborts. - */ - - tcb->xcp.dfar = regs[REG_R15]; - - /* Call pg_miss() to schedule the page fill. A consequences of this - * call are: - * - * (1) The currently executing task will be blocked and saved on - * on the g_waitingforfill task list. - * (2) An interrupt-level context switch will occur so that when - * this function returns, it will return to a different task, - * most likely the page fill worker thread. - * (3) The page fill worker task has been signalled and should - * execute immediately when we return from this exception. - */ - - pg_miss(); - - /* Restore the previous value of current_regs. NULL would indicate that - * we are no longer in an interrupt handler. It will be non-NULL if we - * are returning from a nested interrupt. - */ - - current_regs = savestate; - return regs; - -segfault: - lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", - regs[REG_PC], dfar, dfsr); - PANIC(); - return regs; /* To keep the compiler happy */ -} - -#else /* CONFIG_PAGING */ - uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) { /* Save the saved processor context in current_regs where it can be accessed @@ -195,5 +91,3 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) PANIC(); return regs; /* To keep the compiler happy */ } - -#endif /* CONFIG_PAGING */ diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c index b3931890e38..ced1c68ea58 100644 --- a/arch/arm/src/armv7-r/arm_prefetchabort.c +++ b/arch/arm/src/armv7-r/arm_prefetchabort.c @@ -54,9 +54,6 @@ #include #include -#ifdef CONFIG_PAGING -# include -#endif #include "sched/sched.h" #include "up_internal.h" @@ -87,75 +84,6 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING - -uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) -{ - uint32_t *savestate; - - /* Save the saved processor context in current_regs where it can be accessed - * for register dumps and possibly context switching. - */ - - savestate = (uint32_t *)current_regs; - current_regs = regs; - - /* Get the (virtual) address of instruction that caused the prefetch abort. - * When the exception occurred, this address was provided in the lr register - * and this value was saved in the context save area as the PC at the - * REG_R15 index. - * - * Check to see if this miss address is within the configured range of - * virtual addresses. - */ - - pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n", - regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND); - - if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND) - { - /* Save the offending PC as the fault address in the TCB of the currently - * executing task. This value is, of course, already known in regs[REG_R15], - * but saving it in this location will allow common paging logic for both - * prefetch and data aborts. - */ - - FAR struct tcb_s *tcb = (FAR struct tcb_s *)g_readytorun.head; - tcb->xcp.far = regs[REG_R15]; - - /* Call pg_miss() to schedule the page fill. A consequences of this - * call are: - * - * (1) The currently executing task will be blocked and saved on - * on the g_waitingforfill task list. - * (2) An interrupt-level context switch will occur so that when - * this function returns, it will return to a different task, - * most likely the page fill worker thread. - * (3) The page fill worker task has been signalled and should - * execute immediately when we return from this exception. - */ - - pg_miss(); - - /* Restore the previous value of current_regs. NULL would indicate that - * we are no longer in an interrupt handler. It will be non-NULL if we - * are returning from a nested interrupt. - */ - - current_regs = savestate; - } - else - { - lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", - regs[REG_PC], ifar, ifsr); - PANIC(); - } - - return regs; -} - -#else /* CONFIG_PAGING */ - uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) { /* Save the saved processor context in current_regs where it can be accessed @@ -171,5 +99,3 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) PANIC(); return regs; /* To keep the compiler happy */ } - -#endif /* CONFIG_PAGING */ From c3758286d758a24f402f902434647cf89e1e13d6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Dec 2015 08:34:14 -0600 Subject: [PATCH 16/22] TMS570: Add ESM interrupt handler --- arch/arm/src/armv7-r/arm_prefetchabort.c | 12 --------- arch/arm/src/tms570/tms570_esm.c | 33 +++++++++++++++++++++--- arch/arm/src/tms570/tms570_esm.h | 10 +++++++ arch/arm/src/tms570/tms570_irq.c | 12 ++++++++- 4 files changed, 50 insertions(+), 17 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c index ced1c68ea58..1e3171a80f5 100644 --- a/arch/arm/src/armv7-r/arm_prefetchabort.c +++ b/arch/arm/src/armv7-r/arm_prefetchabort.c @@ -58,18 +58,6 @@ #include "sched/sched.h" #include "up_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c index cbbaa1e4f27..b7f17ab52b4 100644 --- a/arch/arm/src/tms570/tms570_esm.c +++ b/arch/arm/src/tms570/tms570_esm.c @@ -48,14 +48,16 @@ #include #include +#include +#include + +#include "up_internal.h" #include "up_arch.h" #include "chip/tms570_esm.h" #include "tms570_esm.h" -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -113,12 +115,12 @@ int tms570_esm_initialize(void) putreg32(0, TMS570_ESM_EKR); } - /* Clear interrupt level */ + /* Clear interrupt level. All channels set to low level interrupt. */ putreg32(0xffffffff, TMS570_ESM_ILCR1); putreg32(0xffffffff, TMS570_ESM_ILCR4); - /* Set interrupt level */ + /* Set interrupt level (Writing zero does nothing) */ putreg32(0, TMS570_ESM_ILSR1); putreg32(0, TMS570_ESM_ILSR4); @@ -134,3 +136,26 @@ int tms570_esm_initialize(void) putreg32(0, TMS570_ESM_IESR4); return OK; } + +/**************************************************************************** + * Name: tms570_esm_interrupt + * + * Description: + * ESM interrupt handler + * + ****************************************************************************/ + +int tms570_esm_interrupt(int irq, void *context) +{ + /* Save the saved processor context in current_regs where it can be accessed + * for register dumps and possibly context switching. + */ + + current_regs = (uint32_t *)context; + + /* Crash -- possibly showing diagnostic debug information. */ + + lldbg("ESM Interrupt. PC: %08x\n", current_regs[REG_PC]); + PANIC(); + return OK; /* To keep the compiler happy */ +} diff --git a/arch/arm/src/tms570/tms570_esm.h b/arch/arm/src/tms570/tms570_esm.h index b5fd706c8e8..7222cc17fed 100644 --- a/arch/arm/src/tms570/tms570_esm.h +++ b/arch/arm/src/tms570/tms570_esm.h @@ -71,6 +71,16 @@ extern "C" int tms570_esm_initialize(void); +/**************************************************************************** + * Name: tms570_esm_interrupt + * + * Description: + * ESM interrupt handler + * + ****************************************************************************/ + +int tms570_esm_interrupt(int irq, void *context); + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index ed569c74b3a..af617894ae7 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -53,6 +53,7 @@ #include "chip/tms570_vim.h" #include "tms570_gio.h" +#include "tms570_esm.h" #include "tms570_irq.h" /**************************************************************************** @@ -182,7 +183,16 @@ void up_irqinitialize(void) tms570_gioirq_initialize(); #endif - /* And finally, enable interrupts */ + /* Attach and enable ESM interrupts. The high level interrupt is really + * an NMI. + */ + + (void)irq_attach(TMS570_REQ_ESMHIGH, tms570_esm_interrupt); + (void)irq_attach(TMS570_REQ_ESMLO, tms570_esm_interrupt); + up_enable_irq(TMS570_REQ_ESMHIGH); + up_enable_irq(TMS570_REQ_ESMLO); + + /* And finally, enable interrupts globally */ irqenable(); #endif From 00f70474bb59ca91512d396cf9d910da05057656 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Dec 2015 08:30:03 -0600 Subject: [PATCH 17/22] TMS570: Power-up errcheck assertion is a headache --- arch/arm/src/tms570/chip/tms570_sys.h | 1 + arch/arm/src/tms570/tms570_boot.c | 55 +++++++++++++++++++++------ 2 files changed, 44 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/chip/tms570_sys.h index af6f4c9752d..8ed50d1b4a3 100644 --- a/arch/arm/src/tms570/chip/tms570_sys.h +++ b/arch/arm/src/tms570/chip/tms570_sys.h @@ -606,6 +606,7 @@ #define SYS_ESR_PORST (1 << 15) /* Bit 15: Power-up reset */ #define SYS_ESR_RSTALL (0x0000e038) +#define SYS_ESR_FAILALL (0x00006000) /* System Test Abort Status Register */ #define SYS_TASR_ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 3b4102451d2..489613745fb 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -110,6 +110,47 @@ static inline void tms570_event_export(void) cp15_wrpmcr(pmcr); } +/**************************************************************************** + * Name: tms570_check_reset + * + * Description: + * Assert if we go here through any mechanism other than a power-on reset. + * + ****************************************************************************/ + +static inline void tms570_check_reset(void) +{ +#ifdef CONFIG_DEBUG + uint32_t regval; + + /* Read from the system exception status register to identify the cause of + * the CPU reset. + */ + + regval = getreg32(TMS570_SYS_ESR); + + /* Clear all reset status flags on normal reset */ + + regval = getreg32(TMS570_SYS_ESR); + putreg32(SYS_ESR_RSTALL, TMS570_SYS_ESR); + + /* Check for abnormal reset causes: Oscillator failures or watchdog + * timers. Ignore normal reset causes: External reset, software reset, CPU + * reset, power-on reset + * + * REVISIT: The reset cause is not used in the current design. But if you + * need to know the cause of the reset, here is where you would want to + * do that. + */ + + ASSERT((regval & SYS_ESR_FAILALL) == 0); +#else + /* Clear all reset status flags */ + + putreg32(SYS_ESR_RSTALL, TMS570_SYS_ESR); +#endif +} + /**************************************************************************** * Name: tms570_enable_ramecc * @@ -195,19 +236,9 @@ void arm_boot(void) tms570_event_export(); - /* Read from the system exception status register to identify the cause of - * the CPU reset. - * - * REVISIT: This logic is not used in the current design. But if you - * need to know the cause of the reset, here is where you would want - * to do that. - */ + /* Verify that we got here via a power-up reset */ - DEBUGASSERT((getreg32(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0); - - /* Clear all reset status flags on successful power on reset */ - - putreg32(SYS_ESR_RSTALL, TMS570_SYS_ESR); + tms570_check_reset(); /* Check if there were ESM group3 errors during power-up. * From ae0e6b4096fa1b764b839707c38e398f20651100 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Dec 2015 16:15:33 -0600 Subject: [PATCH 18/22] ARMv7-R and TMS570: Re-orider some initialization logic. __start used to called arm_boot() which would return. Then __start would call os_start(). That won't work for the TMS570 if is does a destructive memory tested because the return information will be lost in the stack. Also comment a nuisance assertion. The assertion is probably correct but certainly a nuisance during initial testing --- arch/arm/src/armv7-r/arm.h | 31 +++++++++++ arch/arm/src/armv7-r/arm_head.S | 44 ++++------------ arch/arm/src/tms570/tms570_boot.c | 85 ++++++++++++++++++++++++++++--- 3 files changed, 118 insertions(+), 42 deletions(-) diff --git a/arch/arm/src/armv7-r/arm.h b/arch/arm/src/armv7-r/arm.h index 1c0155e4a31..a2d64dc50fc 100644 --- a/arch/arm/src/armv7-r/arm.h +++ b/arch/arm/src/armv7-r/arm.h @@ -46,6 +46,10 @@ * Included Files ****************************************************************************/ +#ifndef __ASSEMBLY__ +# include +#endif /* __ASSEMBLY__ */ + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -109,6 +113,33 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Name: arm_boot + * + * Description: + * Complete boot operations started in arm_head.S + * + * Boot Sequence + * + * 1. The __start entry point in armv7-r/arm_head.S is invoked upon power- + * on reset. + * 2. __start prepares CPU for code execution. + * 3a. If CONFIG_ARMV7R_MEMINIT is not defined, then __start will prepare + * memory resources by calling arm_data_initialize() and will then + * branch to this function. + * 3b. Otherwise, this function will be called without having initialized + * memory resources! We need to be very careful in this case. This + * function will perform MCU- and board-specific initialization which, + * among other things, must initialize memories. After initializatino + ( of the memories, this function will call arm_data_initialize() to + * initialize the memory resources + * 4. This function will then branch to os_start() to start the operating + * system. + * + ****************************************************************************/ + +void arm_boot(void) noreturn_function; + /**************************************************************************** * Name: arm_data_initialize * diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index 755c700f9b0..688ffebcd92 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -117,9 +117,7 @@ /* Imported symbols */ - .global arm_boot /* Called just before os_start */ - .global os_start /* Start the operating system */ - .global arm_data_initialize /* Perform C data initialization */ + .global arm_boot /* Branch to continue initialization in C */ .global _sbss /* Start of .bss in RAM */ .global _ebss /* End+1 of .bss in RAM */ @@ -137,7 +135,8 @@ /* Exported symbols */ .global __start /* Power-up/Reset entry point */ - .globl g_idle_topstack /* Top of the initial/IDLE stack */ + .global arm_data_initialize /* Perform C data initialization */ + .global g_idle_topstack /* Top of the initial/IDLE stack */ #ifdef CONFIG_ARCH_FPU .cpu cortex-r4 @@ -373,7 +372,8 @@ __start: /* Initialize .bss and .data ONLY if .bss and .data lie in RAM that is * ready to use. Other memory, such as SDRAM, must be initialized before * it can be used. arm_boot() will perform that memory initialization and - * .bss and .data can be initialized after arm_boot() returns. + * .bss and .data can be initialized by arm_boot() by calling this + * arm_data_initialize() later. */ bl arm_data_initialize @@ -382,43 +382,17 @@ __start: /* Perform early C-level, platform-specific initialization. Logic * within arm_boot() must configure SDRAM and call arm_data_initialize() * if CONFIG_ARMV7R_MEMINIT=y. + * + * This function does not return. It must give control to os_start() + * at the completion of its initialization. */ - bl arm_boot - -#ifdef CONFIG_STACK_COLORATION - /* Write a known value to the IDLE thread stack to support stack - * monitoring logic - */ - - adr r3, .Lstkinit - ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */ - -2: /* Top of the loop */ - sub r1, r1, #1 /* R1 = Number of words remaining */ - cmp r1, #0 /* Check (nwords == 0) */ - str r2, [r0], #4 /* Save stack color word, increment stack address */ - bne 2b /* Bottom of the loop */ - -#endif - - /* Finally branch to the OS entry point */ - - mov lr, #0 /* LR = return address (none) */ - b os_start /* Branch to os_start */ + b arm_boot /* .text Data */ .Lstackpointer: .long IDLE_STACK_TOP - -#ifdef CONFIG_STACK_COLORATION - .type .Lstkinit, %object -.Lstkinit: - .long IDLE_STACK_BASE /* Beginning of the IDLE stack, then words of IDLE stack */ - .long (CONFIG_IDLETHREAD_STACKSIZE >> 2) - .long STACK_COLOR /* Stack coloration word */ -#endif .size __start, .-__start /*************************************************************************** diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 489613745fb..3b3390f247b 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -60,6 +60,8 @@ #include "up_internal.h" #include "up_arch.h" +#include + #include "chip/tms570_sys.h" #include "chip/tms570_esm.h" #include "chip/tms570_pbist.h" @@ -143,7 +145,12 @@ static inline void tms570_check_reset(void) * do that. */ +#if 0 ASSERT((regval & SYS_ESR_FAILALL) == 0); +#else + UNUSED(regval); +#endif + #else /* Clear all reset status flags */ @@ -197,6 +204,49 @@ static void tms570_memory_initialize(uint32_t ramset) putreg32(SYS_MINITGCR_DISABLE, TMS570_SYS_MINITGCR); } +/**************************************************************************** + * Name: go_os_start + * + * Description: + * Set the IDLE stack to the + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) + naked_function noreturn_function; + +static void go_os_start(void *pv, unsigned int nbytes) +{ + /* Set the IDLE stack to the stack coloration value then jump to + * os_start(). We take extreme care here because were currently + * executing on this stack. + * + * We want to avoid sneak stack access generated by the compiler. + */ + + __asm__ __volatile__ + ( + "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ + "\tbeq 2f\n" /* (should not happen) */ + + "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ + "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ + "\tmovt r2, #0xdead\n" + + "1:\n" /* Top of the loop */ + "\tsub r1, r1, #1\n" /* R1 nwords-- */ + "\tcmp r1, #0\n" /* Check (nwords == 0) */ + "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ + "\tbne 1b\n" /* Bottom of the loop */ + + "2:\n" + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ + ); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -214,15 +264,15 @@ static void tms570_memory_initialize(uint32_t ramset) * 2. __start prepares CPU for code execution. * 3a. If CONFIG_ARMV7R_MEMINIT is not defined, then __start will prepare * memory resources by calling arm_data_initialize() and will then - * call this function. + * branch this function. * 3b. Otherwise, this function will be called without having initialized * memory resources! We need to be very careful in this case. Here, * this function will call tms570_boardinitialize() which, among other - * things, much initialize SDRAM memory. Upon return, this function - * will call arm_data_initialize() to initialize the memory resources - * 4. This function will initialize all TMS570-specific resources and - * return to __start. - * 4. _start will then branch to os_start() to start the operating system. + * things, must initialize SDRAM memory. After initializatino of the + * memories, this function will call arm_data_initialize() to + * initialize the memory resources + * 4. This function will then branch to os_start() to start the operating + * system. * ****************************************************************************/ @@ -259,7 +309,12 @@ void arm_boot(void) tms570_clockconfig(); #ifdef CONFIG_TMS570_SELFTEST - /* Run a diagnostic check on the memory self-test controller. */ + /* Run a diagnostic check on the memory self-test controller. + * + * REVISIT: This is a destructive test. It will most likely clobber the + * current stack content and result in a failure if this function were to + * attempt to return. + */ tms570_memtest_selftest(); @@ -382,4 +437,20 @@ void arm_boot(void) /* Perform common, low-level chip initialization (might do nothing) */ tms570_lowsetup(); + + /* Then start NuttX */ + +#ifdef CONFIG_STACK_COLORATION + /* Set the IDLE stack to the coloration value and jump into os_start() */ + + go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); +#else + /* Call os_start() */ + + os_start(); + + /* Shouldn't get here */ + + for (; ; ); +#endif } From e7d7036cb90d7a6b729256efdf3f41b86565448e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Dec 2015 16:32:34 -0600 Subject: [PATCH 19/22] ARMv7-R: L2CC_VBASE->L2CC_BASE --- arch/arm/src/armv7-r/l2cc_pl310.h | 68 +++++++++++++++---------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/src/armv7-r/l2cc_pl310.h b/arch/arm/src/armv7-r/l2cc_pl310.h index 12431ace378..51410b19231 100644 --- a/arch/arm/src/armv7-r/l2cc_pl310.h +++ b/arch/arm/src/armv7-r/l2cc_pl310.h @@ -49,7 +49,7 @@ #include /* The base address of the L2CC implementation must be provided in the chip.h - * header file as L2CC_VBASE. + * header file as L2CC_BASE. */ #include "chip/chip.h" @@ -127,43 +127,43 @@ /* L2CC Register Addresses **********************************************************/ -#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET) -#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET) -#define L2CC_CR (L2CC_VBASE+L2CC_CR_OFFSET) -#define L2CC_ACR (L2CC_VBASE+L2CC_ACR_OFFSET) -#define L2CC_TRCR (L2CC_VBASE+L2CC_TRCR_OFFSET) -#define L2CC_DRCR (L2CC_VBASE+L2CC_DRCR_OFFSET) -#define L2CC_ECR (L2CC_VBASE+L2CC_ECR_OFFSET) -#define L2CC_ECFGR1 (L2CC_VBASE+L2CC_ECFGR1_OFFSET) -#define L2CC_ECFGR0 (L2CC_VBASE+L2CC_ECFGR0_OFFSET) -#define L2CC_EVR1 (L2CC_VBASE+L2CC_EVR1_OFFSET) -#define L2CC_EVR0 (L2CC_VBASE+L2CC_EVR0_OFFSET) -#define L2CC_IMR (L2CC_VBASE+L2CC_IMR_OFFSET) -#define L2CC_MISR (L2CC_VBASE+L2CC_MISR_OFFSET) -#define L2CC_RISR (L2CC_VBASE+L2CC_RISR_OFFSET) -#define L2CC_ICR (L2CC_VBASE+L2CC_ICR_OFFSET) -#define L2CC_CSR (L2CC_VBASE+L2CC_CSR_OFFSET) -#define L2CC_IPALR (L2CC_VBASE+L2CC_IPALR_OFFSET) -#define L2CC_IWR (L2CC_VBASE+L2CC_IWR_OFFSET) -#define L2CC_CPALR (L2CC_VBASE+L2CC_CPALR_OFFSET) -#define L2CC_CIR (L2CC_VBASE+L2CC_CIR_OFFSET) -#define L2CC_CWR (L2CC_VBASE+L2CC_CWR_OFFSET) -#define L2CC_CIPALR (L2CC_VBASE+L2CC_CIPALR_OFFSET) -#define L2CC_CIIR (L2CC_VBASE+L2CC_CIIR_OFFSET) -#define L2CC_CIWR (L2CC_VBASE+L2CC_CIWR_OFFSET) -#define L2CC_DLKR(n) (L2CC_VBASE+L2CC_DLKR_OFFSET(n)) -#define L2CC_ILKR(n) (L2CC_VBASE+L2CC_ILKR_OFFSET(n)) +#define L2CC_IDR (L2CC_BASE+L2CC_IDR_OFFSET) +#define L2CC_TYPR (L2CC_BASE+L2CC_TYPR_OFFSET) +#define L2CC_CR (L2CC_BASE+L2CC_CR_OFFSET) +#define L2CC_ACR (L2CC_BASE+L2CC_ACR_OFFSET) +#define L2CC_TRCR (L2CC_BASE+L2CC_TRCR_OFFSET) +#define L2CC_DRCR (L2CC_BASE+L2CC_DRCR_OFFSET) +#define L2CC_ECR (L2CC_BASE+L2CC_ECR_OFFSET) +#define L2CC_ECFGR1 (L2CC_BASE+L2CC_ECFGR1_OFFSET) +#define L2CC_ECFGR0 (L2CC_BASE+L2CC_ECFGR0_OFFSET) +#define L2CC_EVR1 (L2CC_BASE+L2CC_EVR1_OFFSET) +#define L2CC_EVR0 (L2CC_BASE+L2CC_EVR0_OFFSET) +#define L2CC_IMR (L2CC_BASE+L2CC_IMR_OFFSET) +#define L2CC_MISR (L2CC_BASE+L2CC_MISR_OFFSET) +#define L2CC_RISR (L2CC_BASE+L2CC_RISR_OFFSET) +#define L2CC_ICR (L2CC_BASE+L2CC_ICR_OFFSET) +#define L2CC_CSR (L2CC_BASE+L2CC_CSR_OFFSET) +#define L2CC_IPALR (L2CC_BASE+L2CC_IPALR_OFFSET) +#define L2CC_IWR (L2CC_BASE+L2CC_IWR_OFFSET) +#define L2CC_CPALR (L2CC_BASE+L2CC_CPALR_OFFSET) +#define L2CC_CIR (L2CC_BASE+L2CC_CIR_OFFSET) +#define L2CC_CWR (L2CC_BASE+L2CC_CWR_OFFSET) +#define L2CC_CIPALR (L2CC_BASE+L2CC_CIPALR_OFFSET) +#define L2CC_CIIR (L2CC_BASE+L2CC_CIIR_OFFSET) +#define L2CC_CIWR (L2CC_BASE+L2CC_CIWR_OFFSET) +#define L2CC_DLKR(n) (L2CC_BASE+L2CC_DLKR_OFFSET(n)) +#define L2CC_ILKR(n) (L2CC_BASE+L2CC_ILKR_OFFSET(n)) #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE -# define L2CC_LKLN (L2CC_VBASE+L2CC_LKLN_OFFSET) -# define L2CC_UNLKW (L2CC_VBASE+L2CC_UNLKW_OFFSET) +# define L2CC_LKLN (L2CC_BASE+L2CC_LKLN_OFFSET) +# define L2CC_UNLKW (L2CC_BASE+L2CC_UNLKW_OFFSET) #endif -#define L2CC_FLSTRT (L2CC_VBASE+L2CC_FLSTRT_OFFSET) -#define L2CC_FLEND (L2CC_VBASE+L2CC_FLEND_OFFSET) -#define L2CC_DCR (L2CC_VBASE+L2CC_DCR_OFFSET) -#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET) -#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET) +#define L2CC_FLSTRT (L2CC_BASE+L2CC_FLSTRT_OFFSET) +#define L2CC_FLEND (L2CC_BASE+L2CC_FLEND_OFFSET) +#define L2CC_DCR (L2CC_BASE+L2CC_DCR_OFFSET) +#define L2CC_PCR (L2CC_BASE+L2CC_PCR_OFFSET) +#define L2CC_POWCR (L2CC_BASE+L2CC_POWCR_OFFSET) /* L2CC Register Bit Definitions ****************************************************/ From d9737f0645443f6b5bdb3e7a5fd305673764672a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Dec 2015 07:56:22 -0600 Subject: [PATCH 20/22] TMS570: reset stack pointer before calling os_start --- arch/arm/src/armv7-r/arm_head.S | 5 ++++ arch/arm/src/tms570/tms570_boot.c | 50 ++++++++++++++++++++----------- 2 files changed, 37 insertions(+), 18 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index 688ffebcd92..a081d230b63 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -385,6 +385,11 @@ __start: * * This function does not return. It must give control to os_start() * at the completion of its initialization. + * + * Why not just call arm_boot() and branch to os_start() when it returns? + * If the stack pointer initialized above lies in SDRAM, then that may + * not be possible. Also, in the special case of the TMS570, it may + * perform a destructive test, losing the pushed content of the stack. */ b arm_boot diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 3b3390f247b..725338faced 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -208,7 +208,7 @@ static void tms570_memory_initialize(uint32_t ramset) * Name: go_os_start * * Description: - * Set the IDLE stack to the + * Re-initialize the stack and frame pointers and branch to OS start. * ****************************************************************************/ @@ -227,22 +227,40 @@ static void go_os_start(void *pv, unsigned int nbytes) __asm__ __volatile__ ( - "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ - "\tbeq 2f\n" /* (should not happen) */ + "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ + "\tbeq 2f\n" /* (should not happen) */ - "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ - "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ + "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ + "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ "\tmovt r2, #0xdead\n" - "1:\n" /* Top of the loop */ - "\tsub r1, r1, #1\n" /* R1 nwords-- */ - "\tcmp r1, #0\n" /* Check (nwords == 0) */ - "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ - "\tbne 1b\n" /* Bottom of the loop */ + "1:\n" /* Top of the loop */ + "\tsub r1, r1, #1\n" /* R1 nwords-- */ + "\tcmp r1, #0\n" /* Check (nwords == 0) */ + "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ + "\tbne 1b\n" /* Bottom of the loop */ "2:\n" - "\tmov r14, #0\n" /* LR = return address (none) */ - "\tb os_start\n" /* Branch to os_start */ + "\tldr sp, =g_idle_topstack\n" /* Reset the stack pointer */ + "\tmov fp, #0\n" /* Reset the frame pointer */ + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ + ); +} + +#else +static void go_os_start(void) naked_function noreturn_function; + +static void go_os_start(void) +{ + /* Reset the stack/frame pointer and jump to os_start(). */ + + __asm__ __volatile__ + ( + "\tldr sp, =g_idle_topstack\n" /* Reset the stack pointer */ + "\tmov fp, #0\n" /* Reset the frame pointer */ + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ ); } #endif @@ -445,12 +463,8 @@ void arm_boot(void) go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE); #else - /* Call os_start() */ + /* Branch to os_start(), resetting the stack and frame pointers. */ - os_start(); - - /* Shouldn't get here */ - - for (; ; ); + go_os_start(); #endif } From 7a0d6cd7cab3a4675c612bcc771585f7ded6d2b5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Dec 2015 08:10:16 -0600 Subject: [PATCH 21/22] TMS570: Fix an error introduced in last commit --- arch/arm/src/tms570/tms570_boot.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index 725338faced..a3e949d98c4 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -241,7 +241,8 @@ static void go_os_start(void *pv, unsigned int nbytes) "\tbne 1b\n" /* Bottom of the loop */ "2:\n" - "\tldr sp, =g_idle_topstack\n" /* Reset the stack pointer */ + "\tldr ip, =g_idle_topstack\n" /* IP=address of g_idle_topstack */ + "\tldr sp, [ip]\n" /* Reset the stack pointer */ "\tmov fp, #0\n" /* Reset the frame pointer */ "\tmov r14, #0\n" /* LR = return address (none) */ "\tb os_start\n" /* Branch to os_start */ @@ -257,7 +258,8 @@ static void go_os_start(void) __asm__ __volatile__ ( - "\tldr sp, =g_idle_topstack\n" /* Reset the stack pointer */ + "\tldr ip, =g_idle_topstack\n" /* IP=address of g_idle_topstack */ + "\tldr sp, [ip]\n" /* Reset the stack pointer */ "\tmov fp, #0\n" /* Reset the frame pointer */ "\tmov r14, #0\n" /* LR = return address (none) */ "\tb os_start\n" /* Branch to os_start */ From 416e01bbfa600ece06cc30fe06a8146598dd8474 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Dec 2015 09:30:37 -0600 Subject: [PATCH 22/22] TMS570: Add some placeholders for missing logic; fix some conditional compilation --- arch/arm/src/tms570/tms570_boot.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index a3e949d98c4..66c92862f55 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -412,11 +412,21 @@ void arm_boot(void) #ifdef CONFIG_TMS570_DCAN2 | SYS_MSIENA_DCAN2_RAM #endif -#ifdef CONFIG_TMS570_MIBASPI1 +#ifdef CONFIG_TMS570_MIBADC | SYS_MSIENA_MIBADC_RAM #endif ); +#ifdef CONFIG_TMS570_SELFTEST + /* Test the parity protection mechanism for peripheral RAMs */ +#warning Missing logic +#endif + +#ifdef CONFIG_TMS570_MIBASPI1 + /* Wait for MibSPI1 RAM to complete initialization */ +#warning Missing logic +#endif + /* Configure system response to error conditions */ tms570_esm_initialize();