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STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S

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This commit is contained in:
Titus von Boxberg 2017-07-29 19:14:18 +02:00
parent 9d56dbb403
commit 0947b31fbb
1 changed files with 14 additions and 14 deletions
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28
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
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@ -883,7 +883,7 @@ static void stm32_stdclockconfig(void)
{ {
} }
#endif #endif
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) #if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */ /* Configure PLLI2S */
@ -898,6 +898,19 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLSAICFGR_PLLSAIR); | STM32_RCC_PLLSAICFGR_PLLSAIR);
putreg32(regval, STM32_RCC_PLLI2SCFGR); putreg32(regval, STM32_RCC_PLLI2SCFGR);
/* Enable PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLI2SON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLI2S is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
regval = getreg32(STM32_RCC_DCKCFGR2); regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK | RCC_DCKCFGR2_USART2SEL_MASK
@ -937,19 +950,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR2); putreg32(regval, STM32_RCC_DCKCFGR2);
/* Enable PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLI2SON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLI2S is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */ /* Low speed internal clock source LSI */