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arch/arm/samv7/spi: fix ifdelay setup in spi_setdelay call

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ifdelay description (delay between frames) matches the DLYBCT field
(delay between consecutive transfers without removing chip select)
much better compared to stopdelay (delay between last CLK and CS
innactive). The option for stopdelay does not seem to be configurable
in SAMv7 peripheral.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc 2025-02-24 16:34:13 +01:00 • committed by Lup Yuen Lee
parent 98e2bdd324
commit 06d1bf3370
1 changed files with 2 additions and 2 deletions
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4
arch/arm/src/samv7/sam_spi.c
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@ -1157,7 +1157,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT;
spi_putreg(spi, regval, offset);
/* stopdelay = DLYBCT: Delay Between Consecutive Transfers.
/* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
* This field defines the delay between two consecutive transfers with the
* same peripheral without removing the chip select. The delay is always
* inserted after each transfer and before removing the chip select if
@ -1171,7 +1171,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
*/
dlybct = SAM_SPI_CLOCK;
dlybct *= stopdelay;
dlybct *= ifdelay;
dlybct /= 1000000000;
dlybct /= 32;
regval = spi_getreg(spi, offset);