From 79fad2843a07fdb7edf3cd750b1f13fcf62a19bf Mon Sep 17 00:00:00 2001 From: v01d Date: Fri, 30 Oct 2015 20:15:18 -0300 Subject: [PATCH 01/10] lpc4337: WIP --- arch/arm/include/lpc43xx/chip.h | 78 ++++++++++++++++++++++----------- arch/arm/src/lpc43xx/Kconfig | 8 ++++ arch/arm/src/lpc43xx/chip.h | 4 ++ 3 files changed, 64 insertions(+), 26 deletions(-) diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h index 7272f06790f..e8ce651f663 100644 --- a/arch/arm/include/lpc43xx/chip.h +++ b/arch/arm/include/lpc43xx/chip.h @@ -78,33 +78,33 @@ /* Get customizations for each supported chip. * * SRAM Resources - * --------------------- -------- ------- ------- ------- ------- ------- - * Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 - * --------------------- -------- ------- ------- ------- ------- ------- - * BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb - * BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 - * --------------------- -------- ------- ------- ------- ------- ------- - * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb - * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 - * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb - * --------------------- -------- ------- ------- ------- ------- ------- + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337 + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb 32Kb + * BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb 40Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb 72Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337 + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb 48Kb + * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 + * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb 64Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb 136Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- * - * --------------------- -------- ------- ------- ------- ------- ------- - * FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 - * --------------------- -------- ------- ------- ------- ------- ------- - * BANK A (0x1a00 0000) 256Kb 512Kb - * BANK B (0x1b00 8000) 256Kb 512Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * TOTAL None None None None 512Kb 1024Kb - * --------------------- -------- ------- ------- ------- ------- ------- + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337 + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * BANK A (0x1a00 0000) 256Kb 512Kb 512Kb + * BANK B (0x1b00 8000) 256Kb 512Kb 512Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * TOTAL None None None None 512Kb 1024Kb 1024Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- * * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM * banks but are treated as two banks of 48 an 16Kb by the NuttX memory @@ -321,6 +321,32 @@ # define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */ # define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */ # undef LPC43_NADC12 /* No 12-bit ADC controllers */ +#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144) +# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */ +# define LPC43_FLASH_BANKB_SIZE (512*1025) +# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ +# define LPC43_LOCSRAM_BANK1_SIZE (40*1024) +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK1_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ +# define LPC43_NLCD (0) /* Has LCD controller */ +# define LPC43_ETHERNET (1) /* One Ethernet controller */ +# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ +# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */ +# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */ +# define LPC43_MCPWM (1) /* One PWM interface */ +# define LPC43_QEI (0) /* One Quadrature Encoder interface */ +# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */ +# define LPC43_NSSP (2) /* Two SSP controllers */ +# define LPC43_NTIMERS (4) /* Four Timers */ +# define LPC43_NI2C (2) /* Two I2C controllers */ +# define LPC43_NI2S (2) /* Two I2S controllers */ +# define LPC43_NCAN (2) /* Two CAN controllers */ +# define LPC43_NDAC (1) /* One 10-bit DAC */ +# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */ +# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */ +# undef LPC43_NADC12 /* No 12-bit ADC controllers */ #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208) # define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */ # define LPC43_FLASH_BANKB_SIZE (0) diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index 8df9946f070..e3655a47b27 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -34,6 +34,9 @@ config ARCH_CHIP_LPC4330FET180 config ARCH_CHIP_LPC4330FET256 bool "LPC4330FET256" +config ARCH_CHIP_LPC4337JBD144 + bool "LPC4337JBD144" + config ARCH_CHIP_LPC4350FBD208 bool "LPC4350FBD208" @@ -81,6 +84,11 @@ config ARCH_FAMILY_LPC4330 default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 select ARCH_HAVE_TICKLESS +config ARCH_FAMILY_LPC4337 + bool + default y if ARCH_CHIP_LPC4337JBD144 + select ARCH_HAVE_TICKLESS + config ARCH_FAMILY_LPC4350 bool default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256 diff --git a/arch/arm/src/lpc43xx/chip.h b/arch/arm/src/lpc43xx/chip.h index 0551c55b683..08ef7217a52 100644 --- a/arch/arm/src/lpc43xx/chip.h +++ b/arch/arm/src/lpc43xx/chip.h @@ -97,6 +97,10 @@ # define ARMV7M_PERIPHERAL_INTERRUPTS 53 # include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" +#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144) +# define ARMV7M_PERIPHERAL_INTERRUPTS 53 +# include "chip/lpc435357_memorymap.h" +# include "chip/lpc4357fet256_pinconfig.h" #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208) # define ARMV7M_PERIPHERAL_INTERRUPTS 53 # include "chip/lpc4310203050_memorymap.h" From 668c56b1a6a5e99090c4ffe636d337563a8cf7c2 Mon Sep 17 00:00:00 2001 From: pnb Date: Sat, 31 Oct 2015 15:33:32 +0100 Subject: [PATCH 02/10] avoid warning unsused function when GPIO_TIMxCHxOUT declared in board and CONFIG_STM32_TIMx not enable but an other CONFIG_STM32_TIMx is enabled --- arch/arm/src/stm32/stm32_tim.c | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 1f9d5375714..2aeccd86a3e 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -145,6 +145,49 @@ # undef CONFIG_STM32_TIM14 #endif +#if defined(CONFIG_STM32_TIM1) +# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ + defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) +# define HAVE_TIM1_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM2) +# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ + defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) +# define HAVE_TIM2_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM3) +# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ + defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) +# define HAVE_TIM3_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM4) +# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ + defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) +# define HAVE_TIM4_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM5) +# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ + defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) +# define HAVE_TIM5_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM8) +# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ + defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) +# define HAVE_TIM8_PWM_OUTPUT 1 +#endif +#endif + + /* This module then only compiles if there are enabled timers that are not intended for * some other purpose. */ @@ -245,6 +288,9 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) stm32_tim_disable(dev); } +#if defined(HAVE_TIM1_PWM_OUTPUT)||defined(HAVE_TIM2_PWM_OUTPUT)||\ + defined(HAVE_TIM3_PWM_OUTPUT)||defined(HAVE_TIM4_PWM_OUTPUT)||\ + defined(HAVE_TIM5_PWM_OUTPUT)||defined(HAVE_TIM8_PWM_OUTPUT) static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ @@ -258,6 +304,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) stm32_unconfiggpio(cfg); } } +#endif /************************************************************************************ * Basic Functions From 0090cfe6d48993ed01a3a198f1721082177f7414 Mon Sep 17 00:00:00 2001 From: pnb Date: Sat, 31 Oct 2015 15:59:20 +0100 Subject: [PATCH 03/10] Change name of HAVE_TIMx_PWM_OUTPUT into HAVE_TIMx_GPIOCONFIG --- arch/arm/src/stm32/stm32_tim.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 2aeccd86a3e..c7d3b8350ce 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -148,42 +148,42 @@ #if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_PWM_OUTPUT 1 +# define HAVE_TIM1_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_PWM_OUTPUT 1 +# define HAVE_TIM2_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_PWM_OUTPUT 1 +# define HAVE_TIM3_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_PWM_OUTPUT 1 +# define HAVE_TIM4_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_PWM_OUTPUT 1 +# define HAVE_TIM5_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_PWM_OUTPUT 1 +# define HAVE_TIM8_GPIOCONFIG 1 #endif #endif @@ -288,9 +288,9 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) stm32_tim_disable(dev); } -#if defined(HAVE_TIM1_PWM_OUTPUT)||defined(HAVE_TIM2_PWM_OUTPUT)||\ - defined(HAVE_TIM3_PWM_OUTPUT)||defined(HAVE_TIM4_PWM_OUTPUT)||\ - defined(HAVE_TIM5_PWM_OUTPUT)||defined(HAVE_TIM8_PWM_OUTPUT) +#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ + defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ + defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG) static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ From d1b4d55343907a8b0a41b8892f02301d51d033e1 Mon Sep 17 00:00:00 2001 From: pnb Date: Sun, 1 Nov 2015 14:40:43 +0100 Subject: [PATCH 04/10] pwm duty can by zero --- arch/arm/src/stm32/stm32_pwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index a3a16456889..a5cafce7974 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -582,7 +582,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x\n", priv->timid, priv->channel, info->frequency, info->duty); #endif - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && + DEBUGASSERT(info->frequency > 0 && info->duty >= 0 && info->duty < uitoub16(100)); /* Disable all interrupts and DMA requests, clear all pending status */ From 9db4b4ca7e0447b6d09775588bc33e51c8ac1234 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 1 Nov 2015 09:01:59 -0600 Subject: [PATCH 05/10] Rename board_led_initialize to board_autoled_initiaize --- arch/arm/src/arm/up_nommuhead.S | 2 +- arch/arm/src/dm320/dm320_boot.c | 3 +- arch/arm/src/imx/imx_boot.c | 3 +- arch/arm/src/lpc214x/lpc214x_head.S | 2 +- arch/arm/src/lpc2378/lpc23xx_head.S | 2 +- arch/arm/src/str71x/str71x_head.S | 229 +++++++++++----------- arch/sh/src/m16c/m16c_head.S | 72 +++---- arch/sh/src/sh1/sh1_head.S | 288 ++++++++++++++-------------- arch/z16/src/z16f/z16f_head.S | 4 +- arch/z80/src/z8/z8_head.S | 2 +- 10 files changed, 305 insertions(+), 302 deletions(-) diff --git a/arch/arm/src/arm/up_nommuhead.S b/arch/arm/src/arm/up_nommuhead.S index 69855c0b094..04c5205efe0 100644 --- a/arch/arm/src/arm/up_nommuhead.S +++ b/arch/arm/src/arm/up_nommuhead.S @@ -125,7 +125,7 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif #ifdef CONFIG_STACK_COLORATION diff --git a/arch/arm/src/dm320/dm320_boot.c b/arch/arm/src/dm320/dm320_boot.c index 089d7b45fbb..13f64b3ff79 100644 --- a/arch/arm/src/dm320/dm320_boot.c +++ b/arch/arm/src/dm320/dm320_boot.c @@ -225,8 +225,9 @@ void up_boot(void) /* Set up the board-specific LEDs */ #ifdef CONFIG_ARCH_LEDS - board_led_initialize(); + board_autoled_initialize(); #endif + /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT diff --git a/arch/arm/src/imx/imx_boot.c b/arch/arm/src/imx/imx_boot.c index 44d8bf7b05f..71bf743e3f2 100644 --- a/arch/arm/src/imx/imx_boot.c +++ b/arch/arm/src/imx/imx_boot.c @@ -216,8 +216,9 @@ void up_boot(void) /* Set up the board-specific LEDs */ #ifdef CONFIG_ARCH_LEDS - board_led_initialize(); + board_autoled_initialize(); #endif + /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT diff --git a/arch/arm/src/lpc214x/lpc214x_head.S b/arch/arm/src/lpc214x/lpc214x_head.S index 0679bfa2a91..8db27f29ebd 100644 --- a/arch/arm/src/lpc214x/lpc214x_head.S +++ b/arch/arm/src/lpc214x/lpc214x_head.S @@ -592,7 +592,7 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif /* Then jump to OS entry */ diff --git a/arch/arm/src/lpc2378/lpc23xx_head.S b/arch/arm/src/lpc2378/lpc23xx_head.S index d3aa33503be..637402fa885 100755 --- a/arch/arm/src/lpc2378/lpc23xx_head.S +++ b/arch/arm/src/lpc2378/lpc23xx_head.S @@ -193,7 +193,7 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif /* Then jump to OS entry */ diff --git a/arch/arm/src/str71x/str71x_head.S b/arch/arm/src/str71x/str71x_head.S index b7bd53a675b..6a299e8911b 100644 --- a/arch/arm/src/str71x/str71x_head.S +++ b/arch/arm/src/str71x/str71x_head.S @@ -37,11 +37,11 @@ * Included Files *****************************************************************************/ -#include /* NuttX configuration settings */ +#include /* NuttX configuration settings */ #include /* Board-specific settings */ -#include "arm.h" /* ARM-specific settings */ -#include "chip.h" /* Chip-specific settings */ +#include "arm.h" /* ARM-specific settings */ +#include "chip.h" /* Chip-specific settings */ #include "up_internal.h" #include "up_arch.h" @@ -59,18 +59,18 @@ * External references *****************************************************************************/ - .globl str71x_prccuinit /* Clock initialization */ - .globl up_lowsetup /* Early initialization of UART */ + .globl str71x_prccuinit /* Clock initialization */ + .globl up_lowsetup /* Early initialization of UART */ #ifdef USE_EARLYSERIALINIT - .globl up_earlyserialinit /* Early initialization of serial driver */ + .globl up_earlyserialinit /* Early initialization of serial driver */ #endif #ifdef CONFIG_ARCH_LEDS - .globl board_led_initialize /* Boot LED setup */ + .globl board_autoled_initialize /* Boot LED setup */ #endif #ifdef CONFIG_DEBUG - .globl up_lowputc /* Low-level debug output */ + .globl up_lowputc /* Low-level debug output */ #endif - .globl os_start /* NuttX entry point */ + .globl os_start /* NuttX entry point */ /***************************************************************************** * Macros @@ -87,8 +87,8 @@ .macro showprogress, code #ifdef CONFIG_DEBUG - mov r0, #\code - bl up_lowputc + mov r0, #\code + bl up_lowputc #endif .endm @@ -107,32 +107,32 @@ /* In order to use the external memory, certain GPIO pins must be * configured in the alternate function: * - * GPIO ALT Description + * GPIO ALT Description * P2.0-3 CS.0-3 External memory chip select for banks 0,1,3,4 * P2.4-7 A.20-23 External memory extended address bus (needed for * address space > 1Mb) */ #ifdef CONFIG_STR71X_BIGEXTMEM -# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */ +# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */ #else -# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */ +# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */ #endif - ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode - ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET] - orr \value, \value, #EXTMEM_GPIO_BITSET - str \value, [\base, #STR71X_GPIO_PC0_OFFSET] - ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET] - orr \value, \value, #EXTMEM_GPIO_BITSET - str \value, [\base, #STR71X_GPIO_PC1_OFFSET] - ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET] - orr \value, \value, #EXTMEM_GPIO_BITSET - str \value, [\base, #STR71X_GPIO_PC2_OFFSET] + ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode + ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC0_OFFSET] + ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC1_OFFSET] + ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC2_OFFSET] /* Enable bank 0 */ - ldr \base, =STR71X_EMI_BASE + ldr \base, =STR71X_EMI_BASE #ifdef CONFIG_STR71X_BANK0 @@ -156,11 +156,11 @@ # define EXTMEM_BANK0_WAITSTATES (CONFIG_STR71X_BANK0_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON0_OFFSET] + str \value, [\base, #STR71X_EMI_BCON0_OFFSET] /* Enable bank 1 */ @@ -186,11 +186,11 @@ # define EXTMEM_BANK1_WAITSTATES (CONFIG_STR71X_BANK1_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON1_OFFSET] + str \value, [\base, #STR71X_EMI_BCON1_OFFSET] /* Enable bank 2 */ @@ -216,11 +216,11 @@ # define EXTMEM_BANK2_WAITSTATES (CONFIG_STR71X_BANK2_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON2_OFFSET] + str \value, [\base, #STR71X_EMI_BCON2_OFFSET] /* Enable bank 3 */ @@ -246,11 +246,11 @@ # define EXTMEM_BANK3_WAITSTATES (CONFIG_STR71X_BANK3_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON3_OFFSET] + str \value, [\base, #STR71X_EMI_BCON3_OFFSET] #endif .endm @@ -277,42 +277,42 @@ .macro eicinit, eicbase, value, irqno, offset /* Disable and clear all interrupts */ - ldr \eicbase, =STR71X_EIC_BASE + ldr \eicbase, =STR71X_EIC_BASE /* Disable FIQ and IRQ */ - mov \value, #0 - str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET] + mov \value, #0 + str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET] /* Disable all channel interrupts */ - str \value, [\eicbase, #STR71X_EIC_IER_OFFSET] + str \value, [\eicbase, #STR71X_EIC_IER_OFFSET] /* Clear all pending IRQs */ - ldr \value, =0xffffffff - str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET] + ldr \value, =0xffffffff + str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET] /* Disable FIQ channels/clear pending FIQs */ - mov \value, #0x0c - str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET] + mov \value, #0x0c + str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET] /* Reset the current priority register */ - mov \value, #0 - str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET] + mov \value, #0 + str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET] /* Zero IVR 31:16 */ - str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET] + str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET] /* Set up the loop to initialize each SIR register. Start * with IRQ number 0 and SIR0 */ - mov \irqno, #0 - ldr \offset, =STR71X_EIC_SIR_OFFSET + mov \irqno, #0 + ldr \offset, =STR71X_EIC_SIR_OFFSET /* Then loop for each EIC channel */ eicloop: @@ -325,22 +325,22 @@ eicloop: * are all disabled. */ - mov \value, \irqno, lsl #16 - str \value, [\eicbase, \offset] + mov \value, \irqno, lsl #16 + str \value, [\eicbase, \offset] /* Increment the offset to the next SIR register and inrement * the IRQ number. */ - add \offset, \offset, #4 - add \irqno, \irqno, #1 + add \offset, \offset, #4 + add \irqno, \irqno, #1 /* Continue to loop until all of the SIR registers have been * initializeed. */ - cmp \irqno, #STR71X_EIC_NCHANNELS - blt eicloop + cmp \irqno, #STR71X_EIC_NCHANNELS + blt eicloop .endm /***************************************************************************** @@ -355,25 +355,26 @@ eicloop: #ifndef CONFIG_STR71X_DISABLE_PERIPHINIT /* Set up APB1 and APB2 addresses */ - ldr \base1, =STR71X_APB1_BASE - ldr \base2, =STR71X_APB2_BASE + ldr \base1, =STR71X_APB1_BASE + ldr \base2, =STR71X_APB2_BASE /* Disable all APB1 peripherals */ - ldr \value, =STR71X_APB1_APB1ALL + ldr \value, =STR71X_APB1_APB1ALL strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET] /* Disable all(or most) APB2 peripherals */ - ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC) + + ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC) strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET] /* Allow EMI and USB */ - ldr \base1, =STR71X_RCCU_BASE + ldr \base1, =STR71X_RCCU_BASE #ifdef CONFIG_STR71X_USB - ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL) + ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL) #else - ldr \value, =STR71X_RCCUPER_EMI + ldr \value, =STR71X_RCCUPER_EMI #endif strh \value, [\base1, #STR71X_RCCU_PER_OFFSET] #endif @@ -391,15 +392,16 @@ eicloop: *****************************************************************************/ .macro remap, base, value + /* Read the PCU BOOTCR register */ - ldr \base, =STR71X_PCU_BASE + ldr \base, =STR71X_PCU_BASE ldrh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET] /* Mask out the old boot mode bits and set the boot mode to FLASH */ - bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK - orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH + bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK + orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH /* Save the modified BOOTCR register */ @@ -426,16 +428,16 @@ eicloop: .globl _vector_table .type _vector_table, %function _vector_table: - ldr pc, .Lresethandler /* 0x00: Reset */ - ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */ - ldr pc, .Lswihandler /* 0x08: Software interrupt */ - ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */ - ldr pc, .Ldataaborthandler /* 0x10: Data abort */ - .long 0 /* 0x14: Reserved vector */ - ldr pc, .Lirqhandler /* 0x18: IRQ */ - ldr pc, .Lfiqhandler /* 0x1c: FIQ */ + ldr pc, .Lresethandler /* 0x00: Reset */ + ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */ + ldr pc, .Lswihandler /* 0x08: Software interrupt */ + ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */ + ldr pc, .Ldataaborthandler /* 0x10: Data abort */ + .long 0 /* 0x14: Reserved vector */ + ldr pc, .Lirqhandler /* 0x18: IRQ */ + ldr pc, .Lfiqhandler /* 0x1c: FIQ */ - .globl __start + .globl __start .globl up_vectorundefinsn .globl up_vectorswi .globl up_vectorprefetch @@ -444,7 +446,7 @@ _vector_table: .globl up_vectorfiq .Lresethandler: - .long __start + .long __start .Lundefinedhandler: .long up_vectorundefinsn .Lswihandler: @@ -478,16 +480,16 @@ __start: * the aliased copy */ - ldr pc, =__flashstart + ldr pc, =__flashstart __flashstart: .rept 9 - nop /* Wait for OSC stabilization*/ + nop /* Wait for OSC stabilization */ .endr /* Setup the initial processor mode */ - mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT ) - msr cpsr, r0 + mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT ) + msr cpsr, r0 /* Initialize the external memory interface (EMI) */ @@ -499,7 +501,7 @@ __flashstart: /* Disable all peripherals except EIC */ - periphinit r0, r1, r2 + periphinit r0, r1, r2 /* Map memory appropriately for configuration */ @@ -507,42 +509,42 @@ __flashstart: /* Setup system stack (and get the BSS range) */ - adr r0, LC0 - ldmia r0, {r4, r5, sp} + adr r0, LC0 + ldmia r0, {r4, r5, sp} /* Clear system BSS section */ - mov r0, #0 -1: cmp r4, r5 + mov r0, #0 +1: cmp r4, r5 strcc r0, [r4], #4 - bcc 1b + bcc 1b /* Copy system .data sections from FLASH to new home in RAM. */ - adr r3, LC2 + adr r3, LC2 ldmia r3, {r0, r1, r2} 2: ldmia r0!, {r3 - r10} stmia r1!, {r3 - r10} - cmp r1, r2 - blt 2b + cmp r1, r2 + blt 2b /* Initialize clocking */ - bl str71x_prccuinit + bl str71x_prccuinit /* Configure the uart so that we can get debug output as soon * as possible. */ - bl up_lowsetup + bl up_lowsetup showprogress 'A' /* Perform early serial initialization */ - mov fp, #0 + mov fp, #0 #ifdef USE_EARLYSERIALINIT - bl up_earlyserialinit + bl up_earlyserialinit #endif showprogress 'B' @@ -550,17 +552,17 @@ __flashstart: /* Call C++ constructors */ #ifdef CONFIG_CPLUSPLUS - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b ctor_loop + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + mov pc, r2 + ldmfd sp!, {r0-r1} + b ctor_loop ctor_end: showprogress 'C' @@ -570,27 +572,27 @@ ctor_end: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif /* Then jump to OS entry */ - b os_start + b os_start /* Call destructors -- never get here */ #if 0 /* CONFIG_CPLUSPLUS */ - ldr r0, =__dtors_start__ - ldr r1, =__dtors_end__ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ dtor_loop: - cmp r0, r1 - beq dtor_end - ldr r2, [r0], #4 + cmp r0, r1 + beq dtor_end + ldr r2, [r0], #4 stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 + mov lr, pc + mov pc, r2 ldmfd sp!, {r0-r1} - b dtor_loop + b dtor_loop dtor_end: #endif @@ -626,4 +628,3 @@ g_idle_topstack: .size g_idle_topstack, .-g_idle_topstack .end - diff --git a/arch/sh/src/m16c/m16c_head.S b/arch/sh/src/m16c/m16c_head.S index 06f40d225c1..f18da3fe3fe 100644 --- a/arch/sh/src/m16c/m16c_head.S +++ b/arch/sh/src/m16c/m16c_head.S @@ -60,8 +60,8 @@ .macro showprogress, code #ifdef CONFIG_DEBUG .globl _up_lowputc - mov.b r#\code1l /* Character to print */ - jsr.a _up_lowputc /* Print it */ + mov.b r#\code1l /* Character to print */ + jsr.a _up_lowputc /* Print it */ #endif .endm @@ -71,11 +71,11 @@ /* The near RAM memory map is as follows: * - * 0x00400 - DATA Size: Determined by linker - * BSS Size: Determined by linker + * 0x00400 - DATA Size: Determined by linker + * BSS Size: Determined by linker * Interrupt stack Size: CONFIG_ARCH_INTERRUPTSTACK - * Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE - * Heap Size: Everything remaining + * Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE + * Heap Size: Everything remaining * 0x00bff - (end+1) */ @@ -174,48 +174,48 @@ __start: /* Set the interrupt and user stack pointers */ mov.w #_enbss, R0 - ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */ + ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */ add.w #CONFIG_IDLETHREAD_STACKSIZE, R0 - fset U /* Set bit 7 (U) to select the user stack pointer */ - ldc R0, sp /* Set the user stack pointer */ + fset U /* Set bit 7 (U) to select the user stack pointer */ + ldc R0, sp /* Set the user stack pointer */ /* Set BCLK speed. At reset, the processor clock (BLCK) defaults to a divisor of 8. * This sets clock to F1 (divide by 1) on XIN: BCLK = XIN frequency. */ - mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */ - mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1 - * CM17 & CM16 defaults to 0 after reset and - * so we only need to reset CM06 to 0 */ - mov.b #0x00,M16C_PRCR /* protect CM0 */ + mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */ + mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1 + * CM17 & CM16 defaults to 0 after reset and + * so we only need to reset CM06 to 0 */ + mov.b #0x00,M16C_PRCR /* protect CM0 */ /* The two MS bits of the interrupt cause select register must be set to * enable the use of INT4 and INT5 */ - mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */ - ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */ + mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */ + ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */ /* Set up INTB to point to location of variable vector table */ - mov.w _g_svarvect, r0 /* R0 = lower 16-bits */ - mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */ - ldc r1, intbh - ldc r0, intbl + mov.w _g_svarvect, r0 /* R0 = lower 16-bits */ + mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */ + ldc r1, intbh + ldc r0, intbl /* Configure the uart so that we can get debug output as soon as possible. */ - .globl _up_lowsetup /* Early initialization of UART */ + .globl _up_lowsetup /* Early initialization of UART */ jsr.a _up_lowsetup showprogress 'A' /* Clear near .bss sections */ - mov.b #0x00, r0l /* r0l: 0 */ - mov.w _g_snbss, a1 /* a1: start of near .bss */ - mov.w _g_enbss, r3 /* r3: end of near .bss */ - sub.w a1, r3 /* r3: size of near .bss */ - sstr.b /* Clear near .bss */ + mov.b #0x00, r0l /* r0l: 0 */ + mov.w _g_snbss, a1 /* a1: start of near .bss */ + mov.w _g_enbss, r3 /* r3: end of near .bss */ + sub.w a1, r3 /* r3: size of near .bss */ + sstr.b /* Clear near .bss */ /* Clear far .bss sections */ @@ -227,12 +227,12 @@ __start: /* Initialize near .data sections (.rodata is not moved) */ - mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */ - mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */ - mov.w _g_sndata, a1 /* a1: start of near .data */ - mov.w _g_endata, r3 /* r3: end of near .data */ - sub.w a1, r3 /* r3: size of near .data */ - smovf.b /* Copy source to near .data */ + mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */ + mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */ + mov.w _g_sndata, a1 /* a1: start of near .data */ + mov.w _g_endata, r3 /* r3: end of near .data */ + sub.w a1, r3 /* r3: size of near .data */ + smovf.b /* Copy source to near .data */ /* Initialize far .data sections (.rodata is not moved) */ @@ -245,8 +245,8 @@ __start: /* Perform early console initialization */ #ifdef USE_EARLYSERIALINIT - .globl _up_earlyconsoleinit /* Early initialization of console driver */ - jsr.a _up_earlyconsoleinit /* Call it */ + .globl _up_earlyconsoleinit /* Early initialization of console driver */ + jsr.a _up_earlyconsoleinit /* Call it */ showprogress 'D' #endif @@ -260,8 +260,8 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - .globl _board_led_initialize /* Boot LED setup */ - jsr.a _board_led_initialize /* Call it */ + .globl _board_autoled_initialize /* Boot LED setup */ + jsr.a _board_autoled_initialize /* Call it */ #endif showprogress '\n' diff --git a/arch/sh/src/sh1/sh1_head.S b/arch/sh/src/sh1/sh1_head.S index f0f70de1f7b..9bb4efb1f5e 100644 --- a/arch/sh/src/sh1/sh1_head.S +++ b/arch/sh/src/sh1/sh1_head.S @@ -60,31 +60,32 @@ /* Called functions */ - .globl _up_lowsetup /* Early initialization of UART */ + .globl _up_lowsetup /* Early initialization of UART */ #ifdef USE_EARLYSERIALINIT - .globl _up_earlyconsoleinit /* Early initialization of console driver */ + .globl _up_earlyconsoleinit /* Early initialization of console driver */ #endif #ifdef CONFIG_ARCH_LEDS - .globl _board_led_initialize /* Boot LED setup */ + .globl _board_autoled_initialize /* Boot LED setup */ #endif #ifdef CONFIG_DEBUG - .globl _up_lowputc /* Low-level debug output */ + .globl _up_lowputc /* Low-level debug output */ #endif - .globl _os_start /* NuttX entry point */ + .globl _os_start /* NuttX entry point */ /* Variables set up by the linker script */ - .globl _sbss /* Start of BSS */ - .globl _ebss /* End of BSS */ - .globl _svect /* Start of the new vector location */ + .globl _sbss /* Start of BSS */ + .globl _ebss /* End of BSS */ + .globl _svect /* Start of the new vector location */ #ifdef CONFIG_BOOT_RUNFROMFLASH - .globl _eronly /* Where .data defaults are stored in FLASH */ - .global _sdata /* Start of .data in RAM */ - .globl _edata /* End of .data in RAM */ + .globl _eronly /* Where .data defaults are stored in FLASH */ + .global _sdata /* Start of .data in RAM */ + .globl _edata /* End of .data in RAM */ #endif /* Interrupt handlers */ + .globl _up_invalid_handler #ifdef CONFIG_SH1_DMAC0 .globl _up_dmac0_handler @@ -161,9 +162,9 @@ .macro showprogress, code #ifdef CONFIG_DEBUG - mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */ - jsr @r0 /* Call it */ - mov #\code, r4 /* Delay slot */ + mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */ + jsr @r0 /* Call it */ + mov #\code, r4 /* Delay slot */ #endif .endm @@ -191,128 +192,128 @@ __vector_table: * vectors. */ - .long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */ + .long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */ .long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 - .long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */ + .long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */ .long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 - .rept SH1_NCMN_VECTORS-4 + .rept SH1_NCMN_VECTORS-4 .long _up_invalid_handler .endr /* The remaining vectors are unique to the SH-1 703x family */ #ifdef CONFIG_SH1_DMAC0 - .long _up_dmac0_handler /* 72: DMAC0 DEI0 */ + .long _up_dmac0_handler /* 72: DMAC0 DEI0 */ #else - .long _up_invalid_handler /* 72: DMAC0 DEI0 */ + .long _up_invalid_handler /* 72: DMAC0 DEI0 */ #endif - .long _up_invalid_handler /* 73: Reserved */ + .long _up_invalid_handler /* 73: Reserved */ #ifdef CONFIG_SH1_DMAC1 - .long _up_dmac1_handler /* 74: DMAC1 DEI1 */ + .long _up_dmac1_handler /* 74: DMAC1 DEI1 */ #else - .long _up_invalid_handler /* 74: DMAC1 DEI1 */ + .long _up_invalid_handler /* 74: DMAC1 DEI1 */ #endif - .long _up_invalid_handler /* 75: Reserved */ + .long _up_invalid_handler /* 75: Reserved */ #ifdef CONFIG_SH1_DMAC2 - .long _up_dmac2_handler /* 76: DMAC2 DEI2 */ + .long _up_dmac2_handler /* 76: DMAC2 DEI2 */ #else - .long _up_invalid_handler /* 76: DMAC2 DEI2 */ + .long _up_invalid_handler /* 76: DMAC2 DEI2 */ #endif - .long _up_invalid_handler /* 77: Reserved */ + .long _up_invalid_handler /* 77: Reserved */ #ifdef CONFIG_SH1_DMAC3 - .long _up_dmac3_handler /* 78: DMAC3 DEI3 */ + .long _up_dmac3_handler /* 78: DMAC3 DEI3 */ #else - .long _up_invalid_handler /* 78: DMAC3 DEI3 */ + .long _up_invalid_handler /* 78: DMAC3 DEI3 */ #endif - .long _up_invalid_handler /* 79: Reserved */ - .long _up_imia0_handler /* 80: ITU0 IMIA0 */ - .long _up_imib0_handler /* 81: IMIB0 */ - .long _up_ovi0_handler /* 82: OVI0 */ - .long _up_invalid_handler /* 83: Reserved */ + .long _up_invalid_handler /* 79: Reserved */ + .long _up_imia0_handler /* 80: ITU0 IMIA0 */ + .long _up_imib0_handler /* 81: IMIB0 */ + .long _up_ovi0_handler /* 82: OVI0 */ + .long _up_invalid_handler /* 83: Reserved */ #ifdef CONFIG_SH1_ITU1 - .long _up_imia1_handler /* 84: ITU1 IMIA1 */ - .long _up_imib1_handler /* 85: IMIB1 */ - .long _up_ovi1_handler /* 86: OVI1 */ + .long _up_imia1_handler /* 84: ITU1 IMIA1 */ + .long _up_imib1_handler /* 85: IMIB1 */ + .long _up_ovi1_handler /* 86: OVI1 */ #else - .long _up_invalid_handler /* 84: ITU1 IMIA1 */ - .long _up_invalid_handler /* 85: IMIB1 */ - .long _up_invalid_handler /* 86: OVI1 */ + .long _up_invalid_handler /* 84: ITU1 IMIA1 */ + .long _up_invalid_handler /* 85: IMIB1 */ + .long _up_invalid_handler /* 86: OVI1 */ #endif - .long _up_invalid_handler /* 87: Reserved */ + .long _up_invalid_handler /* 87: Reserved */ #ifdef CONFIG_SH1_ITU2 - .long _up_imia2_handler /* 88: ITU2 IMIA2 */ - .long _up_imib2_handler /* 89: IMIB2 */ - .long _up_ovi2_handler /* 90: OVI2 */ + .long _up_imia2_handler /* 88: ITU2 IMIA2 */ + .long _up_imib2_handler /* 89: IMIB2 */ + .long _up_ovi2_handler /* 90: OVI2 */ #else - .long _up_invalid_handler /* 88: ITU2 IMIA2 */ - .long _up_invalid_handler /* 89: IMIB2 */ - .long _up_invalid_handler /* 90: OVI2 */ + .long _up_invalid_handler /* 88: ITU2 IMIA2 */ + .long _up_invalid_handler /* 89: IMIB2 */ + .long _up_invalid_handler /* 90: OVI2 */ #endif - .long _up_invalid_handler /* 91: Reserved */ + .long _up_invalid_handler /* 91: Reserved */ #ifdef CONFIG_SH1_ITU3 - .long _up_imia3_handler /* 92: ITU3 IMIA3 */ - .long _up_imib3_handler /* 93: IMIB3 */ - .long _up_ovi3_handler /* 94: OVI3 */ + .long _up_imia3_handler /* 92: ITU3 IMIA3 */ + .long _up_imib3_handler /* 93: IMIB3 */ + .long _up_ovi3_handler /* 94: OVI3 */ #else - .long _up_invalid_handler /* 92: ITU3 IMIA3 */ - .long _up_invalid_handler /* 93: IMIB3 */ - .long _up_invalid_handler /* 94: OVI3 */ + .long _up_invalid_handler /* 92: ITU3 IMIA3 */ + .long _up_invalid_handler /* 93: IMIB3 */ + .long _up_invalid_handler /* 94: OVI3 */ #endif - .long _up_invalid_handler /* 95: Reserved */ + .long _up_invalid_handler /* 95: Reserved */ #ifdef CONFIG_SH1_ITU4 - .long _up_imia4_handler /* 96: ITU4 IMIA4 */ - .long _up_imib4_handler /* 97: IMIB4 */ - .long _up_ovi4_handler /* 98: OVI4 */ + .long _up_imia4_handler /* 96: ITU4 IMIA4 */ + .long _up_imib4_handler /* 97: IMIB4 */ + .long _up_ovi4_handler /* 98: OVI4 */ #else - .long _up_invalid_handler /* 96: ITU4 IMIA4 */ - .long _up_invalid_handler /* 97: IMIB4 */ - .long _up_invalid_handler /* 98: OVI4 */ + .long _up_invalid_handler /* 96: ITU4 IMIA4 */ + .long _up_invalid_handler /* 97: IMIB4 */ + .long _up_invalid_handler /* 98: OVI4 */ #endif - .long _up_invalid_handler /* 99: Reserved */ + .long _up_invalid_handler /* 99: Reserved */ #ifdef CONFIG_SH1_SCI0 - .long _up_eri0_handler /* 100: SCI0 ERI0 */ - .long _up_rxi0_handler /* 101: RxI0 */ - .long _up_txi0_handler /* 102: TxI0 */ - .long _up_tei0_handler /* 103: TEI0 */ + .long _up_eri0_handler /* 100: SCI0 ERI0 */ + .long _up_rxi0_handler /* 101: RxI0 */ + .long _up_txi0_handler /* 102: TxI0 */ + .long _up_tei0_handler /* 103: TEI0 */ #else - .long _up_invalid_handler /* 100: SCI0 ERI0 */ - .long _up_invalid_handler /* 101: RxI0 */ - .long _up_invalid_handler /* 102: TxI0 */ - .long _up_invalid_handler /* 103: TEI0 */ + .long _up_invalid_handler /* 100: SCI0 ERI0 */ + .long _up_invalid_handler /* 101: RxI0 */ + .long _up_invalid_handler /* 102: TxI0 */ + .long _up_invalid_handler /* 103: TEI0 */ #endif #ifdef CONFIG_SH1_SCI1 - .long _up_eri1_handler /* 104: SCI1 ERI1 */ - .long _up_rxi1_handler /* 105: RxI1 */ - .long _up_txi1_handler /* 106: TxI1 */ - .long _up_tei1_handler /* 107: TEI1 */ + .long _up_eri1_handler /* 104: SCI1 ERI1 */ + .long _up_rxi1_handler /* 105: RxI1 */ + .long _up_txi1_handler /* 106: TxI1 */ + .long _up_tei1_handler /* 107: TEI1 */ #else - .long _up_invalid_handler /* 104: SCI1 ERI1 */ - .long _up_invalid_handler /* 105: RxI1 */ - .long _up_invalid_handler /* 106: TxI1 */ - .long _up_invalid_handler /* 107: TEI1 */ + .long _up_invalid_handler /* 104: SCI1 ERI1 */ + .long _up_invalid_handler /* 105: RxI1 */ + .long _up_invalid_handler /* 106: TxI1 */ + .long _up_invalid_handler /* 107: TEI1 */ #endif #ifdef CONFIG_SH1_PCU - .long _up_pei_handler /* 108: Parity control unit PEI */ + .long _up_pei_handler /* 108: Parity control unit PEI */ #else - .long _up_invalid_handler /* 108: Parity control unit PEI */ + .long _up_invalid_handler /* 108: Parity control unit PEI */ #endif #ifdef CONFIG_SH1_AD - .long _up_aditi_handler /* 109: A/D ITI */ + .long _up_aditi_handler /* 109: A/D ITI */ #else - .long _up_invalid_handler /* 109: A/D ITI */ + .long _up_invalid_handler /* 109: A/D ITI */ #endif - .long _up_invalid_handler /* 110: Reserved */ - .long _up_invalid_handler /* 111: Reserved */ + .long _up_invalid_handler /* 110: Reserved */ + .long _up_invalid_handler /* 111: Reserved */ #ifdef CONFIG_SH1_WDT - .long _up_wdt_handler /* 112: WDT ITI */ + .long _up_wdt_handler /* 112: WDT ITI */ #else - .long _up_invalid_handler /* 112: WDT ITI */ + .long _up_invalid_handler /* 112: WDT ITI */ #endif #ifdef CONFIG_SH1_CMI - .long _up_cmi_handler /* 113: REF CMI */ + .long _up_cmi_handler /* 113: REF CMI */ #else - .long _up_invalid_handler /* 113: REF CMI */ + .long _up_invalid_handler /* 113: REF CMI */ #endif .rept (SH1_LAST_VNDX-SH1_CMI_VNDX) /* 114-255: Reserved */ .long _up_invalid_handler @@ -346,15 +347,15 @@ __start: /* set up the bus controller for the EVB */ mov.l .Lwcr1, r0 - sub r1,r1 + sub r1,r1 mov.w r1, @r0 /* Configure the BSR to use /LBS, /HBS, /WR */ - mov.l .Lbcr, r0 - mov.w .Lbas, r1 - bra __start0 - mov.w r1, @r0 + mov.l .Lbcr, r0 + mov.w .Lbas, r1 + bra __start0 + mov.w r1, @r0 .align 2 .Lstack: @@ -369,67 +370,67 @@ __start: __start0: /* Copy the monitor vectors to a002000-a00211f */ - mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */ - mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */ - mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */ + mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */ + mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */ + mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */ 1: - mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */ - mov.l r2, @r1 /* Write into SRAM vector table */ - add #4, r0 /* R0: Address of next vector to read from monitor vector table */ - add #4, r1 /* R1: Address of next vector to write to SRAM vector table */ - cmp/gt r0, r3 /* Copy only only up to external interrupts at */ - bt 1b /* Continue looping until all copied */ - nop /* Delay slot */ + mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */ + mov.l r2, @r1 /* Write into SRAM vector table */ + add #4, r0 /* R0: Address of next vector to read from monitor vector table */ + add #4, r1 /* R1: Address of next vector to write to SRAM vector table */ + cmp/gt r0, r3 /* Copy only only up to external interrupts at */ + bt 1b /* Continue looping until all copied */ + nop /* Delay slot */ /* Update the VBR to show new adddress of vector table */ - mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */ - ldc r0, vbr /* Set VBR to start of SRAM vector table */ + mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */ + ldc r0, vbr /* Set VBR to start of SRAM vector table */ /* Initialize data segement */ #ifdef CONFIG_BOOT_RUNFROMFLASH - mov.l .Lsdata, r0 /* R0: Start of .data segment */ - mov.l .Ledata, r1 /* R1: End+1 of .data segment */ - mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */ + mov.l .Lsdata, r0 /* R0: Start of .data segment */ + mov.l .Ledata, r1 /* R1: End+1 of .data segment */ + mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */ 2: - mov.l @r2, r3 /* R3: Next byte from FLASH copy */ - mov.l r3, @r0 /* Copy to .data */ - add #4, r2 /* R2: Address of next byte to read from FLASH */ - add #4, r0 /* R0: Address to write next byte to .data */ - cmp/gt r0, r1 /* End of .data? */ - bt 2b /* Loop until end of data */ - nop /* Delay slot */ + mov.l @r2, r3 /* R3: Next byte from FLASH copy */ + mov.l r3, @r0 /* Copy to .data */ + add #4, r2 /* R2: Address of next byte to read from FLASH */ + add #4, r0 /* R0: Address to write next byte to .data */ + cmp/gt r0, r1 /* End of .data? */ + bt 2b /* Loop until end of data */ + nop /* Delay slot */ #endif /* Clear BSS */ - mov.l .Lsbss, r0 /* R0: Start of BSS segment */ - mov.l .Lebss, r1 /* R1: End+1 of BSS segment */ - mov #0, r2 /* R2: Value = 0 */ + mov.l .Lsbss, r0 /* R0: Start of BSS segment */ + mov.l .Lebss, r1 /* R1: End+1 of BSS segment */ + mov #0, r2 /* R2: Value = 0 */ 3: - mov.l r2, @r0 /* Clear the next word in BSS */ - add #4, r0 /* R0: Address of next byte to clear in BSS */ - cmp/ge r0, r1 /* End of BSS? */ - bt 3b /* Loop until the end of BSS */ - nop /* Delay slot */ + mov.l r2, @r0 /* Clear the next word in BSS */ + add #4, r0 /* R0: Address of next byte to clear in BSS */ + cmp/ge r0, r1 /* End of BSS? */ + bt 3b /* Loop until the end of BSS */ + nop /* Delay slot */ /* Configure the uart so that we can get debug output as soon * as possible. */ - mov.l .Llowsetup, r0 /* Address of up_lowsetup */ - jsr @r0 /* Call it */ - or r0, r0 /* Delay slot */ + mov.l .Llowsetup, r0 /* Address of up_lowsetup */ + jsr @r0 /* Call it */ + or r0, r0 /* Delay slot */ showprogress 'A' /* Perform early console initialization */ #ifdef USE_EARLYSERIALINIT - mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */ - jsr @r0 /* Call it */ - or r0, r0 /* Delay slot */ + mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */ + jsr @r0 /* Call it */ + or r0, r0 /* Delay slot */ #endif showprogress 'B' @@ -445,16 +446,16 @@ __start0: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - mov.l .Lledinit, r0 /* Address of board_led_initialize */ - jsr @r0 /* Call it */ - or r0, r0 /* Delay slot */ + mov.l .Lledinit, r0 /* Address of board_autoled_initialize */ + jsr @r0 /* Call it */ + or r0, r0 /* Delay slot */ #endif /* Then jump to NuttX entry */ - mov.l .Losstart,r0 - jsr @r0 - or r0, r0 + mov.l .Losstart,r0 + jsr @r0 + or r0, r0 /* Shouldn't get here */ @@ -471,16 +472,16 @@ __start0: .align 2 #ifdef CONFIG_BOOT_RUNFROMFLASH .Leronly: - .long _eronly + .long _eronly .Lsdata: - .long _sdata + .long _sdata .Ledata: - .long _edata + .long _edata #endif .Lsbss: - .long _sbss + .long _sbss .Lebss: - .long _ebss + .long _ebss #ifdef USE_EARLYSERIALINIT .Learlyconsole: .long _up_earlyconsoleinit @@ -492,13 +493,13 @@ __start0: .long _up_lowputc #endif .Lledinit: - .long _board_led_initialize + .long _board_autoled_initialize .Losstart: - .long _os_start + .long _os_start .Lsvect: - .long _svect + .long _svect .Lvectend: - .long ((4*SH1_NCMN_VECTORS)-1) + .long ((4*SH1_NCMN_VECTORS)-1) .size __start, .-__start /***************************************************************************** @@ -521,4 +522,3 @@ _g_idle_topstack: .size _g_idle_topstack, .-_g_idle_topstack .end - diff --git a/arch/z16/src/z16f/z16f_head.S b/arch/z16/src/z16f/z16f_head.S index 511940c8a65..1ceccf93330 100755 --- a/arch/z16/src/z16f/z16f_head.S +++ b/arch/z16/src/z16f/z16f_head.S @@ -54,7 +54,7 @@ xref _z16f_clkinit:EROM xref _z16f_lowinit:EROM #ifdef CONFIG_ARCH_LEDS - xref _board_led_initialize:EROM + xref _board_autoled_initialize:EROM #endif #if defined(USE_LOWUARTINIT) xref _z16f_lowuartinit:EROM @@ -158,7 +158,7 @@ _z16f_reset: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - call _board_led_initialize + call _board_autoled_initialize #endif /* Perform VERY early UART initialization so that we can use it here */ diff --git a/arch/z80/src/z8/z8_head.S b/arch/z80/src/z8/z8_head.S index 9ad7e4f1604..a211e270212 100755 --- a/arch/z80/src/z8/z8_head.S +++ b/arch/z80/src/z8/z8_head.S @@ -68,7 +68,7 @@ xref _z16f_clkinit:ROM xref _z16f_lowinit:ROM #ifdef CONFIG_ARCH_LEDS - xref _board_led_initialize:ROM + xref _board_autoled_initialize:ROM #endif xref _os_start:ROM xref _up_doirq:ROM From b28e32e3d317d64d49d05b86bccb235f9402017c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 1 Nov 2015 09:07:06 -0600 Subject: [PATCH 06/10] Rename board_led_on to board_autoled_on --- arch/arm/src/arm/up_assert.c | 4 ++-- arch/arm/src/arm/up_doirq.c | 2 +- arch/arm/src/arm/up_sigdeliver.c | 2 +- arch/arm/src/armv6-m/up_assert.c | 4 ++-- arch/arm/src/armv6-m/up_doirq.c | 2 +- arch/arm/src/armv6-m/up_sigdeliver.c | 2 +- arch/arm/src/armv7-a/arm_assert.c | 4 ++-- arch/arm/src/armv7-a/arm_doirq.c | 2 +- arch/arm/src/armv7-a/arm_sigdeliver.c | 2 +- arch/arm/src/armv7-m/up_assert.c | 4 ++-- arch/arm/src/armv7-m/up_doirq.c | 2 +- arch/arm/src/armv7-m/up_sigdeliver.c | 2 +- arch/arm/src/common/up_allocateheap.c | 4 ++-- arch/arm/src/common/up_createstack.c | 2 +- arch/arm/src/common/up_initialize.c | 2 +- arch/arm/src/dm320/dm320_allocateheap.c | 2 +- arch/arm/src/efm32/efm32_idle.c | 2 +- arch/arm/src/imx/imx_allocateheap.c | 2 +- arch/arm/src/kinetis/kinetis_allocateheap.c | 4 ++-- arch/arm/src/kinetis/kinetis_idle.c | 2 +- arch/arm/src/kl/kl_idle.c | 2 +- arch/arm/src/lpc11xx/lpc11_idle.c | 2 +- arch/arm/src/lpc17xx/lpc17_allocateheap.c | 4 ++-- arch/arm/src/lpc17xx/lpc17_idle.c | 2 +- arch/arm/src/lpc31xx/lpc31_allocateheap.c | 2 +- arch/arm/src/lpc43xx/lpc43_allocateheap.c | 2 +- arch/arm/src/lpc43xx/lpc43_idle.c | 2 +- arch/arm/src/nuc1xx/nuc_idle.c | 2 +- arch/arm/src/sam34/sam_allocateheap.c | 4 ++-- arch/arm/src/sama5/sam_allocateheap.c | 4 ++-- arch/arm/src/samdl/sam_idle.c | 2 +- arch/arm/src/samv7/sam_allocateheap.c | 4 ++-- arch/arm/src/stm32/stm32_allocateheap.c | 4 ++-- arch/arm/src/stm32/stm32_idle.c | 2 +- arch/arm/src/stm32f7/stm32_allocateheap.c | 4 ++-- arch/arm/src/str71x/str71x_decodeirq.c | 4 ++-- arch/arm/src/tiva/tiva_allocateheap.c | 4 ++-- arch/avr/src/avr/up_createstack.c | 2 +- arch/avr/src/avr/up_doirq.c | 2 +- arch/avr/src/avr/up_sigdeliver.c | 2 +- arch/avr/src/avr32/up_createstack.c | 2 +- arch/avr/src/avr32/up_doirq.c | 2 +- arch/avr/src/avr32/up_sigdeliver.c | 2 +- arch/avr/src/common/up_allocateheap.c | 2 +- arch/avr/src/common/up_assert.c | 4 ++-- arch/avr/src/common/up_initialize.c | 2 +- arch/hc/src/common/up_allocateheap.c | 2 +- arch/hc/src/common/up_createstack.c | 2 +- arch/hc/src/common/up_doirq.c | 2 +- arch/hc/src/common/up_initialize.c | 2 +- arch/hc/src/m9s12/m9s12_assert.c | 4 ++-- arch/mips/src/common/up_allocateheap.c | 2 +- arch/mips/src/common/up_createstack.c | 2 +- arch/mips/src/common/up_initialize.c | 2 +- arch/mips/src/mips32/up_assert.c | 4 ++-- arch/mips/src/mips32/up_doirq.c | 2 +- arch/mips/src/mips32/up_sigdeliver.c | 2 +- arch/mips/src/pic32mx/pic32mx-decodeirq.c | 2 +- arch/mips/src/pic32mx/pic32mx-exception.c | 2 +- arch/mips/src/pic32mz/pic32mz-decodeirq.c | 2 +- arch/mips/src/pic32mz/pic32mz-exception.c | 2 +- arch/sh/src/common/up_allocateheap.c | 2 +- arch/sh/src/common/up_assert.c | 4 ++-- arch/sh/src/common/up_createstack.c | 2 +- arch/sh/src/common/up_doirq.c | 2 +- arch/sh/src/common/up_initialize.c | 2 +- arch/sh/src/m16c/m16c_sigdeliver.c | 2 +- arch/sh/src/sh1/sh1_sigdeliver.c | 2 +- arch/x86/src/common/up_allocateheap.c | 2 +- arch/x86/src/common/up_assert.c | 4 ++-- arch/x86/src/common/up_initialize.c | 2 +- arch/x86/src/i486/up_createstack.c | 2 +- arch/x86/src/i486/up_sigdeliver.c | 2 +- arch/x86/src/qemu/qemu_handlers.c | 10 +++++----- arch/z16/src/common/up_allocateheap.c | 2 +- arch/z16/src/common/up_assert.c | 4 ++-- arch/z16/src/common/up_createstack.c | 2 +- arch/z16/src/common/up_doirq.c | 2 +- arch/z16/src/common/up_idle.c | 2 +- arch/z16/src/common/up_initialize.c | 2 +- arch/z16/src/common/up_sigdeliver.c | 2 +- arch/z80/src/common/up_allocateheap.c | 2 +- arch/z80/src/common/up_assert.c | 4 ++-- arch/z80/src/common/up_createstack.c | 2 +- arch/z80/src/common/up_doirq.c | 2 +- arch/z80/src/common/up_idle.c | 2 +- arch/z80/src/common/up_initialize.c | 2 +- arch/z80/src/ez80/ez80_sigdeliver.c | 2 +- arch/z80/src/z180/z180_sigdeliver.c | 2 +- arch/z80/src/z8/z8_sigdeliver.c | 2 +- arch/z80/src/z80/z80_sigdeliver.c | 2 +- 91 files changed, 116 insertions(+), 116 deletions(-) diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index f8cd706fa56..c9ed3cff3b0 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -316,7 +316,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -343,7 +343,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/arm/up_doirq.c b/arch/arm/src/arm/up_doirq.c index 35ba735cdb6..7df75a436d1 100644 --- a/arch/arm/src/arm/up_doirq.c +++ b/arch/arm/src/arm/up_doirq.c @@ -74,7 +74,7 @@ void up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c index 625a0993ae5..38127a706a2 100644 --- a/arch/arm/src/arm/up_sigdeliver.c +++ b/arch/arm/src/arm/up_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c index 4c570637a5e..9f196926a33 100644 --- a/arch/arm/src/armv6-m/up_assert.c +++ b/arch/arm/src/armv6-m/up_assert.c @@ -371,7 +371,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -398,7 +398,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/armv6-m/up_doirq.c b/arch/arm/src/armv6-m/up_doirq.c index 54557585f22..4be88b4c088 100644 --- a/arch/arm/src/armv6-m/up_doirq.c +++ b/arch/arm/src/armv6-m/up_doirq.c @@ -72,7 +72,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c index f0f4dd54bfe..153c9bd4d05 100644 --- a/arch/arm/src/armv6-m/up_sigdeliver.c +++ b/arch/arm/src/armv6-m/up_sigdeliver.c @@ -98,7 +98,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 19630740eb6..166de067acc 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -371,7 +371,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -397,7 +397,7 @@ void up_assert(const uint8_t *filename, int lineno) #ifdef CONFIG_PRINT_TASKNAME struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c index d126f565dbc..f62fc7f60c1 100644 --- a/arch/arm/src/armv7-a/arm_doirq.c +++ b/arch/arm/src/armv7-a/arm_doirq.c @@ -74,7 +74,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 0ea2b4c13e1..1cfa8884219 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index 0a264cb8cb2..74ac5e30e5e 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -380,7 +380,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -407,7 +407,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c index 0582000c582..27740d2704f 100644 --- a/arch/arm/src/armv7-m/up_doirq.c +++ b/arch/arm/src/armv7-m/up_doirq.c @@ -72,7 +72,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index df5c17fbcfb..085380fb5a9 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/common/up_allocateheap.c b/arch/arm/src/common/up_allocateheap.c index f1f219ebc8e..b4aa3d05d00 100644 --- a/arch/arm/src/common/up_allocateheap.c +++ b/arch/arm/src/common/up_allocateheap.c @@ -142,14 +142,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; #else /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/common/up_createstack.c b/arch/arm/src/common/up_createstack.c index 7cec83a18ff..5d03ee4556e 100644 --- a/arch/arm/src/common/up_createstack.c +++ b/arch/arm/src/common/up_createstack.c @@ -227,7 +227,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size); #endif - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index 21b5ea2d6ef..2cb332671b6 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -275,5 +275,5 @@ void up_initialize(void) /* Initialize the L2 cache if present and selected */ up_l2ccinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/arm/src/dm320/dm320_allocateheap.c b/arch/arm/src/dm320/dm320_allocateheap.c index c6802c4c5c6..d1a96f8020a 100644 --- a/arch/arm/src/dm320/dm320_allocateheap.c +++ b/arch/arm/src/dm320/dm320_allocateheap.c @@ -85,7 +85,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack; } diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c index 5740d14f6a5..75c9905c1b9 100644 --- a/arch/arm/src/efm32/efm32_idle.c +++ b/arch/arm/src/efm32/efm32_idle.c @@ -61,7 +61,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/imx/imx_allocateheap.c b/arch/arm/src/imx/imx_allocateheap.c index 2447d6a2b2b..179c4751eda 100644 --- a/arch/arm/src/imx/imx_allocateheap.c +++ b/arch/arm/src/imx/imx_allocateheap.c @@ -85,7 +85,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack; } diff --git a/arch/arm/src/kinetis/kinetis_allocateheap.c b/arch/arm/src/kinetis/kinetis_allocateheap.c index ac96b2d455d..1eb21eeb4d9 100644 --- a/arch/arm/src/kinetis/kinetis_allocateheap.c +++ b/arch/arm/src/kinetis/kinetis_allocateheap.c @@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/kinetis/kinetis_idle.c b/arch/arm/src/kinetis/kinetis_idle.c index 8e58beb8841..b47e56a668b 100644 --- a/arch/arm/src/kinetis/kinetis_idle.c +++ b/arch/arm/src/kinetis/kinetis_idle.c @@ -54,7 +54,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c index a198ad8b27d..8e34a7a1a40 100644 --- a/arch/arm/src/kl/kl_idle.c +++ b/arch/arm/src/kl/kl_idle.c @@ -58,7 +58,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/lpc11xx/lpc11_idle.c b/arch/arm/src/lpc11xx/lpc11_idle.c index f258c2b0c96..e45cf3068b9 100644 --- a/arch/arm/src/lpc11xx/lpc11_idle.c +++ b/arch/arm/src/lpc11xx/lpc11_idle.c @@ -53,7 +53,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c index e6969326b65..20568f0457f 100644 --- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c +++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c @@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -260,7 +260,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/lpc17xx/lpc17_idle.c b/arch/arm/src/lpc17xx/lpc17_idle.c index baf62b0155b..db90892e448 100644 --- a/arch/arm/src/lpc17xx/lpc17_idle.c +++ b/arch/arm/src/lpc17xx/lpc17_idle.c @@ -55,7 +55,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/arch/arm/src/lpc31xx/lpc31_allocateheap.c index b6d77b190a1..9c54871eaf7 100644 --- a/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -180,7 +180,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = LPC31_HEAP_VEND - g_idle_topstack; } diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c index b914b4d8bb7..243ea98b61c 100644 --- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c +++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { /* Start with the first SRAM region */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c index 029a55f1f89..476c36c91f4 100644 --- a/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/arch/arm/src/lpc43xx/lpc43_idle.c @@ -57,7 +57,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c index 3236b572c86..d656767e7ed 100644 --- a/arch/arm/src/nuc1xx/nuc_idle.c +++ b/arch/arm/src/nuc1xx/nuc_idle.c @@ -58,7 +58,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c index 0f0b981ee48..3e1d5e6efe9 100644 --- a/arch/arm/src/sam34/sam_allocateheap.c +++ b/arch/arm/src/sam34/sam_allocateheap.c @@ -230,7 +230,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -241,7 +241,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index 33e4fe1c6a8..14388795f98 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -258,7 +258,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * heap is at the end of BSS through the configured end of SDRAM. */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)&_ebss; *heap_size = SAMA5_PRIMARY_HEAP_END - (size_t)&_ebss; @@ -267,7 +267,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * IDLE stack through the configured end of ISRAM. */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = SAMA5_PRIMARY_HEAP_END - g_idle_topstack; #endif diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c index f0baac5f9b0..743b26a4f78 100644 --- a/arch/arm/src/samdl/sam_idle.c +++ b/arch/arm/src/samdl/sam_idle.c @@ -58,7 +58,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c index 65ba3f425ff..1e8dc087963 100644 --- a/arch/arm/src/samv7/sam_allocateheap.c +++ b/arch/arm/src/samv7/sam_allocateheap.c @@ -237,7 +237,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 8350b859e18..8a844b6d22d 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -511,7 +511,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -526,7 +526,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = SRAM1_END - g_idle_topstack; diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c index 7108956cae4..2934cc3e4c3 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/stm32/stm32_idle.c @@ -60,7 +60,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 628a83ff4fb..919890b8334 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -240,7 +240,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -255,7 +255,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = SRAM1_END - g_idle_topstack; diff --git a/arch/arm/src/str71x/str71x_decodeirq.c b/arch/arm/src/str71x/str71x_decodeirq.c index 363590f2666..72e4da677cb 100644 --- a/arch/arm/src/str71x/str71x_decodeirq.c +++ b/arch/arm/src/str71x/str71x_decodeirq.c @@ -90,7 +90,7 @@ void up_decodeirq(uint32_t *regs) { #ifdef CONFIG_SUPPRESS_INTERRUPTS - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); lowsyslog(LOG_ERR, "Unexpected IRQ\n"); current_regs = regs; PANIC(); @@ -101,7 +101,7 @@ void up_decodeirq(uint32_t *regs) * info from CIC register without the setup). */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); irq = getreg32(STR71X_EIC_IVR); /* Verify that the resulting IRQ number is valid */ diff --git a/arch/arm/src/tiva/tiva_allocateheap.c b/arch/arm/src/tiva/tiva_allocateheap.c index 4bca5ff2bd7..06df87bb31b 100644 --- a/arch/arm/src/tiva/tiva_allocateheap.c +++ b/arch/arm/src/tiva/tiva_allocateheap.c @@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/avr/src/avr/up_createstack.c b/arch/avr/src/avr/up_createstack.c index 3a30888ab6b..781258e702d 100644 --- a/arch/avr/src/avr/up_createstack.c +++ b/arch/avr/src/avr/up_createstack.c @@ -160,7 +160,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR void *)top_of_stack; tcb->adj_stack_size = stack_size; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/avr/src/avr/up_doirq.c b/arch/avr/src/avr/up_doirq.c index a6768cf1994..b692420a4d4 100644 --- a/arch/avr/src/avr/up_doirq.c +++ b/arch/avr/src/avr/up_doirq.c @@ -72,7 +72,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c index ae2d70f8e34..92604bcf14d 100644 --- a/arch/avr/src/avr/up_sigdeliver.c +++ b/arch/avr/src/avr/up_sigdeliver.c @@ -92,7 +92,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/avr/src/avr32/up_createstack.c b/arch/avr/src/avr32/up_createstack.c index f4ad76a679e..db76abc38d9 100644 --- a/arch/avr/src/avr32/up_createstack.c +++ b/arch/avr/src/avr32/up_createstack.c @@ -186,7 +186,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR void *)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/avr/src/avr32/up_doirq.c b/arch/avr/src/avr32/up_doirq.c index ba0dfe4cca2..6acf3c9f099 100644 --- a/arch/avr/src/avr32/up_doirq.c +++ b/arch/avr/src/avr32/up_doirq.c @@ -74,7 +74,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c index 691fe8cc8fc..e4be7e7d164 100644 --- a/arch/avr/src/avr32/up_sigdeliver.c +++ b/arch/avr/src/avr32/up_sigdeliver.c @@ -96,7 +96,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/avr/src/common/up_allocateheap.c b/arch/avr/src/common/up_allocateheap.c index 7e2c03022a2..052876f6740 100644 --- a/arch/avr/src/common/up_allocateheap.c +++ b/arch/avr/src/common/up_allocateheap.c @@ -82,7 +82,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c index a1a22956856..cddb4a7c861 100644 --- a/arch/avr/src/common/up_assert.c +++ b/arch/avr/src/common/up_assert.c @@ -111,7 +111,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -163,7 +163,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c index fdd05dd72f2..f44b421c6d0 100644 --- a/arch/avr/src/common/up_initialize.c +++ b/arch/avr/src/common/up_initialize.c @@ -286,6 +286,6 @@ void up_initialize(void) up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/hc/src/common/up_allocateheap.c b/arch/hc/src/common/up_allocateheap.c index fb1a24f177d..946fbf69ec1 100644 --- a/arch/hc/src/common/up_allocateheap.c +++ b/arch/hc/src/common/up_allocateheap.c @@ -81,7 +81,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/hc/src/common/up_createstack.c b/arch/hc/src/common/up_createstack.c index 278a643f7bc..9afb471e470 100644 --- a/arch/hc/src/common/up_createstack.c +++ b/arch/hc/src/common/up_createstack.c @@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/hc/src/common/up_doirq.c b/arch/hc/src/common/up_doirq.c index 1a81731dc04..a0cb7998aa2 100644 --- a/arch/hc/src/common/up_doirq.c +++ b/arch/hc/src/common/up_doirq.c @@ -74,7 +74,7 @@ uint8_t *up_doirq(int irq, uint8_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c index 315064354f6..5628c3aaecd 100644 --- a/arch/hc/src/common/up_initialize.c +++ b/arch/hc/src/common/up_initialize.c @@ -210,5 +210,5 @@ void up_initialize(void) up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c index efc5d6492a0..a99da66185d 100644 --- a/arch/hc/src/m9s12/m9s12_assert.c +++ b/arch/hc/src/m9s12/m9s12_assert.c @@ -299,7 +299,7 @@ static void _up_assert(int errorcode) for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -326,7 +326,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/mips/src/common/up_allocateheap.c b/arch/mips/src/common/up_allocateheap.c index 1e99b86ceeb..7bcb04de738 100644 --- a/arch/mips/src/common/up_allocateheap.c +++ b/arch/mips/src/common/up_allocateheap.c @@ -82,7 +82,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/mips/src/common/up_createstack.c b/arch/mips/src/common/up_createstack.c index 541633683b9..5540b8bc4f8 100644 --- a/arch/mips/src/common/up_createstack.c +++ b/arch/mips/src/common/up_createstack.c @@ -206,7 +206,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index 4ee09a2acac..1274772249a 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -211,5 +211,5 @@ void up_initialize(void) /* Initialize USB -- device and/or host */ up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index 3ddb82a87d3..a02750874e3 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -111,7 +111,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -163,7 +163,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index 6c55ed9cc99..debc56b6421 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -74,7 +74,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c index 74c2c5b170d..d255b2b820f 100644 --- a/arch/mips/src/mips32/up_sigdeliver.c +++ b/arch/mips/src/mips32/up_sigdeliver.c @@ -94,7 +94,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c index f9cf81d467e..24b13217651 100644 --- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c +++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c @@ -97,7 +97,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Save the current value of current_regs (to support nested interrupt * handling). Then set current_regs to regs, indicating that this is diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c index aaf7b4805f4..0ca9bdfa3e8 100644 --- a/arch/mips/src/pic32mx/pic32mx-exception.c +++ b/arch/mips/src/pic32mx/pic32mx-exception.c @@ -94,7 +94,7 @@ uint32_t *pic32mx_exception(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_DEBUG /* Get the cause of the exception from the CAUSE register */ diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c index f2766ff3317..bcf35488f86 100644 --- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c +++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c @@ -97,7 +97,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Save the current value of current_regs (to support nested interrupt * handling). Then set current_regs to regs, indicating that this is diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c index 81766676ac6..3b6b3bb3f46 100644 --- a/arch/mips/src/pic32mz/pic32mz-exception.c +++ b/arch/mips/src/pic32mz/pic32mz-exception.c @@ -94,7 +94,7 @@ uint32_t *pic32mz_exception(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_DEBUG /* Get the cause of the exception from the CAUSE register */ diff --git a/arch/sh/src/common/up_allocateheap.c b/arch/sh/src/common/up_allocateheap.c index b1a2c818b6e..ddf287983a1 100644 --- a/arch/sh/src/common/up_allocateheap.c +++ b/arch/sh/src/common/up_allocateheap.c @@ -81,7 +81,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c index 9568b33ae0f..2a3b89eaeb9 100644 --- a/arch/sh/src/common/up_assert.c +++ b/arch/sh/src/common/up_assert.c @@ -99,7 +99,7 @@ static void _up_assert(int errorcode) for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -151,7 +151,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/sh/src/common/up_createstack.c b/arch/sh/src/common/up_createstack.c index 825efb8cf3b..f52f03386ed 100644 --- a/arch/sh/src/common/up_createstack.c +++ b/arch/sh/src/common/up_createstack.c @@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/sh/src/common/up_doirq.c b/arch/sh/src/common/up_doirq.c index 6c9854ba754..530a6e41af2 100644 --- a/arch/sh/src/common/up_doirq.c +++ b/arch/sh/src/common/up_doirq.c @@ -73,7 +73,7 @@ uint32_t *up_doirq(int irq, uint32_t* regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/sh/src/common/up_initialize.c b/arch/sh/src/common/up_initialize.c index fb38f4a8288..f4e067489f8 100644 --- a/arch/sh/src/common/up_initialize.c +++ b/arch/sh/src/common/up_initialize.c @@ -200,5 +200,5 @@ void up_initialize(void) up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/sh/src/m16c/m16c_sigdeliver.c b/arch/sh/src/m16c/m16c_sigdeliver.c index 817d3bc02d4..e27ef794522 100644 --- a/arch/sh/src/m16c/m16c_sigdeliver.c +++ b/arch/sh/src/m16c/m16c_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/sh/src/sh1/sh1_sigdeliver.c b/arch/sh/src/sh1/sh1_sigdeliver.c index c395d49c6ac..7d53f29c654 100644 --- a/arch/sh/src/sh1/sh1_sigdeliver.c +++ b/arch/sh/src/sh1/sh1_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/x86/src/common/up_allocateheap.c b/arch/x86/src/common/up_allocateheap.c index 22b1ed5ba35..5fb0a9f288f 100644 --- a/arch/x86/src/common/up_allocateheap.c +++ b/arch/x86/src/common/up_allocateheap.c @@ -82,7 +82,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c index a3b82d3b7f4..025f121f125 100644 --- a/arch/x86/src/common/up_assert.c +++ b/arch/x86/src/common/up_assert.c @@ -261,7 +261,7 @@ static void _up_assert(int errorcode) for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -288,7 +288,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/x86/src/common/up_initialize.c b/arch/x86/src/common/up_initialize.c index f720c2ae107..21d4eba7cb7 100644 --- a/arch/x86/src/common/up_initialize.c +++ b/arch/x86/src/common/up_initialize.c @@ -211,5 +211,5 @@ void up_initialize(void) /* Initialize USB -- device and/or host */ up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/x86/src/i486/up_createstack.c b/arch/x86/src/i486/up_createstack.c index 8a7146f32a1..1d9b1008d09 100644 --- a/arch/x86/src/i486/up_createstack.c +++ b/arch/x86/src/i486/up_createstack.c @@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c index 0996e7eb92f..4824bbb4737 100644 --- a/arch/x86/src/i486/up_sigdeliver.c +++ b/arch/x86/src/i486/up_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c index fce1969faa5..26a2de452ac 100644 --- a/arch/x86/src/qemu/qemu_handlers.c +++ b/arch/x86/src/qemu/qemu_handlers.c @@ -88,7 +88,7 @@ static void idt_outb(uint8_t val, uint16_t addr) #ifndef CONFIG_SUPPRESS_INTERRUPTS static uint32_t *common_handler(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Current regs non-zero indicates that we are processing an interrupt; * current_regs is also used to manage interrupt level context switches. @@ -163,7 +163,7 @@ static uint32_t *common_handler(int irq, uint32_t *regs) uint32_t *isr_handler(uint32_t *regs) { #ifdef CONFIG_SUPPRESS_INTERRUPTS - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); PANIC(); /* Doesn't return */ return regs; /* To keep the compiler happy */ #else @@ -171,7 +171,7 @@ uint32_t *isr_handler(uint32_t *regs) /* Dispatch the interrupt */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); ret = common_handler((int)regs[REG_IRQNO], regs); board_led_off(LED_INIRQ); return ret; @@ -189,14 +189,14 @@ uint32_t *isr_handler(uint32_t *regs) uint32_t *irq_handler(uint32_t *regs) { #ifdef CONFIG_SUPPRESS_INTERRUPTS - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); PANIC(); /* Doesn't return */ return regs; /* To keep the compiler happy */ #else uint32_t *ret; int irq; - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Get the IRQ number */ diff --git a/arch/z16/src/common/up_allocateheap.c b/arch/z16/src/common/up_allocateheap.c index 57a4ade72e2..f307a8a73e2 100644 --- a/arch/z16/src/common/up_allocateheap.c +++ b/arch/z16/src/common/up_allocateheap.c @@ -92,7 +92,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { *heap_start = (FAR void*)CONFIG_HEAP1_BASE; *heap_size = CONFIG_HEAP1_END - CONFIG_HEAP1_BASE; - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); } /**************************************************************************** diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c index 55d98535785..cf55172dca8 100644 --- a/arch/z16/src/common/up_assert.c +++ b/arch/z16/src/common/up_assert.c @@ -98,7 +98,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -154,7 +154,7 @@ void up_assert(void) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_HAVE_FILENAME #if CONFIG_TASK_NAME_SIZE > 0 diff --git a/arch/z16/src/common/up_createstack.c b/arch/z16/src/common/up_createstack.c index e395bae4369..c4d55370408 100644 --- a/arch/z16/src/common/up_createstack.c +++ b/arch/z16/src/common/up_createstack.c @@ -166,7 +166,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c index 9d9a38361d5..38f89c49e0d 100644 --- a/arch/z16/src/common/up_doirq.c +++ b/arch/z16/src/common/up_doirq.c @@ -82,7 +82,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs) { FAR chipreg_t *ret = regs; - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/z16/src/common/up_idle.c b/arch/z16/src/common/up_idle.c index 8bbbc7c04b6..364fd615e94 100644 --- a/arch/z16/src/common/up_idle.c +++ b/arch/z16/src/common/up_idle.c @@ -88,7 +88,7 @@ void up_idle(void) g_ledtoggle++; if (g_ledtoggle == 0x80) { - board_led_on(LED_IDLE); + board_autoled_on(LED_IDLE); } else if (g_ledtoggle == 0x00) { diff --git a/arch/z16/src/common/up_initialize.c b/arch/z16/src/common/up_initialize.c index 79cf4617ed0..747d448b0cb 100644 --- a/arch/z16/src/common/up_initialize.c +++ b/arch/z16/src/common/up_initialize.c @@ -212,5 +212,5 @@ void up_initialize(void) (void)tun_initialize(); #endif - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/z16/src/common/up_sigdeliver.c b/arch/z16/src/common/up_sigdeliver.c index d1113addc55..893a7661213 100644 --- a/arch/z16/src/common/up_sigdeliver.c +++ b/arch/z16/src/common/up_sigdeliver.c @@ -94,7 +94,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/common/up_allocateheap.c b/arch/z80/src/common/up_allocateheap.c index 4cb3b02ff61..7ea677c5f94 100644 --- a/arch/z80/src/common/up_allocateheap.c +++ b/arch/z80/src/common/up_allocateheap.c @@ -101,7 +101,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { *heap_start = (FAR void*)CONFIG_HEAP1_BASE; *heap_size = CONFIG_HEAP1_END - CONFIG_HEAP1_BASE; - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); } /**************************************************************************** diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c index be886dc44db..f6d92719a5e 100644 --- a/arch/z80/src/common/up_assert.c +++ b/arch/z80/src/common/up_assert.c @@ -97,7 +97,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -153,7 +153,7 @@ void up_assert(void) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_HAVE_FILENAME #if CONFIG_TASK_NAME_SIZE > 0 diff --git a/arch/z80/src/common/up_createstack.c b/arch/z80/src/common/up_createstack.c index e3880a0c612..60c4733d99e 100644 --- a/arch/z80/src/common/up_createstack.c +++ b/arch/z80/src/common/up_createstack.c @@ -184,7 +184,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c index f123782c2c7..bd9d0adbc3b 100644 --- a/arch/z80/src/common/up_doirq.c +++ b/arch/z80/src/common/up_doirq.c @@ -74,7 +74,7 @@ FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/z80/src/common/up_idle.c b/arch/z80/src/common/up_idle.c index 29ac104df02..bb6c028a797 100644 --- a/arch/z80/src/common/up_idle.c +++ b/arch/z80/src/common/up_idle.c @@ -88,7 +88,7 @@ void up_idle(void) g_ledtoggle++; if (g_ledtoggle == 0x80) { - board_led_on(LED_IDLE); + board_autoled_on(LED_IDLE); } else if (g_ledtoggle == 0x00) { diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c index 12e5cff6d85..2bc7420c391 100644 --- a/arch/z80/src/common/up_initialize.c +++ b/arch/z80/src/common/up_initialize.c @@ -195,5 +195,5 @@ void up_initialize(void) (void)tun_initialize(); #endif - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c index 3b3f5ec8605..a9a2e3f3c6d 100644 --- a/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/arch/z80/src/ez80/ez80_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/z180/z180_sigdeliver.c b/arch/z80/src/z180/z180_sigdeliver.c index 484508e831f..35b1647f21a 100644 --- a/arch/z80/src/z180/z180_sigdeliver.c +++ b/arch/z80/src/z180/z180_sigdeliver.c @@ -92,7 +92,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c index fed589ef775..ea2a589d301 100644 --- a/arch/z80/src/z8/z8_sigdeliver.c +++ b/arch/z80/src/z8/z8_sigdeliver.c @@ -107,7 +107,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c index 60058879b58..0e19072b5fa 100644 --- a/arch/z80/src/z80/z80_sigdeliver.c +++ b/arch/z80/src/z80/z80_sigdeliver.c @@ -92,7 +92,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); From 79df5616694665f8a9944a3537e6888ffe1e0e02 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 1 Nov 2015 09:09:36 -0600 Subject: [PATCH 07/10] Rename board_led_off to board_autoled_off --- arch/arm/src/arm/up_assert.c | 2 +- arch/arm/src/arm/up_doirq.c | 2 +- arch/arm/src/arm/up_sigdeliver.c | 2 +- arch/arm/src/armv6-m/up_assert.c | 2 +- arch/arm/src/armv6-m/up_doirq.c | 2 +- arch/arm/src/armv6-m/up_sigdeliver.c | 2 +- arch/arm/src/armv7-a/arm_assert.c | 2 +- arch/arm/src/armv7-a/arm_doirq.c | 2 +- arch/arm/src/armv7-a/arm_sigdeliver.c | 2 +- arch/arm/src/armv7-m/up_assert.c | 2 +- arch/arm/src/armv7-m/up_doirq.c | 2 +- arch/arm/src/armv7-m/up_sigdeliver.c | 2 +- arch/arm/src/efm32/efm32_idle.c | 2 +- arch/arm/src/kinetis/kinetis_idle.c | 2 +- arch/arm/src/kl/kl_idle.c | 2 +- arch/arm/src/lpc11xx/lpc11_idle.c | 2 +- arch/arm/src/lpc17xx/lpc17_idle.c | 2 +- arch/arm/src/lpc43xx/lpc43_idle.c | 2 +- arch/arm/src/nuc1xx/nuc_idle.c | 2 +- arch/arm/src/samdl/sam_idle.c | 2 +- arch/arm/src/stm32/stm32_idle.c | 2 +- arch/arm/src/str71x/str71x_decodeirq.c | 2 +- arch/avr/src/avr/up_doirq.c | 2 +- arch/avr/src/avr/up_sigdeliver.c | 2 +- arch/avr/src/avr32/up_doirq.c | 2 +- arch/avr/src/avr32/up_sigdeliver.c | 2 +- arch/avr/src/common/up_assert.c | 2 +- arch/hc/src/common/up_doirq.c | 2 +- arch/hc/src/m9s12/m9s12_assert.c | 2 +- arch/mips/src/mips32/up_assert.c | 2 +- arch/mips/src/mips32/up_doirq.c | 2 +- arch/mips/src/mips32/up_sigdeliver.c | 2 +- arch/mips/src/pic32mx/pic32mx-decodeirq.c | 4 ++-- arch/mips/src/pic32mz/pic32mz-decodeirq.c | 4 ++-- arch/sh/src/common/up_assert.c | 2 +- arch/sh/src/common/up_doirq.c | 2 +- arch/sh/src/m16c/m16c_sigdeliver.c | 2 +- arch/sh/src/sh1/sh1_sigdeliver.c | 2 +- arch/x86/src/common/up_assert.c | 2 +- arch/x86/src/i486/up_sigdeliver.c | 2 +- arch/x86/src/qemu/qemu_handlers.c | 4 ++-- arch/z16/src/common/up_assert.c | 2 +- arch/z16/src/common/up_doirq.c | 2 +- arch/z16/src/common/up_idle.c | 2 +- arch/z16/src/common/up_sigdeliver.c | 2 +- arch/z80/src/common/up_assert.c | 2 +- arch/z80/src/common/up_doirq.c | 2 +- arch/z80/src/common/up_idle.c | 2 +- arch/z80/src/ez80/ez80_sigdeliver.c | 2 +- arch/z80/src/z180/z180_sigdeliver.c | 2 +- arch/z80/src/z8/z8_sigdeliver.c | 2 +- arch/z80/src/z80/z80_sigdeliver.c | 2 +- 52 files changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index c9ed3cff3b0..28b7776f976 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -318,7 +318,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/arm/up_doirq.c b/arch/arm/src/arm/up_doirq.c index 7df75a436d1..52603f435d5 100644 --- a/arch/arm/src/arm/up_doirq.c +++ b/arch/arm/src/arm/up_doirq.c @@ -130,5 +130,5 @@ void up_doirq(int irq, uint32_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); } diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c index 38127a706a2..eab3193bf00 100644 --- a/arch/arm/src/arm/up_sigdeliver.c +++ b/arch/arm/src/arm/up_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c index 9f196926a33..0e05acdd4a7 100644 --- a/arch/arm/src/armv6-m/up_assert.c +++ b/arch/arm/src/armv6-m/up_assert.c @@ -373,7 +373,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/armv6-m/up_doirq.c b/arch/arm/src/armv6-m/up_doirq.c index 4be88b4c088..3edc9d3b82e 100644 --- a/arch/arm/src/armv6-m/up_doirq.c +++ b/arch/arm/src/armv6-m/up_doirq.c @@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs) current_regs = savestate; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c index 153c9bd4d05..b5630625025 100644 --- a/arch/arm/src/armv6-m/up_sigdeliver.c +++ b/arch/arm/src/armv6-m/up_sigdeliver.c @@ -143,7 +143,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 166de067acc..a814a80bb02 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -373,7 +373,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c index f62fc7f60c1..79a5ed5f557 100644 --- a/arch/arm/src/armv7-a/arm_doirq.c +++ b/arch/arm/src/armv7-a/arm_doirq.c @@ -128,6 +128,6 @@ uint32_t *arm_doirq(int irq, uint32_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 1cfa8884219..1f52b5ec913 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index 74ac5e30e5e..b18bc1e265c 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -382,7 +382,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c index 27740d2704f..71c1fc7d11e 100644 --- a/arch/arm/src/armv7-m/up_doirq.c +++ b/arch/arm/src/armv7-m/up_doirq.c @@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs) current_regs = savestate; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index 085380fb5a9..8d24cf9e460 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -146,7 +146,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c index 75c9905c1b9..9e0c218e0e9 100644 --- a/arch/arm/src/efm32/efm32_idle.c +++ b/arch/arm/src/efm32/efm32_idle.c @@ -62,7 +62,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/kinetis/kinetis_idle.c b/arch/arm/src/kinetis/kinetis_idle.c index b47e56a668b..71ee037c14c 100644 --- a/arch/arm/src/kinetis/kinetis_idle.c +++ b/arch/arm/src/kinetis/kinetis_idle.c @@ -55,7 +55,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c index 8e34a7a1a40..ce7ec7ff356 100644 --- a/arch/arm/src/kl/kl_idle.c +++ b/arch/arm/src/kl/kl_idle.c @@ -59,7 +59,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/lpc11xx/lpc11_idle.c b/arch/arm/src/lpc11xx/lpc11_idle.c index e45cf3068b9..802105dbc19 100644 --- a/arch/arm/src/lpc11xx/lpc11_idle.c +++ b/arch/arm/src/lpc11xx/lpc11_idle.c @@ -54,7 +54,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/lpc17xx/lpc17_idle.c b/arch/arm/src/lpc17xx/lpc17_idle.c index db90892e448..71d940a6ab5 100644 --- a/arch/arm/src/lpc17xx/lpc17_idle.c +++ b/arch/arm/src/lpc17xx/lpc17_idle.c @@ -56,7 +56,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c index 476c36c91f4..8b15bb079a4 100644 --- a/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/arch/arm/src/lpc43xx/lpc43_idle.c @@ -58,7 +58,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c index d656767e7ed..5414c70e74a 100644 --- a/arch/arm/src/nuc1xx/nuc_idle.c +++ b/arch/arm/src/nuc1xx/nuc_idle.c @@ -59,7 +59,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c index 743b26a4f78..b661733d745 100644 --- a/arch/arm/src/samdl/sam_idle.c +++ b/arch/arm/src/samdl/sam_idle.c @@ -59,7 +59,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c index 2934cc3e4c3..ce95c861ee9 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/stm32/stm32_idle.c @@ -61,7 +61,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/str71x/str71x_decodeirq.c b/arch/arm/src/str71x/str71x_decodeirq.c index 72e4da677cb..9e28a1b4aee 100644 --- a/arch/arm/src/str71x/str71x_decodeirq.c +++ b/arch/arm/src/str71x/str71x_decodeirq.c @@ -138,6 +138,6 @@ void up_decodeirq(uint32_t *regs) PANIC(); /* Normally never happens */ } #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif } diff --git a/arch/avr/src/avr/up_doirq.c b/arch/avr/src/avr/up_doirq.c index b692420a4d4..88cbcce8700 100644 --- a/arch/avr/src/avr/up_doirq.c +++ b/arch/avr/src/avr/up_doirq.c @@ -112,7 +112,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs) current_regs = savestate; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c index 92604bcf14d..0db6a03344f 100644 --- a/arch/avr/src/avr/up_sigdeliver.c +++ b/arch/avr/src/avr/up_sigdeliver.c @@ -147,7 +147,7 @@ void up_sigdeliver(void) * to the size of register save structure size will protect its contents. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/avr/src/avr32/up_doirq.c b/arch/avr/src/avr32/up_doirq.c index 6acf3c9f099..14b4d6a7ae9 100644 --- a/arch/avr/src/avr32/up_doirq.c +++ b/arch/avr/src/avr32/up_doirq.c @@ -133,7 +133,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c index e4be7e7d164..60387714857 100644 --- a/arch/avr/src/avr32/up_sigdeliver.c +++ b/arch/avr/src/avr32/up_sigdeliver.c @@ -150,7 +150,7 @@ void up_sigdeliver(void) * to the size of register save structure size will protect its contents. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c index cddb4a7c861..04c2809052a 100644 --- a/arch/avr/src/common/up_assert.c +++ b/arch/avr/src/common/up_assert.c @@ -113,7 +113,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/hc/src/common/up_doirq.c b/arch/hc/src/common/up_doirq.c index a0cb7998aa2..99e7ba6a64c 100644 --- a/arch/hc/src/common/up_doirq.c +++ b/arch/hc/src/common/up_doirq.c @@ -133,6 +133,6 @@ uint8_t *up_doirq(int irq, uint8_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c index a99da66185d..7f48615c9a0 100644 --- a/arch/hc/src/m9s12/m9s12_assert.c +++ b/arch/hc/src/m9s12/m9s12_assert.c @@ -301,7 +301,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index a02750874e3..c392bf5386c 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -113,7 +113,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index debc56b6421..5cb7fbdbb31 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -143,6 +143,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs) up_enable_irq(irq); #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c index d255b2b820f..060298010c9 100644 --- a/arch/mips/src/mips32/up_sigdeliver.c +++ b/arch/mips/src/mips32/up_sigdeliver.c @@ -136,7 +136,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); /* up_fullcontextrestore() should not return but could if the software diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c index 24b13217651..13144eb67e6 100644 --- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c +++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c @@ -189,11 +189,11 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) current_regs = savestate; if (current_regs == NULL) { - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); } #else current_regs = NULL; - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return regs; diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c index bcf35488f86..632af96b462 100644 --- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c +++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c @@ -189,11 +189,11 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) current_regs = savestate; if (current_regs == NULL) { - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); } #else current_regs = NULL; - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return regs; diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c index 2a3b89eaeb9..3499e9404dc 100644 --- a/arch/sh/src/common/up_assert.c +++ b/arch/sh/src/common/up_assert.c @@ -101,7 +101,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/sh/src/common/up_doirq.c b/arch/sh/src/common/up_doirq.c index 530a6e41af2..dd0edc42db6 100644 --- a/arch/sh/src/common/up_doirq.c +++ b/arch/sh/src/common/up_doirq.c @@ -133,7 +133,7 @@ uint32_t *up_doirq(int irq, uint32_t* regs) current_regs = NULL; } - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return regs; } diff --git a/arch/sh/src/m16c/m16c_sigdeliver.c b/arch/sh/src/m16c/m16c_sigdeliver.c index e27ef794522..220e8e2c280 100644 --- a/arch/sh/src/m16c/m16c_sigdeliver.c +++ b/arch/sh/src/m16c/m16c_sigdeliver.c @@ -136,7 +136,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); #endif } diff --git a/arch/sh/src/sh1/sh1_sigdeliver.c b/arch/sh/src/sh1/sh1_sigdeliver.c index 7d53f29c654..69f5446df56 100644 --- a/arch/sh/src/sh1/sh1_sigdeliver.c +++ b/arch/sh/src/sh1/sh1_sigdeliver.c @@ -133,7 +133,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); #endif } diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c index 025f121f125..0e4761c2bc2 100644 --- a/arch/x86/src/common/up_assert.c +++ b/arch/x86/src/common/up_assert.c @@ -263,7 +263,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c index 4824bbb4737..ddc87e08d85 100644 --- a/arch/x86/src/i486/up_sigdeliver.c +++ b/arch/x86/src/i486/up_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c index 26a2de452ac..0a22d7346f1 100644 --- a/arch/x86/src/qemu/qemu_handlers.c +++ b/arch/x86/src/qemu/qemu_handlers.c @@ -173,7 +173,7 @@ uint32_t *isr_handler(uint32_t *regs) board_autoled_on(LED_INIRQ); ret = common_handler((int)regs[REG_IRQNO], regs); - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return ret; #endif } @@ -220,7 +220,7 @@ uint32_t *irq_handler(uint32_t *regs) /* Dispatch the interrupt */ ret = common_handler(irq, regs); - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return ret; #endif } diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c index cf55172dca8..45537de5993 100644 --- a/arch/z16/src/common/up_assert.c +++ b/arch/z16/src/common/up_assert.c @@ -100,7 +100,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c index 38f89c49e0d..98983538bff 100644 --- a/arch/z16/src/common/up_doirq.c +++ b/arch/z16/src/common/up_doirq.c @@ -124,7 +124,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs) current_regs = savestate; } - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return ret; diff --git a/arch/z16/src/common/up_idle.c b/arch/z16/src/common/up_idle.c index 364fd615e94..01aa0f8d6d8 100644 --- a/arch/z16/src/common/up_idle.c +++ b/arch/z16/src/common/up_idle.c @@ -92,7 +92,7 @@ void up_idle(void) } else if (g_ledtoggle == 0x00) { - board_led_off(LED_IDLE); + board_autoled_off(LED_IDLE); } #endif diff --git a/arch/z16/src/common/up_sigdeliver.c b/arch/z16/src/common/up_sigdeliver.c index 893a7661213..0fc52262737 100644 --- a/arch/z16/src/common/up_sigdeliver.c +++ b/arch/z16/src/common/up_sigdeliver.c @@ -137,7 +137,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); SIGNAL_RETURN(regs); #endif } diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c index f6d92719a5e..a848172b24c 100644 --- a/arch/z80/src/common/up_assert.c +++ b/arch/z80/src/common/up_assert.c @@ -99,7 +99,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c index bd9d0adbc3b..30e2caf9fd1 100644 --- a/arch/z80/src/common/up_doirq.c +++ b/arch/z80/src/common/up_doirq.c @@ -129,7 +129,7 @@ FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs) IRQ_LEAVE(irq); } - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; #endif } diff --git a/arch/z80/src/common/up_idle.c b/arch/z80/src/common/up_idle.c index bb6c028a797..43deca5aa0f 100644 --- a/arch/z80/src/common/up_idle.c +++ b/arch/z80/src/common/up_idle.c @@ -92,7 +92,7 @@ void up_idle(void) } else if (g_ledtoggle == 0x00) { - board_led_off(LED_IDLE); + board_autoled_off(LED_IDLE); } #endif diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c index a9a2e3f3c6d..12db8846aa7 100644 --- a/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/arch/z80/src/ez80/ez80_sigdeliver.c @@ -135,7 +135,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); ez80_restorecontext(regs); #endif } diff --git a/arch/z80/src/z180/z180_sigdeliver.c b/arch/z80/src/z180/z180_sigdeliver.c index 35b1647f21a..58e9aa9c949 100644 --- a/arch/z80/src/z180/z180_sigdeliver.c +++ b/arch/z80/src/z180/z180_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); z180_restoreusercontext(regs); #endif } diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c index ea2a589d301..6605bba7d5e 100644 --- a/arch/z80/src/z8/z8_sigdeliver.c +++ b/arch/z80/src/z8/z8_sigdeliver.c @@ -147,7 +147,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); z8_restorecontext(regs); #endif } diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c index 0e19072b5fa..4e6dafc0bdc 100644 --- a/arch/z80/src/z80/z80_sigdeliver.c +++ b/arch/z80/src/z80/z80_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); z80_restoreusercontext(regs); #endif } From 4c2c9898382e93a52cfd0f039e20797a07aeeab0 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Sun, 1 Nov 2015 17:09:11 -0500 Subject: [PATCH 08/10] STM32 PWM: Add support for multiple output channels --- arch/arm/src/stm32/Kconfig | 1610 ++++++++++++++++++++++++++- arch/arm/src/stm32/chip/stm32_tim.h | 12 +- arch/arm/src/stm32/stm32_pwm.c | 1182 ++++++++++++++++---- arch/arm/src/stm32/stm32_pwm.h | 839 +++++++++++++- 4 files changed, 3349 insertions(+), 294 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 48e01e0efaf..cfe4eb5d09f 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2486,15 +2486,137 @@ config STM32_TIM1_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM1_PWM + +config STM32_TIM1_MODE + int "TIM1 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM1_CHANNEL1 + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM1_CHANNEL1 + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM1_CHANNEL2 + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM1_CHANNEL2 + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM1_CHANNEL3 + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM1_CHANNEL3 + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM1_CHANNEL4 + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM1_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM1_CHANNEL int "TIM1 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM1_PWM ---help--- If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM1_PWM + config STM32_TIM2_PWM bool "TIM2 PWM" default n @@ -2508,15 +2630,137 @@ config STM32_TIM2_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM2_PWM + +config STM32_TIM2_MODE + int "TIM2 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM2_CHANNEL1 + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM2_CHANNEL1 + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM2_CHANNEL2 + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM2_CHANNEL2 + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM2_CHANNEL3 + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM2_CHANNEL3 + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM2_CHANNEL4 + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM2_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM2_CHANNEL int "TIM2 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM2_PWM ---help--- If TIM2 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM2_PWM + config STM32_TIM3_PWM bool "TIM3 PWM" default n @@ -2530,15 +2774,137 @@ config STM32_TIM3_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM3_PWM + +config STM32_TIM3_MODE + int "TIM3 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM3_CHANNEL1 + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM3_CHANNEL1 + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM3_CHANNEL2 + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM3_CHANNEL2 + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM3_CHANNEL3 + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM3_CHANNEL3 + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM3_CHANNEL4 + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM3_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM3_CHANNEL int "TIM3 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM3_PWM ---help--- If TIM3 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM3_PWM + config STM32_TIM4_PWM bool "TIM4 PWM" default n @@ -2552,15 +2918,137 @@ config STM32_TIM4_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM4_PWM + +config STM32_TIM4_MODE + int "TIM4 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM4_CHANNEL1 + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM4_CHANNEL1 + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM4_CHANNEL2 + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM4_CHANNEL2 + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM4_CHANNEL3 + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM4_CHANNEL3 + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM4_CHANNEL4 + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM4_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM4_CHANNEL int "TIM4 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM4_PWM ---help--- If TIM4 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM4_PWM + config STM32_TIM5_PWM bool "TIM5 PWM" default n @@ -2574,15 +3062,137 @@ config STM32_TIM5_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM5_PWM + +config STM32_TIM5_MODE + int "TIM5 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM5_CHANNEL1 + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM5_CHANNEL1 + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM5_CHANNEL2 + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM5_CHANNEL2 + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM5_CHANNEL3 + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM5_CHANNEL3 + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM5_CHANNEL4 + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM5_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM5_CHANNEL int "TIM5 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM5_PWM ---help--- If TIM5 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM5_PWM + config STM32_TIM8_PWM bool "TIM8 PWM" default n @@ -2596,15 +3206,137 @@ config STM32_TIM8_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM8_PWM + +config STM32_TIM8_MODE + int "TIM8 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM8_CHANNEL1 + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM8_CHANNEL1 + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM8_CHANNEL2 + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM8_CHANNEL2 + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM8_CHANNEL3 + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM8_CHANNEL3 + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM8_CHANNEL4 + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM8_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM8_CHANNEL int "TIM8 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM8_PWM ---help--- If TIM8 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM8_PWM + config STM32_TIM9_PWM bool "TIM9 PWM" default n @@ -2618,15 +3350,130 @@ config STM32_TIM9_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM9_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM9_CHANNEL1 + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM9_CHANNEL1 + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM9_CHANNEL2 + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM9_CHANNEL2 + +config STM32_TIM9_CHANNEL3 + bool "TIM9 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM9_CHANNEL3 + +config STM32_TIM9_CH3MODE + int "TIM9 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH3OUT + bool "TIM9 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM9_CHANNEL3 + +config STM32_TIM9_CHANNEL4 + bool "TIM9 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM9_CHANNEL4 + +config STM32_TIM9_CH4MODE + int "TIM9 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH4OUT + bool "TIM9 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM9_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM9_CHANNEL int "TIM9 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM9_PWM ---help--- If TIM9 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM9_PWM + config STM32_TIM10_PWM bool "TIM10 PWM" default n @@ -2640,15 +3487,130 @@ config STM32_TIM10_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM10_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM10_CHANNEL1 + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM10_CHANNEL1 + +config STM32_TIM10_CHANNEL2 + bool "TIM10 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM10_CHANNEL2 + +config STM32_TIM10_CH2MODE + int "TIM10 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH2OUT + bool "TIM10 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM10_CHANNEL2 + +config STM32_TIM10_CHANNEL3 + bool "TIM10 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM10_CHANNEL3 + +config STM32_TIM10_CH3MODE + int "TIM10 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH3OUT + bool "TIM10 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM10_CHANNEL3 + +config STM32_TIM10_CHANNEL4 + bool "TIM10 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM10_CHANNEL4 + +config STM32_TIM10_CH4MODE + int "TIM10 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH4OUT + bool "TIM10 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM10_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM10_CHANNEL int "TIM10 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM10_PWM ---help--- If TIM10 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM10_PWM + config STM32_TIM11_PWM bool "TIM11 PWM" default n @@ -2662,15 +3624,130 @@ config STM32_TIM11_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM11_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM11_CHANNEL1 + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM11_CHANNEL1 + +config STM32_TIM11_CHANNEL2 + bool "TIM11 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM11_CHANNEL2 + +config STM32_TIM11_CH2MODE + int "TIM11 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH2OUT + bool "TIM11 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM11_CHANNEL2 + +config STM32_TIM11_CHANNEL3 + bool "TIM11 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM11_CHANNEL3 + +config STM32_TIM11_CH3MODE + int "TIM11 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH3OUT + bool "TIM11 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM11_CHANNEL3 + +config STM32_TIM11_CHANNEL4 + bool "TIM11 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM11_CHANNEL4 + +config STM32_TIM11_CH4MODE + int "TIM11 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH4OUT + bool "TIM11 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM11_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM11_CHANNEL int "TIM11 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM11_PWM ---help--- If TIM11 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM11_PWM + config STM32_TIM12_PWM bool "TIM12 PWM" default n @@ -2684,15 +3761,130 @@ config STM32_TIM12_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM12_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM12_CHANNEL1 + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM12_CHANNEL1 + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM12_CHANNEL2 + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM12_CHANNEL2 + +config STM32_TIM12_CHANNEL3 + bool "TIM12 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM12_CHANNEL3 + +config STM32_TIM12_CH3MODE + int "TIM12 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH3OUT + bool "TIM12 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM12_CHANNEL3 + +config STM32_TIM12_CHANNEL4 + bool "TIM12 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM12_CHANNEL4 + +config STM32_TIM12_CH4MODE + int "TIM12 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH4OUT + bool "TIM12 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM12_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM12_CHANNEL int "TIM12 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM12_PWM ---help--- If TIM12 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM12_PWM + config STM32_TIM13_PWM bool "TIM13 PWM" default n @@ -2706,15 +3898,130 @@ config STM32_TIM13_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM13_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM13_CHANNEL1 + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM13_CHANNEL1 + +config STM32_TIM13_CHANNEL2 + bool "TIM13 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM13_CHANNEL2 + +config STM32_TIM13_CH2MODE + int "TIM13 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH2OUT + bool "TIM13 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM13_CHANNEL2 + +config STM32_TIM13_CHANNEL3 + bool "TIM13 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM13_CHANNEL3 + +config STM32_TIM13_CH3MODE + int "TIM13 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH3OUT + bool "TIM13 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM13_CHANNEL3 + +config STM32_TIM13_CHANNEL4 + bool "TIM13 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM13_CHANNEL4 + +config STM32_TIM13_CH4MODE + int "TIM13 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH4OUT + bool "TIM13 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM13_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM13_CHANNEL int "TIM13 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM13_PWM ---help--- If TIM13 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM13_PWM + config STM32_TIM14_PWM bool "TIM14 PWM" default n @@ -2728,15 +4035,130 @@ config STM32_TIM14_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM14_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM14_CHANNEL1 + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM14_CHANNEL1 + +config STM32_TIM14_CHANNEL2 + bool "TIM14 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM14_CHANNEL2 + +config STM32_TIM14_CH2MODE + int "TIM14 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH2OUT + bool "TIM14 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM14_CHANNEL2 + +config STM32_TIM14_CHANNEL3 + bool "TIM14 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM14_CHANNEL3 + +config STM32_TIM14_CH3MODE + int "TIM14 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH3OUT + bool "TIM14 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM14_CHANNEL3 + +config STM32_TIM14_CHANNEL4 + bool "TIM14 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM14_CHANNEL4 + +config STM32_TIM14_CH4MODE + int "TIM14 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH4OUT + bool "TIM14 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM14_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM14_CHANNEL int "TIM14 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM14_PWM ---help--- If TIM14 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM14_PWM + config STM32_TIM15_PWM bool "TIM15 PWM" default n @@ -2749,15 +4171,82 @@ config STM32_TIM15_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM15_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM15_CHANNEL1 + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + default 0 + range 0 3 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM15_CHANNEL1 + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM15_CHANNEL2 + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + default 0 + range 0 3 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM15_CHANNEL2 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM15_CHANNEL int "TIM15 PWM Output Channel" default 1 range 1 2 - depends on STM32_TIM15_PWM ---help--- If TIM15 is enabled for PWM usage, you also need specifies the timer output channel {1,2} +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + default 0 + range 0 3 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM15_PWM + config STM32_TIM16_PWM bool "TIM16 PWM" default n @@ -2770,15 +4259,56 @@ config STM32_TIM16_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM16_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM16_CHANNEL1 + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM16_CHANNEL1 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM16_CHANNEL int "TIM16 PWM Output Channel" default 1 range 1 1 - depends on STM32_TIM16_PWM ---help--- If TIM16 is enabled for PWM usage, you also need specifies the timer output channel {1} +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM16_PWM + config STM32_TIM17_PWM bool "TIM17 PWM" default n @@ -2791,15 +4321,65 @@ config STM32_TIM17_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM17_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM17_CHANNEL1 + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM17_CHANNEL1 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM17_CHANNEL int "TIM17 PWM Output Channel" default 1 range 1 1 - depends on STM32_TIM17_PWM ---help--- If TIM17 is enabled for PWM usage, you also need specifies the timer output channel {1} +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM17_PWM + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + default n + depends on STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM || STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM || STM32_TIM9_PWM || STM32_TIM10_PWM || STM32_TIM11_PWM || STM32_TIM12_PWM || STM32_TIM13_PWM || STM32_TIM14_PWM || STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + select ARCH_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + config STM32_TIM1_ADC bool "TIM1 ADC" default n diff --git a/arch/arm/src/stm32/chip/stm32_tim.h b/arch/arm/src/stm32/chip/stm32_tim.h index 80e86c00260..573dd9dd84b 100644 --- a/arch/arm/src/stm32/chip/stm32_tim.h +++ b/arch/arm/src/stm32/chip/stm32_tim.h @@ -677,8 +677,8 @@ #define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ #ifdef CONFIG_STM32_STM32F30XX -# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ +# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ #endif /* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ @@ -698,6 +698,10 @@ #define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ #define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ #define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ /* Capture/compare mode register 1 -- Input capture mode */ @@ -764,8 +768,8 @@ #define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ #ifdef CONFIG_STM32_STM32F30XX -# define ATIM_CCMR1_OC3M 1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -# define ATIM_CCMR1_OC4M 1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ +# define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +# define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ #endif /* Capture/compare mode register 2 - Input Capture Mode */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index a3a16456889..d8b98e0ee27 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_pwm.c * * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -65,7 +67,9 @@ defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \ defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \ - defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) + defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) /**************************************************************************** * Pre-processor Definitions @@ -75,7 +79,7 @@ #define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */ #define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */ -#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */ +#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4, TIM15-17 on F3 */ #define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */ #define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */ @@ -105,6 +109,9 @@ #define TIMTYPE_TIM12 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM13 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16 /* Debug ********************************************************************/ /* Non-standard debug that may be enabled just for testing PWM */ @@ -136,14 +143,42 @@ /**************************************************************************** * Private Types ****************************************************************************/ + +enum stm32_timmode_e +{ + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, +}; + +enum stm32_chanmode_e +{ + STM32_CHANMODE_PWM1 = 0, + STM32_CHANMODE_PWM2 = 1, + STM32_CHANMODE_COMBINED1 = 2, + STM32_CHANMODE_COMBINED2 = 3, + STM32_CHANMODE_ASYMMETRIC1 = 4, + STM32_CHANMODE_ASYMMETRIC2 = 5, +}; + +struct stm32_pwmchan_s +{ + uint8_t channel; /* Timer output channel: {1,..4} */ + uint32_t pincfg; /* Output pin configuration */ + enum stm32_chanmode_e mode; +}; + /* This structure represents the state of one PWM timer */ struct stm32_pwmtimer_s { FAR const struct pwm_ops_s *ops; /* PWM operations */ - uint8_t timid; /* Timer ID {1,...,14} */ - uint8_t channel; /* Timer output channel: {1,..4} */ + uint8_t timid; /* Timer ID {1,...,17} */ + struct stm32_pwmchan_s channels[PWM_NCHANNELS]; uint8_t timtype; /* See the TIMTYPE_* definitions */ + enum stm32_timmode_e mode; #ifdef CONFIG_PWM_PULSECOUNT uint8_t irq; /* Timer update IRQ */ uint8_t prev; /* The previous value of the RCR (pre-loaded) */ @@ -151,11 +186,10 @@ struct stm32_pwmtimer_s uint32_t count; /* Remaining pluse count */ #endif uint32_t base; /* The base address of the timer */ - uint32_t pincfg; /* Output pin configuration */ uint32_t pclk; /* The frequency of the peripheral clock * that drives the timer module. */ #ifdef CONFIG_PWM_PULSECOUNT - FAR void * handle; /* Handle used for upper-half callback */ + FAR void *handle; /* Handle used for upper-half callback */ #endif }; @@ -214,185 +248,515 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, static const struct pwm_ops_s g_pwmops = { - .setup = pwm_setup, - .shutdown = pwm_shutdown, - .start = pwm_start, - .stop = pwm_stop, - .ioctl = pwm_ioctl, + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, }; #ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmtimer_s g_pwm1dev = { - .ops = &g_pwmops, - .timid = 1, - .channel = CONFIG_STM32_TIM1_CHANNEL, - .timtype = TIMTYPE_TIM1, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM1UP, + .ops = &g_pwmops, + .timid = 1, + .channels = + { +#ifdef CONFIG_STM32_TIM1_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM1_CH1CFG, + .mode = CONFIG_STM32_TIM1_CH1MODE, + }, #endif - .base = STM32_TIM1_BASE, - .pincfg = PWM_TIM1_PINCFG, - .pclk = STM32_APB2_TIM1_CLKIN, +#ifdef CONFIG_STM32_TIM1_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM1_CH2CFG, + .mode = CONFIG_STM32_TIM1_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM1_CH3CFG, + .mode = CONFIG_STM32_TIM1_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM1_CH4CFG, + .mode = CONFIG_STM32_TIM1_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM1, + .mode = CONFIG_STM32_TIM1_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM1UP, +#endif + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmtimer_s g_pwm2dev = { - .ops = &g_pwmops, - .timid = 2, - .channel = CONFIG_STM32_TIM2_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM2, + .ops = &g_pwmops, + .timid = 2, + .channels = + { +#ifdef CONFIG_STM32_TIM2_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM2_CH1CFG, + .mode = CONFIG_STM32_TIM2_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM2, - .base = STM32_TIM2_BASE, - .pincfg = PWM_TIM2_PINCFG, - .pclk = STM32_APB1_TIM2_CLKIN, +#ifdef CONFIG_STM32_TIM2_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM2_CH2CFG, + .mode = CONFIG_STM32_TIM2_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM2_CH3CFG, + .mode = CONFIG_STM32_TIM2_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM2_CH4CFG, + .mode = CONFIG_STM32_TIM2_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM2, + .mode = CONFIG_STM32_TIM2_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM2, +#endif + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmtimer_s g_pwm3dev = { - .ops = &g_pwmops, - .timid = 3, - .channel = CONFIG_STM32_TIM3_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM3, + .ops = &g_pwmops, + .timid = 3, + .channels = + { +#ifdef CONFIG_STM32_TIM3_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM3_CH1CFG, + .mode = CONFIG_STM32_TIM3_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM3, - .base = STM32_TIM3_BASE, - .pincfg = PWM_TIM3_PINCFG, - .pclk = STM32_APB1_TIM3_CLKIN, +#ifdef CONFIG_STM32_TIM3_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM3_CH2CFG, + .mode = CONFIG_STM32_TIM3_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM3_CH3CFG, + .mode = CONFIG_STM32_TIM3_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM3_CH4CFG, + .mode = CONFIG_STM32_TIM3_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM3, + .mode = CONFIG_STM32_TIM3_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM3, +#endif + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmtimer_s g_pwm4dev = { - .ops = &g_pwmops, - .timid = 4, - .channel = CONFIG_STM32_TIM4_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM4, + .ops = &g_pwmops, + .timid = 4, + .channels = + { +#ifdef CONFIG_STM32_TIM4_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM4_CH1CFG, + .mode = CONFIG_STM32_TIM4_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM4, - .base = STM32_TIM4_BASE, - .pincfg = PWM_TIM4_PINCFG, - .pclk = STM32_APB1_TIM4_CLKIN, +#ifdef CONFIG_STM32_TIM4_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM4_CH2CFG, + .mode = CONFIG_STM32_TIM4_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM4_CH3CFG, + .mode = CONFIG_STM32_TIM4_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM4_CH4CFG, + .mode = CONFIG_STM32_TIM4_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM4, + .mode = CONFIG_STM32_TIM4_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM4, +#endif + .base = STM32_TIM4_BASE, + .pclk = STM32_APB1_TIM4_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmtimer_s g_pwm5dev = { - .ops = &g_pwmops, - .timid = 5, - .channel = CONFIG_STM32_TIM5_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM5, + .ops = &g_pwmops, + .timid = 5, + .channels = + { +#ifdef CONFIG_STM32_TIM5_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM5_CH1CFG, + .mode = CONFIG_STM32_TIM5_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM5, - .base = STM32_TIM5_BASE, - .pincfg = PWM_TIM5_PINCFG, - .pclk = STM32_APB1_TIM5_CLKIN, +#ifdef CONFIG_STM32_TIM5_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM5_CH2CFG, + .mode = CONFIG_STM32_TIM5_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM5_CH3CFG, + .mode = CONFIG_STM32_TIM5_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM5_CH4CFG, + .mode = CONFIG_STM32_TIM5_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM5, + .mode = CONFIG_STM32_TIM5_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM5, +#endif + .base = STM32_TIM5_BASE, + .pclk = STM32_APB1_TIM5_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmtimer_s g_pwm8dev = { - .ops = &g_pwmops, - .timid = 8, - .channel = CONFIG_STM32_TIM8_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM8UP, + .ops = &g_pwmops, + .timid = 8, + .channels = + { +#ifdef CONFIG_STM32_TIM8_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM8_CH1CFG, + .mode = CONFIG_STM32_TIM8_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM8, - .base = STM32_TIM8_BASE, - .pincfg = PWM_TIM8_PINCFG, - .pclk = STM32_APB2_TIM8_CLKIN, +#ifdef CONFIG_STM32_TIM8_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM8_CH2CFG, + .mode = CONFIG_STM32_TIM8_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM8_CH3CFG, + .mode = CONFIG_STM32_TIM8_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM8_CH4CFG, + .mode = CONFIG_STM32_TIM8_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM8, + .mode = CONFIG_STM32_TIM8_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM8UP, +#endif + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM9_PWM static struct stm32_pwmtimer_s g_pwm9dev = { - .ops = &g_pwmops, - .timid = 9, - .channel = CONFIG_STM32_TIM9_CHANNEL, - .timtype = TIMTYPE_TIM9, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM9, + .ops = &g_pwmops, + .timid = 9, + .channels = + { +#ifdef CONFIG_STM32_TIM9_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM9_CH1CFG, + .mode = CONFIG_STM32_TIM9_CH1MODE, + }, #endif - .base = STM32_TIM9_BASE, - .pincfg = PWM_TIM9_PINCFG, - .pclk = STM32_APB2_TIM9_CLKIN, +#ifdef CONFIG_STM32_TIM9_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM9_CH2CFG, + .mode = CONFIG_STM32_TIM9_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM9_CH3CFG, + .mode = CONFIG_STM32_TIM9_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM9_CH4CFG, + .mode = CONFIG_STM32_TIM9_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM9, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM9, +#endif + .base = STM32_TIM9_BASE, + .pclk = STM32_APB2_TIM9_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM10_PWM static struct stm32_pwmtimer_s g_pwm10dev = { - .ops = &g_pwmops, - .timid = 10, - .channel = CONFIG_STM32_TIM10_CHANNEL, - .timtype = TIMTYPE_TIM10, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM10, + .ops = &g_pwmops, + .timid = 10, + .channels = + { +#ifdef CONFIG_STM32_TIM10_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM10_CH1CFG, + .mode = CONFIG_STM32_TIM10_CH1MODE, + }, #endif - .base = STM32_TIM10_BASE, - .pincfg = PWM_TIM10_PINCFG, - .pclk = STM32_APB2_TIM10_CLKIN, +#ifdef CONFIG_STM32_TIM10_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM10_CH2CFG, + .mode = CONFIG_STM32_TIM10_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM10_CH3CFG, + .mode = CONFIG_STM32_TIM10_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM10_CH4CFG, + .mode = CONFIG_STM32_TIM10_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM10, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM10, +#endif + .base = STM32_TIM10_BASE, + .pclk = STM32_APB2_TIM10_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM11_PWM static struct stm32_pwmtimer_s g_pwm11dev = { - .ops = &g_pwmops, - .timid = 11, - .channel = CONFIG_STM32_TIM11_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM11, + .ops = &g_pwmops, + .timid = 11, + .channels = + { +#ifdef CONFIG_STM32_TIM11_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM11_CH1CFG, + .mode = CONFIG_STM32_TIM11_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM11, - .base = STM32_TIM11_BASE, - .pincfg = PWM_TIM11_PINCFG, - .pclk = STM32_APB2_TIM11_CLKIN, +#ifdef CONFIG_STM32_TIM11_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM11_CH2CFG, + .mode = CONFIG_STM32_TIM11_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM11_CH3CFG, + .mode = CONFIG_STM32_TIM11_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM11_CH4CFG, + .mode = CONFIG_STM32_TIM11_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM11, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM11, +#endif + .base = STM32_TIM11_BASE, + .pclk = STM32_APB2_TIM11_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmtimer_s g_pwm12dev = { - .ops = &g_pwmops, - .timid = 12, - .channel = CONFIG_STM32_TIM12_CHANNEL, - .timtype = TIMTYPE_TIM12, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM12, + .ops = &g_pwmops, + .timid = 12, + .channels = + { +#ifdef CONFIG_STM32_TIM12_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM12_CH1CFG, + .mode = CONFIG_STM32_TIM12_CH1MODE, + }, #endif - .base = STM32_TIM12_BASE, - .pincfg = PWM_TIM12_PINCFG, - .pclk = STM32_APB1_TIM12_CLKIN, +#ifdef CONFIG_STM32_TIM12_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM12_CH2CFG, + .mode = CONFIG_STM32_TIM12_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM12_CH3CFG, + .mode = CONFIG_STM32_TIM12_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM12_CH4CFG, + .mode = CONFIG_STM32_TIM12_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM12, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM12, +#endif + .base = STM32_TIM12_BASE, + .pclk = STM32_APB1_TIM12_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmtimer_s g_pwm13dev = { - .ops = &g_pwmops, - .timid = 13, - .channel = CONFIG_STM32_TIM13_CHANNEL, - .timtype = TIMTYPE_TIM13, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM13, + .ops = &g_pwmops, + .timid = 13, + .channels = + { +#ifdef CONFIG_STM32_TIM13_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM13_CH1CFG, + .mode = CONFIG_STM32_TIM13_CH1MODE, + }, #endif - .base = STM32_TIM13_BASE, - .pincfg = PWM_TIM13_PINCFG, +#ifdef CONFIG_STM32_TIM13_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM13_CH2CFG, + .mode = CONFIG_STM32_TIM13_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM13_CH3CFG, + .mode = CONFIG_STM32_TIM13_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM13_CH4CFG, + .mode = CONFIG_STM32_TIM13_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM13, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM13, +#endif + .base = STM32_TIM13_BASE, .pclk = STM32_APB1_TIM13_CLKIN, }; #endif @@ -400,16 +764,128 @@ static struct stm32_pwmtimer_s g_pwm13dev = #ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmtimer_s g_pwm14dev = { - .ops = &g_pwmops, - .timid = 14, - .channel = CONFIG_STM32_TIM14_CHANNEL, - .timtype = TIMTYPE_TIM14, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM14, + .ops = &g_pwmops, + .timid = 14, + .channels = + { +#ifdef CONFIG_STM32_TIM14_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM14_CH1CFG, + .mode = CONFIG_STM32_TIM14_CH1MODE, + }, #endif - .base = STM32_TIM14_BASE, - .pincfg = PWM_TIM14_PINCFG, - .pclk = STM32_APB1_TIM14_CLKIN, +#ifdef CONFIG_STM32_TIM14_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM14_CH2CFG, + .mode = CONFIG_STM32_TIM14_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM14_CH3CFG, + .mode = CONFIG_STM32_TIM14_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM14_CH4CFG, + .mode = CONFIG_STM32_TIM14_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM14, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM14, +#endif + .base = STM32_TIM14_BASE, + .pclk = STM32_APB1_TIM14_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM15_PWM +static struct stm32_pwmtimer_s g_pwm15dev = +{ + .ops = &g_pwmops, + .timid = 15, + .channels = + { +#ifdef CONFIG_STM32_TIM15_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM15_CH1CFG, + .mode = CONFIG_STM32_TIM15_CH1MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM15_CH2CFG, + .mode = CONFIG_STM32_TIM15_CH2MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM15, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM15, +#endif + .base = STM32_TIM15_BASE, + .pclk = STM32_APB1_TIM15_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +static struct stm32_pwmtimer_s g_pwm16dev = +{ + .ops = &g_pwmops, + .timid = 16, + .channels = + { +#ifdef CONFIG_STM32_TIM16_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM16_CH1CFG, + .mode = CONFIG_STM32_TIM16_CH1MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM16, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM16, +#endif + .base = STM32_TIM16_BASE, + .pclk = STM32_APB1_TIM16_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +static struct stm32_pwmtimer_s g_pwm17dev = +{ + .ops = &g_pwmops, + .timid = 17, + .channels = + { +#ifdef CONFIG_STM32_TIM17_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM17_CH1CFG, + .mode = CONFIG_STM32_TIM17_CH1MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM17, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM17, +#endif + .base = STM32_TIM17_BASE, + .pclk = STM32_APB1_TIM17_CLKIN, }; #endif @@ -551,6 +1027,10 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, FAR const struct pwm_info_s *info) { +#ifdef CONFIG_PWM_MULTICHAN + int i; +#endif + /* Calculated values */ uint32_t prescaler; @@ -563,18 +1043,31 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, uint16_t cr1; uint16_t ccer; uint16_t cr2; +#ifdef CONFIG_STM32_STM32F30XX + uint32_t ccmr1; + uint32_t ccmr2; +#else uint16_t ccmr1; uint16_t ccmr2; +#endif /* New timer regiser bit settings */ uint16_t ccenable; +#ifdef CONFIG_STM32_STM32F30XX + uint32_t ocmode1; + uint32_t ocmode2; +#else uint16_t ocmode1; uint16_t ocmode2; +#endif DEBUGASSERT(priv != NULL && info != NULL); -#ifdef CONFIG_PWM_PULSECOUNT +#if defined(CONFIG_PWM_MULTICHAN) + pwmvdbg("TIM%d frequency: %d\n", + priv->timid, info->frequency); +#elif defined(CONFIG_PWM_PULSECOUNT) pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x count: %d\n", priv->timid, priv->channel, info->frequency, info->duty, info->count); @@ -582,8 +1075,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x\n", priv->timid, priv->channel, info->frequency, info->duty); #endif - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && - info->duty < uitoub16(100)); + DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_PWM_MULTICHAN + DEBUGASSERT(info->duty > 0 && info->duty < uitoub16(100)); +#endif /* Disable all interrupts and DMA requests, clear all pending status */ @@ -647,22 +1142,16 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, reload = 65535; } - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(info->duty * reload + b16HALF); - - pwmvdbg("TIM%d PCLK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d ccr: %d\n", - priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload, ccr); + pwmvdbg("TIM%d PCLK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d\n", + priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload); /* Set up the timer CR1 register: * - * 1-8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN - * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN - * 6-7 ARPE OPM URS UDIS CEN - * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN + * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN + * 6-7 ARPE OPM URS UDIS CEN + * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN */ cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); @@ -672,25 +1161,53 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, cr1 &= ~GTIM_CR1_CEN; /* Set the counter mode for the advanced timers (1,8) and most general - * purpose timers (all 2-5, but not 9-14), i.e., all but TIMTYPE_COUNTUP16 + * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 * and TIMTYPE_BASIC */ -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ - defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16) { - /* Select the Counter Mode == count up: + /* Select the Counter Mode: * * GTIM_CR1_EDGE: The counter counts up or down depending on the - * direction bit(DIR). + * direction bit (DIR). + * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter + * counts up then down. * GTIM_CR1_DIR: 0: count up, 1: count down */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; + + switch (priv->mode) + { + case STM32_TIMMODE_COUNTUP: + cr1 |= GTIM_CR1_EDGE; + break; + + case STM32_TIMMODE_COUNTDOWN: + cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; + break; + + case STM32_TIMMODE_CENTER1: + cr1 |= GTIM_CR1_CENTER1; + break; + + case STM32_TIMMODE_CENTER2: + cr1 |= GTIM_CR1_CENTER2; + break; + + case STM32_TIMMODE_CENTER3: + cr1 |= GTIM_CR1_CENTER3; + break; + + default: + pwmdbg("No such timer mode: %d\n", (int)priv->mode); + return -EINVAL; + } } #endif @@ -706,7 +1223,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - /* Set the advanced timer's repitition counter */ + /* Set the advanced timer's repetition counter */ #if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) @@ -719,12 +1236,12 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, #ifdef CONFIG_PWM_PULSECOUNT if (info->count > 0) { - /* Save the remining count and the number of counts that will have + /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. */ /* If the first interrupt occurs at the end end of the first - * repition count, then the count will be the same as the RCR + * repetition count, then the count will be the same as the RCR * value. */ @@ -746,12 +1263,12 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } - /* Otherwise, just clear the repitition counter */ + /* Otherwise, just clear the repetition counter */ else #endif { - /* Set the repeition counter to zero */ + /* Set the repetition counter to zero */ pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); @@ -770,85 +1287,203 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Handle channel specific setup */ - ocmode1 = 0; - ocmode2 = 0; - switch (priv->channel) + ccenable = 0; + ocmode1 = 0; + ocmode2 = 0; + +#ifdef CONFIG_PWM_MULTICHAN + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) +#endif { - case 1: /* PWM Mode configuration: Channel 1 */ + ub16_t duty; +#ifdef CONFIG_STM32_STM32F30XX + uint32_t chanmode; + bool ocmbit = false; +#else + uint16_t chanmode; +#endif + uint8_t channel; +#ifdef CONFIG_PWM_MULTICHAN + int j; +#endif + enum stm32_chanmode_e mode; + +#ifdef CONFIG_PWM_MULTICHAN + duty = info->channels[i].duty; + channel = info->channels[i].channel; + + for (j = 0; j < PWM_NCHANNELS; j++) { - /* Select the CCER enable bit for this channel */ - - ccenable = ATIM_CCER_CC1E; - - /* Set the CCMR1 mode values (leave CCMR2 zero) */ - - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | - ATIM_CCMR1_OC1PE; - - /* Set the duty cycle by writing to the CCR register for this channel */ - - pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)ccr); + if (priv->channels[j].channel == channel) + { + mode = priv->channels[j].mode; + break; + } } - break; - case 2: /* PWM Mode configuration: Channel 2 */ + if (j >= PWM_NCHANNELS) { - /* Select the CCER enable bit for this channel */ - - ccenable = ATIM_CCER_CC2E; - - /* Set the CCMR1 mode values (leave CCMR2 zero) */ - - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | - ATIM_CCMR1_OC2PE; - - /* Set the duty cycle by writing to the CCR register for this channel */ - - pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)ccr); + pwmdbg("No such channel: %d\n", channel); + return -EINVAL; } - break; +#else + duty = info->duty; + channel = priv->channels[0].channel; + mode = priv->channels[0].mode; +#endif - case 3: /* PWM Mode configuration: Channel3 */ + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + pwmvdbg("ccr: %d\n", ccr); + + switch (mode) { - /* Select the CCER enable bit for this channel */ + case STM32_CHANMODE_PWM1: + chanmode = ATIM_CCMR_MODE_PWM1; + break; - ccenable = ATIM_CCER_CC3E; + case STM32_CHANMODE_PWM2: + chanmode = ATIM_CCMR_MODE_PWM2; + break; - /* Set the CCMR2 mode values (leave CCMR1 zero) */ +#ifdef CONFIG_STM32_STM32F30XX + case STM32_CHANMODE_COMBINED1: + chanmode = ATIM_CCMR_MODE_COMBINED1; + ocmbit = true; + break; - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; + case STM32_CHANMODE_COMBINED2: + chanmode = ATIM_CCMR_MODE_COMBINED2; + ocmbit = true; + break; - /* Set the duty cycle by writing to the CCR register for this channel */ + case STM32_CHANMODE_ASYMMETRIC1: + chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; + ocmbit = true; + break; - pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)ccr); + case STM32_CHANMODE_ASYMMETRIC2: + chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; + ocmbit = true; + break; +#endif + + default: + pwmdbg("No such mode: %d\n", (int)mode); + return -EINVAL; } - break; - case 4: /* PWM1 Mode configuration: Channel4 */ + switch (channel) { - /* Select the CCER enable bit for this channel */ + case 1: /* PWM Mode configuration: Channel 1 */ + { + /* Select the CCER enable bit for this channel */ - ccenable = ATIM_CCER_CC4E; + ccenable |= ATIM_CCER_CC1E; - /* Set the CCMR2 mode values (leave CCMR1 zero) */ + /* Set the CCMR1 mode values (leave CCMR2 zero) */ - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; + ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | + (chanmode << ATIM_CCMR1_OC1M_SHIFT) | + ATIM_CCMR1_OC1PE; - /* Set the duty cycle by writing to the CCR register for this channel */ +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode1 |= ATIM_CCMR1_OC1M; + } +#endif - pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)ccr); + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)ccr); + } + break; + + case 2: /* PWM Mode configuration: Channel 2 */ + { + /* Select the CCER enable bit for this channel */ + + ccenable |= ATIM_CCER_CC2E; + + /* Set the CCMR1 mode values (leave CCMR2 zero) */ + + ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | + (chanmode << ATIM_CCMR1_OC2M_SHIFT) | + ATIM_CCMR1_OC2PE; + +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode1 |= ATIM_CCMR1_OC2M; + } +#endif + + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)ccr); + } + break; + + case 3: /* PWM Mode configuration: Channel 3 */ + { + /* Select the CCER enable bit for this channel */ + + ccenable |= ATIM_CCER_CC3E; + + /* Set the CCMR2 mode values (leave CCMR1 zero) */ + + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | + (chanmode << ATIM_CCMR2_OC3M_SHIFT) | + ATIM_CCMR2_OC3PE; + +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode2 |= ATIM_CCMR2_OC3M; + } +#endif + + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)ccr); + } + break; + + case 4: /* PWM Mode configuration: Channel 4 */ + { + /* Select the CCER enable bit for this channel */ + + ccenable |= ATIM_CCER_CC4E; + + /* Set the CCMR2 mode values (leave CCMR1 zero) */ + + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | + (chanmode << ATIM_CCMR2_OC4M_SHIFT) | + ATIM_CCMR2_OC4PE; + +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode2 |= ATIM_CCMR2_OC4M; + } +#endif + + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)ccr); + } + break; + + default: + pwmdbg("No such channel: %d\n", channel); + return -EINVAL; } - break; - - default: - pwmdbg("No such channel: %d\n", priv->channel); - return -EINVAL; } /* Disable the Channel by resetting the CCxE Bit in the CCER register */ @@ -866,9 +1501,17 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Reset the Output Compare Mode Bits and set the select output compare mode */ ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | - ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); + ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE +#ifdef CONFIG_STM32_STM32F30XX + | ATIM_CCMR1_OC1M | ATIM_CCMR1_OC2M +#endif + ); ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | - ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); + ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE +#ifdef CONFIG_STM32_STM32F30XX + | ATIM_CCMR2_OC3M | ATIM_CCMR2_OC4M +#endif + ); ccmr1 |= ocmode1; ccmr2 |= ocmode2; @@ -876,7 +1519,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P); - /* Enable the output state of the selected channel (only) */ + /* Enable the output state of the selected channels */ ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; @@ -892,7 +1535,8 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, * output compare N idle state. */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); #else @@ -914,11 +1558,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, bdtr |= ATIM_BDTR_MOE; pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); } -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) else #endif #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) { ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); } @@ -927,8 +1573,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Save the modified register values */ pwm_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); +#ifdef CONFIG_STM32_STM32F30XX + putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); + putreg32(ccmr2, priv->base + STM32_GTIM_CCMR2_OFFSET); +#else pwm_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); pwm_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); +#endif pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the ARR Preload Bit */ @@ -939,7 +1590,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Setup update interrupt. If info->count is > 0, then we can be * assured that pwm_start() has already verified: (1) that this is an - * advanced timer, and that (2) the repetitioncount is within range. + * advanced timer, and that (2) the repetition count is within range. */ #ifdef CONFIG_PWM_PULSECOUNT @@ -1222,6 +1873,24 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) regaddr = STM32_RCC_APB1ENR; en_bit = RCC_APB1ENR_TIM14EN; break; +#endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM15EN; + break; +#endif +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM16EN; + break; +#endif +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM17EN; + break; #endif } @@ -1260,18 +1929,32 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t pincfg; + int i; - pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + pwmvdbg("TIM%d\n", priv->timid); pwm_dumpregs(priv, "Initially"); /* Enable APB1/2 clocking for timer. */ pwm_set_apb_clock(priv, true); - /* Configure the PWM output pin, but do not start the timer yet */ + /* Configure the PWM output pins, but do not start the timer yet */ + + for (i = 0; i < PWM_NCHANNELS; i++) + { + pincfg = priv->channels[i].pincfg; + if (pincfg == 0) + { + continue; + } + + pwmvdbg("pincfg: %08x\n", pincfg); + + stm32_configgpio(pincfg); + pwm_dumpgpio(pincfg, "PWM setup"); + } - stm32_configgpio(priv->pincfg); - pwm_dumpgpio(priv->pincfg, "PWM setup"); return OK; } @@ -1295,8 +1978,9 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; uint32_t pincfg; + int i; - pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + pwmvdbg("TIM%d\n", priv->timid); /* Make sure that the output has been stopped */ @@ -1306,20 +1990,34 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pwm_set_apb_clock(priv, false); - /* Then put the GPIO pin back to the default state */ + /* Then put the GPIO pins back to the default state */ - pincfg = priv->pincfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + for (i = 0; i < PWM_NCHANNELS; i++) + { + pincfg = priv->channels[i].pincfg; + if (pincfg == 0) + { + continue; + } + + pwmvdbg("pincfg: %08x\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); #if defined(CONFIG_STM32_STM32F10XX) - pincfg |= (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT); -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) - pincfg |= (GPIO_INPUT | GPIO_FLOAT); + pincfg |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) + pincfg |= GPIO_INPUT | GPIO_FLOAT; #else # error "Unrecognized STM32 chip" #endif - stm32_configgpio(pincfg); + stm32_configgpio(pincfg); + } + return OK; } @@ -1491,6 +2189,24 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM14RST; break; +#endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM15RST; + break; +#endif +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM16RST; + break; +#endif +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM17RST; + break; #endif } @@ -1552,7 +2268,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg * Input Parameters: * timer - A number identifying the timer use. The number of valid timer * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,14}. + * the range of {1,..,17}. * * Returned Value: * On success, a pointer to the STM32 lower half PWM driver is returned. @@ -1654,6 +2370,24 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + lower = &g_pwm15dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + lower = &g_pwm16dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + lower = &g_pwm17dev; + break; +#endif + default: pwmdbg("No such timer configured\n"); return NULL; @@ -1662,4 +2396,4 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (FAR struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,14 */ +#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,17 */ diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h index 96764de9bc0..e636ead3a37 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/stm32/stm32_pwm.h @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_pwm.h * * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -96,6 +98,15 @@ #ifndef CONFIG_STM32_TIM14 # undef CONFIG_STM32_TIM14_PWM #endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM +#endif +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM +#endif +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM +#endif /* The basic timers (timer 6 and 7) are not capable of generating output pulses */ @@ -109,11 +120,597 @@ defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \ defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \ - defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) + defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) #include #include "chip/stm32_tim.h" +#ifdef CONFIG_PWM_MULTICHAN + +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# else +# define PWM_TIM1_CH1CFG 0 +# endif +# define PWM_TIM1_CHANNEL1 1 +#else +# define PWM_TIM1_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# else +# define PWM_TIM1_CH2CFG 0 +# endif +# define PWM_TIM1_CHANNEL2 1 +#else +# define PWM_TIM1_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# else +# define PWM_TIM1_CH3CFG 0 +# endif +# define PWM_TIM1_CHANNEL3 1 +#else +# define PWM_TIM1_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +# else +# define PWM_TIM1_CH4CFG 0 +# endif +# define PWM_TIM1_CHANNEL4 1 +#else +# define PWM_TIM1_CHANNEL4 0 +#endif +#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ + PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) + +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# else +# define PWM_TIM2_CH1CFG 0 +# endif +# define PWM_TIM2_CHANNEL1 1 +#else +# define PWM_TIM2_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# else +# define PWM_TIM2_CH2CFG 0 +# endif +# define PWM_TIM2_CHANNEL2 1 +#else +# define PWM_TIM2_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# else +# define PWM_TIM2_CH3CFG 0 +# endif +# define PWM_TIM2_CHANNEL3 1 +#else +# define PWM_TIM2_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +# else +# define PWM_TIM2_CH4CFG 0 +# endif +# define PWM_TIM2_CHANNEL4 1 +#else +# define PWM_TIM2_CHANNEL4 0 +#endif +#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ + PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) + +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# else +# define PWM_TIM3_CH1CFG 0 +# endif +# define PWM_TIM3_CHANNEL1 1 +#else +# define PWM_TIM3_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# else +# define PWM_TIM3_CH2CFG 0 +# endif +# define PWM_TIM3_CHANNEL2 1 +#else +# define PWM_TIM3_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# else +# define PWM_TIM3_CH3CFG 0 +# endif +# define PWM_TIM3_CHANNEL3 1 +#else +# define PWM_TIM3_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +# else +# define PWM_TIM3_CH4CFG 0 +# endif +# define PWM_TIM3_CHANNEL4 1 +#else +# define PWM_TIM3_CHANNEL4 0 +#endif +#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ + PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) + +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# ifdef CONFIG_STM32_TIM4_CH1OUT +# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT +# else +# define PWM_TIM4_CH1CFG 0 +# endif +# define PWM_TIM4_CHANNEL1 1 +#else +# define PWM_TIM4_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# ifdef CONFIG_STM32_TIM4_CH2OUT +# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT +# else +# define PWM_TIM4_CH2CFG 0 +# endif +# define PWM_TIM4_CHANNEL2 1 +#else +# define PWM_TIM4_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# ifdef CONFIG_STM32_TIM4_CH3OUT +# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT +# else +# define PWM_TIM4_CH3CFG 0 +# endif +# define PWM_TIM4_CHANNEL3 1 +#else +# define PWM_TIM4_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# ifdef CONFIG_STM32_TIM4_CH4OUT +# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT +# else +# define PWM_TIM4_CH4CFG 0 +# endif +# define PWM_TIM4_CHANNEL4 1 +#else +# define PWM_TIM4_CHANNEL4 0 +#endif +#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ + PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) + +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# ifdef CONFIG_STM32_TIM5_CH1OUT +# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT +# else +# define PWM_TIM5_CH1CFG 0 +# endif +# define PWM_TIM5_CHANNEL1 1 +#else +# define PWM_TIM5_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# ifdef CONFIG_STM32_TIM5_CH2OUT +# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT +# else +# define PWM_TIM5_CH2CFG 0 +# endif +# define PWM_TIM5_CHANNEL2 1 +#else +# define PWM_TIM5_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# ifdef CONFIG_STM32_TIM5_CH3OUT +# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT +# else +# define PWM_TIM5_CH3CFG 0 +# endif +# define PWM_TIM5_CHANNEL3 1 +#else +# define PWM_TIM5_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# ifdef CONFIG_STM32_TIM5_CH4OUT +# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT +# else +# define PWM_TIM5_CH4CFG 0 +# endif +# define PWM_TIM5_CHANNEL4 1 +#else +# define PWM_TIM5_CHANNEL4 0 +#endif +#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ + PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) + +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# ifdef CONFIG_STM32_TIM8_CH1OUT +# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT +# else +# define PWM_TIM8_CH1CFG 0 +# endif +# define PWM_TIM8_CHANNEL1 1 +#else +# define PWM_TIM8_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# ifdef CONFIG_STM32_TIM8_CH2OUT +# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT +# else +# define PWM_TIM8_CH2CFG 0 +# endif +# define PWM_TIM8_CHANNEL2 1 +#else +# define PWM_TIM8_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# ifdef CONFIG_STM32_TIM8_CH3OUT +# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT +# else +# define PWM_TIM8_CH3CFG 0 +# endif +# define PWM_TIM8_CHANNEL3 1 +#else +# define PWM_TIM8_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# ifdef CONFIG_STM32_TIM8_CH4OUT +# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT +# else +# define PWM_TIM8_CH4CFG 0 +# endif +# define PWM_TIM8_CHANNEL4 1 +#else +# define PWM_TIM8_CHANNEL4 0 +#endif +#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ + PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4) + +#ifdef CONFIG_STM32_TIM9_CHANNEL1 +# ifdef CONFIG_STM32_TIM9_CH1OUT +# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT +# else +# define PWM_TIM9_CH1CFG 0 +# endif +# define PWM_TIM9_CHANNEL1 1 +#else +# define PWM_TIM9_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL2 +# ifdef CONFIG_STM32_TIM9_CH2OUT +# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT +# else +# define PWM_TIM9_CH2CFG 0 +# endif +# define PWM_TIM9_CHANNEL2 1 +#else +# define PWM_TIM9_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL3 +# ifdef CONFIG_STM32_TIM9_CH3OUT +# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT +# else +# define PWM_TIM9_CH3CFG 0 +# endif +# define PWM_TIM9_CHANNEL3 1 +#else +# define PWM_TIM9_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL4 +# ifdef CONFIG_STM32_TIM9_CH4OUT +# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT +# else +# define PWM_TIM9_CH4CFG 0 +# endif +# define PWM_TIM9_CHANNEL4 1 +#else +# define PWM_TIM9_CHANNEL4 0 +#endif +#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2 + \ + PWM_TIM9_CHANNEL3 + PWM_TIM9_CHANNEL4) + +#ifdef CONFIG_STM32_TIM10_CHANNEL1 +# ifdef CONFIG_STM32_TIM10_CH1OUT +# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT +# else +# define PWM_TIM10_CH1CFG 0 +# endif +# define PWM_TIM10_CHANNEL1 1 +#else +# define PWM_TIM10_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL2 +# ifdef CONFIG_STM32_TIM10_CH2OUT +# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT +# else +# define PWM_TIM10_CH2CFG 0 +# endif +# define PWM_TIM10_CHANNEL2 1 +#else +# define PWM_TIM10_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL3 +# ifdef CONFIG_STM32_TIM10_CH3OUT +# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT +# else +# define PWM_TIM10_CH3CFG 0 +# endif +# define PWM_TIM10_CHANNEL3 1 +#else +# define PWM_TIM10_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL4 +# ifdef CONFIG_STM32_TIM10_CH4OUT +# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT +# else +# define PWM_TIM10_CH4CFG 0 +# endif +# define PWM_TIM10_CHANNEL4 1 +#else +# define PWM_TIM10_CHANNEL4 0 +#endif +#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1 + PWM_TIM10_CHANNEL2 + \ + PWM_TIM10_CHANNEL3 + PWM_TIM10_CHANNEL4) + +#ifdef CONFIG_STM32_TIM11_CHANNEL1 +# ifdef CONFIG_STM32_TIM11_CH1OUT +# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT +# else +# define PWM_TIM11_CH1CFG 0 +# endif +# define PWM_TIM11_CHANNEL1 1 +#else +# define PWM_TIM11_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL2 +# ifdef CONFIG_STM32_TIM11_CH2OUT +# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT +# else +# define PWM_TIM11_CH2CFG 0 +# endif +# define PWM_TIM11_CHANNEL2 1 +#else +# define PWM_TIM11_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL3 +# ifdef CONFIG_STM32_TIM11_CH3OUT +# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT +# else +# define PWM_TIM11_CH3CFG 0 +# endif +# define PWM_TIM11_CHANNEL3 1 +#else +# define PWM_TIM11_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL4 +# ifdef CONFIG_STM32_TIM11_CH4OUT +# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT +# else +# define PWM_TIM11_CH4CFG 0 +# endif +# define PWM_TIM11_CHANNEL4 1 +#else +# define PWM_TIM11_CHANNEL4 0 +#endif +#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1 + PWM_TIM11_CHANNEL2 + \ + PWM_TIM11_CHANNEL3 + PWM_TIM11_CHANNEL4) + +#ifdef CONFIG_STM32_TIM12_CHANNEL1 +# ifdef CONFIG_STM32_TIM12_CH1OUT +# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT +# else +# define PWM_TIM12_CH1CFG 0 +# endif +# define PWM_TIM12_CHANNEL1 1 +#else +# define PWM_TIM12_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL2 +# ifdef CONFIG_STM32_TIM12_CH2OUT +# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT +# else +# define PWM_TIM12_CH2CFG 0 +# endif +# define PWM_TIM12_CHANNEL2 1 +#else +# define PWM_TIM12_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL3 +# ifdef CONFIG_STM32_TIM12_CH3OUT +# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT +# else +# define PWM_TIM12_CH3CFG 0 +# endif +# define PWM_TIM12_CHANNEL3 1 +#else +# define PWM_TIM12_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL4 +# ifdef CONFIG_STM32_TIM12_CH4OUT +# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT +# else +# define PWM_TIM12_CH4CFG 0 +# endif +# define PWM_TIM12_CHANNEL4 1 +#else +# define PWM_TIM12_CHANNEL4 0 +#endif +#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2 + \ + PWM_TIM12_CHANNEL3 + PWM_TIM12_CHANNEL4) + +#ifdef CONFIG_STM32_TIM13_CHANNEL1 +# ifdef CONFIG_STM32_TIM13_CH1OUT +# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT +# else +# define PWM_TIM13_CH1CFG 0 +# endif +# define PWM_TIM13_CHANNEL1 1 +#else +# define PWM_TIM13_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL2 +# ifdef CONFIG_STM32_TIM13_CH2OUT +# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT +# else +# define PWM_TIM13_CH2CFG 0 +# endif +# define PWM_TIM13_CHANNEL2 1 +#else +# define PWM_TIM13_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL3 +# ifdef CONFIG_STM32_TIM13_CH3OUT +# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT +# else +# define PWM_TIM13_CH3CFG 0 +# endif +# define PWM_TIM13_CHANNEL3 1 +#else +# define PWM_TIM13_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL4 +# ifdef CONFIG_STM32_TIM13_CH4OUT +# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT +# else +# define PWM_TIM13_CH4CFG 0 +# endif +# define PWM_TIM13_CHANNEL4 1 +#else +# define PWM_TIM13_CHANNEL4 0 +#endif +#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1 + PWM_TIM13_CHANNEL2 + \ + PWM_TIM13_CHANNEL3 + PWM_TIM13_CHANNEL4) + +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# ifdef CONFIG_STM32_TIM14_CH1OUT +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# else +# define PWM_TIM14_CH1CFG 0 +# endif +# define PWM_TIM14_CHANNEL1 1 +#else +# define PWM_TIM14_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL2 +# ifdef CONFIG_STM32_TIM14_CH2OUT +# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT +# else +# define PWM_TIM14_CH2CFG 0 +# endif +# define PWM_TIM14_CHANNEL2 1 +#else +# define PWM_TIM14_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL3 +# ifdef CONFIG_STM32_TIM14_CH3OUT +# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT +# else +# define PWM_TIM14_CH3CFG 0 +# endif +# define PWM_TIM14_CHANNEL3 1 +#else +# define PWM_TIM14_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL4 +# ifdef CONFIG_STM32_TIM14_CH4OUT +# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT +# else +# define PWM_TIM14_CH4CFG 0 +# endif +# define PWM_TIM14_CHANNEL4 1 +#else +# define PWM_TIM14_CHANNEL4 0 +#endif +#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1 + PWM_TIM14_CHANNEL2 + \ + PWM_TIM14_CHANNEL3 + PWM_TIM14_CHANNEL4) + +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# else +# define PWM_TIM15_CH1CFG 0 +# endif +# define PWM_TIM15_CHANNEL1 1 +#else +# define PWM_TIM15_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# define PWM_TIM15_CH2CFG 0 +# endif +# define PWM_TIM15_CHANNEL2 1 +#else +# define PWM_TIM15_CHANNEL2 0 +#endif +#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) + +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# else +# define PWM_TIM16_CH1CFG 0 +# endif +# define PWM_TIM16_CHANNEL1 1 +#else +# define PWM_TIM16_CHANNEL1 0 +#endif +#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 + +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# else +# define PWM_TIM17_CH1CFG 0 +# endif +# define PWM_TIM17_CHANNEL1 1 +#else +# define PWM_TIM17_CHANNEL1 0 +#endif +#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 + +#define PWM_MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define PWM_NCHANNELS PWM_MAX(PWM_TIM1_NCHANNELS, \ + PWM_MAX(PWM_TIM2_NCHANNELS, \ + PWM_MAX(PWM_TIM3_NCHANNELS, \ + PWM_MAX(PWM_TIM4_NCHANNELS, \ + PWM_MAX(PWM_TIM5_NCHANNELS, \ + PWM_MAX(PWM_TIM8_NCHANNELS, \ + PWM_MAX(PWM_TIM9_NCHANNELS, \ + PWM_MAX(PWM_TIM10_NCHANNELS, \ + PWM_MAX(PWM_TIM11_NCHANNELS, \ + PWM_MAX(PWM_TIM12_NCHANNELS, \ + PWM_MAX(PWM_TIM13_NCHANNELS, \ + PWM_MAX(PWM_TIM14_NCHANNELS, \ + PWM_MAX(PWM_TIM15_NCHANNELS, \ + PWM_MAX(PWM_TIM16_NCHANNELS, \ + PWM_TIM17_NCHANNELS)))))))))))))) + +#else + /* For each timer that is enabled for PWM usage, we need the following additional * configuration settings: * @@ -131,13 +728,21 @@ # if !defined(CONFIG_STM32_TIM1_CHANNEL) # error "CONFIG_STM32_TIM1_CHANNEL must be provided" # elif CONFIG_STM32_TIM1_CHANNEL == 1 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH1OUT +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # elif CONFIG_STM32_TIM1_CHANNEL == 2 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH2OUT +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # elif CONFIG_STM32_TIM1_CHANNEL == 3 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH3OUT +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # elif CONFIG_STM32_TIM1_CHANNEL == 4 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH4OUT +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif @@ -147,13 +752,21 @@ # if !defined(CONFIG_STM32_TIM2_CHANNEL) # error "CONFIG_STM32_TIM2_CHANNEL must be provided" # elif CONFIG_STM32_TIM2_CHANNEL == 1 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH1OUT +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # elif CONFIG_STM32_TIM2_CHANNEL == 2 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH2OUT +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # elif CONFIG_STM32_TIM2_CHANNEL == 3 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH3OUT +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # elif CONFIG_STM32_TIM2_CHANNEL == 4 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH4OUT +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif @@ -163,13 +776,21 @@ # if !defined(CONFIG_STM32_TIM3_CHANNEL) # error "CONFIG_STM32_TIM3_CHANNEL must be provided" # elif CONFIG_STM32_TIM3_CHANNEL == 1 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH1OUT +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # elif CONFIG_STM32_TIM3_CHANNEL == 2 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH2OUT +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # elif CONFIG_STM32_TIM3_CHANNEL == 3 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH3OUT +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # elif CONFIG_STM32_TIM3_CHANNEL == 4 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH4OUT +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif @@ -179,13 +800,21 @@ # if !defined(CONFIG_STM32_TIM4_CHANNEL) # error "CONFIG_STM32_TIM4_CHANNEL must be provided" # elif CONFIG_STM32_TIM4_CHANNEL == 1 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH1OUT +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT # elif CONFIG_STM32_TIM4_CHANNEL == 2 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH2OUT +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT # elif CONFIG_STM32_TIM4_CHANNEL == 3 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH3OUT +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT # elif CONFIG_STM32_TIM4_CHANNEL == 4 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH4OUT +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif @@ -195,13 +824,21 @@ # if !defined(CONFIG_STM32_TIM5_CHANNEL) # error "CONFIG_STM32_TIM5_CHANNEL must be provided" # elif CONFIG_STM32_TIM5_CHANNEL == 1 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH1OUT +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT # elif CONFIG_STM32_TIM5_CHANNEL == 2 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH2OUT +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT # elif CONFIG_STM32_TIM5_CHANNEL == 3 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH3OUT +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT # elif CONFIG_STM32_TIM5_CHANNEL == 4 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH4OUT +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif @@ -211,13 +848,21 @@ # if !defined(CONFIG_STM32_TIM8_CHANNEL) # error "CONFIG_STM32_TIM8_CHANNEL must be provided" # elif CONFIG_STM32_TIM8_CHANNEL == 1 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH1OUT +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # elif CONFIG_STM32_TIM8_CHANNEL == 2 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH2OUT +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # elif CONFIG_STM32_TIM8_CHANNEL == 3 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH3OUT +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # elif CONFIG_STM32_TIM8_CHANNEL == 4 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH4OUT +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif @@ -227,13 +872,21 @@ # if !defined(CONFIG_STM32_TIM9_CHANNEL) # error "CONFIG_STM32_TIM9_CHANNEL must be provided" # elif CONFIG_STM32_TIM9_CHANNEL == 1 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH1OUT +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT # elif CONFIG_STM32_TIM9_CHANNEL == 2 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH2OUT +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT # elif CONFIG_STM32_TIM9_CHANNEL == 3 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH3OUT +# define CONFIG_STM32_TIM9_CHANNEL3 1 +# define CONFIG_STM32_TIM9_CH3MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT # elif CONFIG_STM32_TIM9_CHANNEL == 4 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH4OUT +# define CONFIG_STM32_TIM9_CHANNEL4 1 +# define CONFIG_STM32_TIM9_CH4MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" # endif @@ -243,13 +896,21 @@ # if !defined(CONFIG_STM32_TIM10_CHANNEL) # error "CONFIG_STM32_TIM10_CHANNEL must be provided" # elif CONFIG_STM32_TIM10_CHANNEL == 1 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH1OUT +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT # elif CONFIG_STM32_TIM10_CHANNEL == 2 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH2OUT +# define CONFIG_STM32_TIM10_CHANNEL2 1 +# define CONFIG_STM32_TIM10_CH2MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT # elif CONFIG_STM32_TIM10_CHANNEL == 3 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH3OUT +# define CONFIG_STM32_TIM10_CHANNEL3 1 +# define CONFIG_STM32_TIM10_CH3MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT # elif CONFIG_STM32_TIM10_CHANNEL == 4 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH4OUT +# define CONFIG_STM32_TIM10_CHANNEL4 1 +# define CONFIG_STM32_TIM10_CH4MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" # endif @@ -259,13 +920,21 @@ # if !defined(CONFIG_STM32_TIM11_CHANNEL) # error "CONFIG_STM32_TIM11_CHANNEL must be provided" # elif CONFIG_STM32_TIM11_CHANNEL == 1 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH1OUT +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT # elif CONFIG_STM32_TIM11_CHANNEL == 2 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH2OUT +# define CONFIG_STM32_TIM11_CHANNEL2 1 +# define CONFIG_STM32_TIM11_CH2MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT # elif CONFIG_STM32_TIM11_CHANNEL == 3 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH3OUT +# define CONFIG_STM32_TIM11_CHANNEL3 1 +# define CONFIG_STM32_TIM11_CH3MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT # elif CONFIG_STM32_TIM11_CHANNEL == 4 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH4OUT +# define CONFIG_STM32_TIM11_CHANNEL4 1 +# define CONFIG_STM32_TIM11_CH4MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" # endif @@ -275,13 +944,21 @@ # if !defined(CONFIG_STM32_TIM12_CHANNEL) # error "CONFIG_STM32_TIM12_CHANNEL must be provided" # elif CONFIG_STM32_TIM12_CHANNEL == 1 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH1OUT +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT # elif CONFIG_STM32_TIM12_CHANNEL == 2 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH2OUT +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT # elif CONFIG_STM32_TIM12_CHANNEL == 3 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH3OUT +# define CONFIG_STM32_TIM12_CHANNEL3 1 +# define CONFIG_STM32_TIM12_CH3MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT # elif CONFIG_STM32_TIM12_CHANNEL == 4 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH4OUT +# define CONFIG_STM32_TIM12_CHANNEL4 1 +# define CONFIG_STM32_TIM12_CH4MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif @@ -291,13 +968,21 @@ # if !defined(CONFIG_STM32_TIM13_CHANNEL) # error "CONFIG_STM32_TIM13_CHANNEL must be provided" # elif CONFIG_STM32_TIM13_CHANNEL == 1 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH1OUT +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT # elif CONFIG_STM32_TIM13_CHANNEL == 2 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH2OUT +# define CONFIG_STM32_TIM13_CHANNEL2 1 +# define CONFIG_STM32_TIM13_CH2MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT # elif CONFIG_STM32_TIM13_CHANNEL == 3 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH3OUT +# define CONFIG_STM32_TIM13_CHANNEL3 1 +# define CONFIG_STM32_TIM13_CH3MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT # elif CONFIG_STM32_TIM13_CHANNEL == 4 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH4OUT +# define CONFIG_STM32_TIM13_CHANNEL4 1 +# define CONFIG_STM32_TIM13_CH4MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif @@ -307,18 +992,70 @@ # if !defined(CONFIG_STM32_TIM14_CHANNEL) # error "CONFIG_STM32_TIM14_CHANNEL must be provided" # elif CONFIG_STM32_TIM14_CHANNEL == 1 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH1OUT +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT # elif CONFIG_STM32_TIM14_CHANNEL == 2 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH2OUT +# define CONFIG_STM32_TIM14_CHANNEL2 1 +# define CONFIG_STM32_TIM14_CH2MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT # elif CONFIG_STM32_TIM14_CHANNEL == 3 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH3OUT +# define CONFIG_STM32_TIM14_CHANNEL3 1 +# define CONFIG_STM32_TIM14_CH3MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT # elif CONFIG_STM32_TIM14_CHANNEL == 4 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH4OUT +# define CONFIG_STM32_TIM14_CHANNEL4 1 +# define CONFIG_STM32_TIM14_CH4MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif #endif +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" +# endif +#endif + +#define PWM_NCHANNELS 1 + +#endif + /************************************************************************************ * Public Types ************************************************************************************/ @@ -351,7 +1088,7 @@ extern "C" * Input Parameters: * timer - A number identifying the timer use. The number of valid timer * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,14}. + * the range of {1,..,17}. * * Returned Value: * On success, a pointer to the STM32 lower half PWM driver is returned. From f6d7da24a7cd6c3b6a5a80a76a4deec704b9e77c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 2 Nov 2015 06:39:24 -0600 Subject: [PATCH 09/10] SAM4CM should advertise that it supports Tickless operation in Kconfig --- arch/arm/src/sam34/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index 56c7ff2c9f8..65d456fa966 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -240,6 +240,7 @@ config ARCH_CHIP_SAM3A config ARCH_CHIP_SAM4CM bool default n + select ARCH_HAVE_TICKLESS config ARCH_CHIP_SAM4L bool From c90876ff9c0ad935b0872ff586b3ecaa082c038a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 2 Nov 2015 13:58:19 -0600 Subject: [PATCH 10/10] SAMV7: Add configuration support (only) for use of USART as SPI --- arch/arm/src/samv7/sam_config.h | 22 +++++--- arch/arm/src/samv7/sam_serial.c | 90 ++++++++++++++++++++------------- 2 files changed, 70 insertions(+), 42 deletions(-) diff --git a/arch/arm/src/samv7/sam_config.h b/arch/arm/src/samv7/sam_config.h index 8aca6fb6fd4..242c2eb5037 100644 --- a/arch/arm/src/samv7/sam_config.h +++ b/arch/arm/src/samv7/sam_config.h @@ -109,18 +109,26 @@ #endif /* USARTs *******************************************************************/ -/* If the USART is not being used as a UART, then it really isn't enabled - * for our purposes. +/* If the USART is not being used as a UART or for SPI, then it really isn't + * enabled for our purposes. */ -#ifndef CONFIG_USART0_ISUART +#if !defined(CONFIG_USART0_ISUART) && !defined(CONFIG_USART0_ISSPI) # undef CONFIG_SAMV7_USART0 +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART0_IFLOWCONTROL #endif -#ifndef CONFIG_USART1_ISUART + +#if !defined(CONFIG_USART1_ISUART) && !defined(CONFIG_USART1_ISSPI) # undef CONFIG_SAMV7_USART1 +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART1_IFLOWCONTROL #endif -#ifndef CONFIG_USART2_ISUART + +#if !defined(CONFIG_USART2_ISUART) && !defined(CONFIG_USART2_ISSPI) # undef CONFIG_SAMV7_USART2 +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART2_IFLOWCONTROL #endif /* Don't enable USARTs not supported by the chip. */ @@ -153,10 +161,10 @@ #undef CONFIG_UART3_IFLOWCONTROL #undef CONFIG_UART4_IFLOWCONTROL -/* Hardware flow control requires using DMAC channel (not yet supported) */ +/* Hardware flow control requires using a DMAC channel (not yet supported) */ #ifdef CONFIG_SERIAL_IFLOWCONTROL -# warning PDC or DMAC support is required for RTS hardware flow control +# warning XDMAC support is required for RTS hardware flow control # undef CONFIG_SERIAL_IFLOWCONTROL # undef CONFIG_USART0_IFLOWCONTROL # undef CONFIG_USART1_IFLOWCONTROL diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 47f7d8e9265..a520350f982 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -123,13 +123,13 @@ # elif defined(CONFIG_SAMV7_UART4) # define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ # define UART4_ASSIGNED 1 -# elif defined(CONFIG_SAMV7_USART0) +# elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) # define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ # define USART0_ASSIGNED 1 -# elif defined(CONFIG_SAMV7_USART1) +# elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) # define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ # define USART1_ASSIGNED 1 -# elif defined(CONFIG_SAMV7_USART2) +# elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) # define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ # define USART2_ASSIGNED 1 # endif @@ -154,13 +154,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */ # define USART2_ASSIGNED 1 #endif @@ -182,13 +185,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */ # define USART2_ASSIGNED 1 #endif @@ -207,13 +213,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */ # define USART2_ASSIGNED 1 #endif @@ -229,13 +238,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS4_DEV g_usart0port /* USART0 is ttyS4 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ # define USART2_ASSIGNED 1 #endif @@ -248,13 +260,16 @@ #if defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS5_DEV g_usart0port /* USART0 is ttyS5 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS5_DEV g_usart1port /* USART1 is ttyS5 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ # define USART2_ASSIGNED 1 #endif @@ -264,13 +279,16 @@ * One of USART0-2 could also be the console. */ -#if defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS6_DEV g_usart0port /* USART0 is ttyS6 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS6_DEV g_usart1port /* USART1 is ttyS6 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS6_DEV g_usart2port /* USART2 is ttyS6 */ # define USART2_ASSIGNED 1 #endif @@ -280,10 +298,12 @@ * One of of USART1-2 could also be the console. */ -#if defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS7_DEV g_usart1port /* USART1 is ttyS7 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS7_DEV g_usart2port /* USART2 is ttyS7 */ # define USART2_ASSIGNED 1 #endif @@ -349,13 +369,13 @@ static int sam_uart3_interrupt(int irq, void *context); #ifdef CONFIG_SAMV7_UART4 static int sam_uart4_interrupt(int irq, void *context); #endif -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static int sam_usart0_interrupt(int irq, void *context); #endif -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static int sam_usart1_interrupt(int irq, void *context); #endif -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static int sam_usart2_interrupt(int irq, void *context); #endif static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); @@ -412,15 +432,15 @@ static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; #endif -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE]; #endif -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; #endif @@ -582,7 +602,7 @@ static uart_dev_t g_uart4port = /* This describes the state of the USART0 port. */ -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static struct sam_dev_s g_usart0priv = { .usartbase = SAM_USART0_BASE, @@ -616,7 +636,7 @@ static uart_dev_t g_usart0port = /* This describes the state of the USART1 port. */ -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static struct sam_dev_s g_usart1priv = { .usartbase = SAM_USART1_BASE, @@ -650,7 +670,7 @@ static uart_dev_t g_usart1port = /* This describes the state of the USART2 port. */ -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static struct sam_dev_s g_usart2priv = { .usartbase = SAM_USART2_BASE, @@ -1095,19 +1115,19 @@ static int sam_uart4_interrupt(int irq, void *context) * ****************************************************************************/ -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static int sam_usart0_interrupt(int irq, void *context) { return sam_interrupt(&g_usart0port); } #endif -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static int sam_usart1_interrupt(int irq, void *context) { return sam_interrupt(&g_usart1port); } #endif -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static int sam_usart2_interrupt(int irq, void *context) { return sam_interrupt(&g_usart2port);