diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h index a9d9e676d66..d0834d142a2 100644 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h @@ -79,6 +79,16 @@ #define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ + +#if defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ + defined(CONFIG_STM32F0L0G0_STM32G0C1) +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ +#endif + #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ #define STM32_IRQ_EXTI17_18 (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */ diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 4eb19ca36c4..2262dbe0c91 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -1267,13 +1267,19 @@ config STM32F0L0G0_STM32G030 bool default n select STM32F0L0G0_STM32G0 + select STM32F0L0G0_STM32G03X config STM32F0L0G0_STM32G031 bool default n select STM32F0L0G0_STM32G0 + select STM32F0L0G0_STM32G03X select STM32F0L0G0_HAVE_LPUART1 +config STM32F0L0G0_STM32G03X + bool + default n + config STM32F0L0G0_STM32G041 bool default n @@ -1286,21 +1292,25 @@ config STM32F0L0G0_STM32G050 bool default n select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 + select STM32F0L0G0_STM32G05X config STM32F0L0G0_STM32G051 bool default n select STM32F0L0G0_STM32G0 + select STM32F0L0G0_STM32G05X select STM32F0L0G0_HAVE_DAC1 select STM32F0L0G0_HAVE_COMP1 select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 select STM32F0L0G0_HAVE_TIM15 select STM32F0L0G0_HAVE_LPUART1 +config STM32F0L0G0_STM32G05X + bool + default n + select STM32F0L0G0_HAVE_TIM6 + select STM32F0L0G0_HAVE_TIM7 + config STM32F0L0G0_STM32G061 bool default n @@ -1319,30 +1329,29 @@ config STM32F0L0G0_STM32G070 bool default n select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 + select STM32F0L0G0_STM32G07X config STM32F0L0G0_STM32G071 bool default n select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 + select STM32F0L0G0_STM32G07X select STM32F0L0G0_HAVE_DAC1 select STM32F0L0G0_HAVE_COMP1 select STM32F0L0G0_HAVE_COMP2 + select STM32F0L0G0_HAVE_CEC + select STM32F0L0G0_HAVE_LPUART1 + +config STM32F0L0G0_STM32G07X + bool + default n + select STM32F0L0G0_HAVE_USART3 + select STM32F0L0G0_HAVE_USART4 select STM32F0L0G0_HAVE_TIM6 select STM32F0L0G0_HAVE_TIM7 select STM32F0L0G0_HAVE_TIM15 select STM32F0L0G0_HAVE_UCPD1 select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 config STM32F0L0G0_STM32G081 bool @@ -1367,30 +1376,24 @@ config STM32F0L0G0_STM32G0B0 bool default n select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_LPUART1 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_HSI48 + select STM32F0L0G0_STM32G0BX config STM32F0L0G0_STM32G0B1 bool default n select STM32F0L0G0_STM32G0 + select STM32F0L0G0_STM32G0BX + select STM32F0L0G0_HAVE_DAC1 + select STM32F0L0G0_HAVE_COMP1 + select STM32F0L0G0_HAVE_COMP2 + select STM32F0L0G0_HAVE_COMP3 + select STM32F0L0G0_HAVE_FDCAN1 + select STM32F0L0G0_HAVE_FDCAN2 + select STM32F0L0G0_HAVE_CEC + +config STM32F0L0G0_STM32G0BX + bool + default n select STM32F0L0G0_HAVE_DMA2 select STM32F0L0G0_HAVE_USART3 select STM32F0L0G0_HAVE_USART4 @@ -1399,10 +1402,6 @@ config STM32F0L0G0_STM32G0B1 select STM32F0L0G0_HAVE_LPUART1 select STM32F0L0G0_HAVE_LPUART2 select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 select STM32F0L0G0_HAVE_TIM4 select STM32F0L0G0_HAVE_TIM6 select STM32F0L0G0_HAVE_TIM7 @@ -1413,9 +1412,6 @@ config STM32F0L0G0_STM32G0B1 select STM32F0L0G0_HAVE_USBDEV select STM32F0L0G0_HAVE_UCPD1 select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC select STM32F0L0G0_HAVE_HSI48 config STM32F0L0G0_STM32G0C1 @@ -3698,6 +3694,16 @@ config STM32F0L0G0_ADC1_EXTSEL ---help--- Enable EXTSEL for ADC1. +config STM32F0L0G0_ADC1_CONTINUOUS + bool "Enable ADC1 Continuous Conversion Mode" + default n + depends on STM32F0L0G0_ADC1 + ---help--- + If enabled, the ADC will operate in continuous conversion mode. + Otherwise, it will perform single conversions. + Note: Continuous and discontinuous mode cannot be defined at + the same time + endmenu # ADC Configuration menu "SPI Configuration" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h index 35873b30d2c..b855b530df5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h @@ -243,8 +243,9 @@ #define ADC_SMPR_SMP2_SHIFT (4) /* Bits 4-6: Sampling time selection 2 */ #define ADC_SMPR_SMP2_MASK (7 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMPSEL_SHIFT (8) /* Bits 8-26: channel-x sampling time selection */ -#if defined(CONFIG_ARCH_CHIP_STM32G0) -# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..18] and smp = 1 or 0 */ +#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) +# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..22] and smp = 0 or 1 */ +# define ADC_SMPSEL(ch, smp) ((smp) << (ch)) /* For use in adc_sampletime_set */ #else # define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT) #endif diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h index 67e3a291b29..2f1161c7d37 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h @@ -36,26 +36,290 @@ /* DMAMUX1 mapping **********************************************************/ -/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7 */ +/* Peripheral to DMAMUX request line mappings (RM0444 Rev 6, Table 55) */ -#define DMAMUX1_REQ_GEN0 (1) -#define DMAMUX1_REQ_GEN1 (2) -#define DMAMUX1_REQ_GEN2 (3) -#define DMAMUX1_REQ_GEN3 (4) -#define DMAMUX1_ADC1 (5) -#define DMAMUX1_AES_IN (6) -#define DMAMUX1_AES_OUT (7) +#define DMAMUX1_REQ_GEN0 1 +#define DMAMAP_DMA1_REQ_GEN0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0) +#define DMAMAP_DMA2_REQ_GEN0 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN0) +#define DMAMUX1_REQ_GEN1 2 +#define DMAMAP_DMA1_REQ_GEN1 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1) +#define DMAMAP_DMA2_REQ_GEN1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN1) +#define DMAMUX1_REQ_GEN2 3 +#define DMAMAP_DMA1_REQ_GEN2 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2) +#define DMAMAP_DMA2_REQ_GEN2 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN2) +#define DMAMUX1_REQ_GEN3 4 +#define DMAMAP_DMA1_REQ_GEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3) +#define DMAMAP_DMA2_REQ_GEN3 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN3) +#define DMAMUX1_ADC1 5 +#define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1) +#define DMAMAP_DMA2_ADC1 DMAMAP_MAP(DMA2, DMAMUX1_ADC1) +#define DMAMUX1_AES_IN 6 +#define DMAMAP_DMA1_AES_IN DMAMAP_MAP(DMA1, DMAMUX1_AES_IN) +#define DMAMAP_DMA2_AES_IN DMAMAP_MAP(DMA2, DMAMUX1_AES_IN) +#define DMAMUX1_AES_OUT 7 +#define DMAMAP_DMA1_AES_OUT DMAMAP_MAP(DMA1, DMAMUX1_AES_OUT) +#define DMAMAP_DMA2_AES_OUT DMAMAP_MAP(DMA2, DMAMUX1_AES_OUT) +#define DMAMUX1_DAC_CH1 8 +#define DMAMAP_DMA1_DAC_CH1 DMAMAP_MAP(DMA1, DMAMUX1_DAC_CH1) +#define DMAMAP_DMA2_DAC_CH1 DMAMAP_MAP(DMA2, DMAMUX1_DAC_CH1) +#define DMAMUX1_DAC_CH2 9 +#define DMAMAP_DMA1_DAC_CH2 DMAMAP_MAP(DMA1, DMAMUX1_DAC_CH2) +#define DMAMAP_DMA2_DAC_CH2 DMAMAP_MAP(DMA2, DMAMUX1_DAC_CH2) +#define DMAMUX1_I2C1_RX 10 +#define DMAMAP_DMA1_I2C1_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C1_RX) +#define DMAMAP_DMA2_I2C1_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C1_RX) +#define DMAMUX1_I2C1_TX 11 +#define DMAMAP_DMA1_I2C1_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C1_TX) +#define DMAMAP_DMA2_I2C1_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C1_TX) +#define DMAMUX1_I2C2_RX 12 +#define DMAMAP_DMA1_I2C2_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C2_RX) +#define DMAMAP_DMA2_I2C2_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C2_RX) +#define DMAMUX1_I2C2_TX 13 +#define DMAMAP_DMA1_I2C2_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C2_TX) +#define DMAMAP_DMA2_I2C2_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C2_TX) +#define DMAMUX1_LPUART1_RX 14 +#define DMAMAP_DMA1_LPUART1_RX DMAMAP_MAP(DMA1, DMAMUX1_LPUART1_RX) +#define DMAMAP_DMA2_LPUART1_RX DMAMAP_MAP(DMA2, DMAMUX1_LPUART1_RX) +#define DMAMUX1_LPUART1_TX 15 +#define DMAMAP_DMA1_LPUART1_TX DMAMAP_MAP(DMA1, DMAMUX1_LPUART1_TX) +#define DMAMAP_DMA2_LPUART1_TX DMAMAP_MAP(DMA2, DMAMUX1_LPUART1_TX) +#define DMAMUX1_SPI1_RX 16 +#define DMAMAP_DMA1_SPI1_RX DMAMAP_MAP(DMA1, DMAMUX1_SPI1_RX) +#define DMAMAP_DMA2_SPI1_RX DMAMAP_MAP(DMA2, DMAMUX1_SPI1_RX) +#define DMAMUX1_SPI1_TX 17 +#define DMAMAP_DMA1_SPI1_TX DMAMAP_MAP(DMA1, DMAMUX1_SPI1_TX) +#define DMAMAP_DMA2_SPI1_TX DMAMAP_MAP(DMA2, DMAMUX1_SPI1_TX) +#define DMAMUX1_SPI2_RX 18 +#define DMAMAP_DMA1_SPI2_RX DMAMAP_MAP(DMA1, DMAMUX1_SPI2_RX) +#define DMAMAP_DMA2_SPI2_RX DMAMAP_MAP(DMA2, DMAMUX1_SPI2_RX) +#define DMAMUX1_SPI2_TX 19 +#define DMAMAP_DMA1_SPI2_TX DMAMAP_MAP(DMA1, DMAMUX1_SPI2_TX) +#define DMAMAP_DMA2_SPI2_TX DMAMAP_MAP(DMA2, DMAMUX1_SPI2_TX) +#define DMAMUX1_TIM1_CH1 20 +#define DMAMAP_DMA1_TIM1_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH1) +#define DMAMAP_DMA2_TIM1_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH1) +#define DMAMUX1_TIM1_CH2 21 +#define DMAMAP_DMA1_TIM1_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH2) +#define DMAMAP_DMA2_TIM1_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH2) +#define DMAMUX1_TIM1_CH3 22 +#define DMAMAP_DMA1_TIM1_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH3) +#define DMAMAP_DMA2_TIM1_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH3) +#define DMAMUX1_TIM1_CH4 23 +#define DMAMAP_DMA1_TIM1_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH4) +#define DMAMAP_DMA2_TIM1_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH4) +#define DMAMUX1_TIM1_TRIG 24 +#define DMAMAP_DMA1_TIM1_TRIG DMAMAP_MAP(DMA1, DMAMUX1_TIM1_TRIG) +#define DMAMAP_DMA2_TIM1_TRIG DMAMAP_MAP(DMA2, DMAMUX1_TIM1_TRIG) +#define DMAMUX1_TIM1_UP 25 +#define DMAMAP_DMA1_TIM1_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM1_UP) +#define DMAMAP_DMA2_TIM1_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM1_UP) +#define DMAMUX1_TIM2_CH1 26 +#define DMAMAP_DMA1_TIM2_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH1) +#define DMAMAP_DMA2_TIM2_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH1) +#define DMAMUX1_TIM2_CH2 27 +#define DMAMAP_DMA1_TIM2_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH2) +#define DMAMAP_DMA2_TIM2_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH2) +#define DMAMUX1_TIM2_CH3 28 +#define DMAMAP_DMA1_TIM2_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH3) +#define DMAMAP_DMA2_TIM2_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH3) +#define DMAMUX1_TIM2_CH4 29 +#define DMAMAP_DMA1_TIM2_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH4) +#define DMAMAP_DMA2_TIM2_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH4) +#define DMAMUX1_TIM2_TRIG 30 +#define DMAMAP_DMA1_TIM2_TRIG DMAMAP_MAP(DMA1, DMAMUX1_TIM2_TRIG) +#define DMAMAP_DMA2_TIM2_TRIG DMAMAP_MAP(DMA2, DMAMUX1_TIM2_TRIG) +#define DMAMUX1_TIM2_UP 31 +#define DMAMAP_DMA1_TIM2_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM2_UP) +#define DMAMAP_DMA2_TIM2_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM2_UP) +#define DMAMUX1_TIM3_CH1 32 +#define DMAMAP_DMA1_TIM3_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH1) +#define DMAMAP_DMA2_TIM3_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH1) +#define DMAMUX1_TIM3_CH2 33 +#define DMAMAP_DMA1_TIM3_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH2) +#define DMAMAP_DMA2_TIM3_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH2) +#define DMAMUX1_TIM3_CH3 34 +#define DMAMAP_DMA1_TIM3_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH3) +#define DMAMAP_DMA2_TIM3_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH3) +#define DMAMUX1_TIM3_CH4 35 +#define DMAMAP_DMA1_TIM3_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH4) +#define DMAMAP_DMA2_TIM3_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH4) +#define DMAMUX1_TIM3_TRIG 36 +#define DMAMAP_DMA1_TIM3_TRIG DMAMAP_MAP(DMA1, DMAMUX1_TIM3_TRIG) +#define DMAMAP_DMA2_TIM3_TRIG DMAMAP_MAP(DMA2, DMAMUX1_TIM3_TRIG) +#define DMAMUX1_TIM3_UP 37 +#define DMAMAP_DMA1_TIM3_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM3_UP) +#define DMAMAP_DMA2_TIM3_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM3_UP) +#define DMAMUX1_TIM6_UP 38 +#define DMAMAP_DMA1_TIM6_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM6_UP) +#define DMAMAP_DMA2_TIM6_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM6_UP) +#define DMAMUX1_TIM7_UP 39 +#define DMAMAP_DMA1_TIM7_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM7_UP) +#define DMAMAP_DMA2_TIM7_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM7_UP) +#define DMAMUX1_TIM15_CH1 40 +#define DMAMAP_DMA1_TIM15_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_CH1) +#define DMAMAP_DMA2_TIM15_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_CH1) +#define DMAMUX1_TIM15_CH2 41 +#define DMAMAP_DMA1_TIM15_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_CH2) +#define DMAMAP_DMA2_TIM15_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_CH2) +#define DMAMUX1_TIM15_TRIG_COM 42 +#define DMAMAP_DMA1_TIM15_TRIG_COM DMAMAP_MAP(DMA1, DMAMUX1_TIM15_TRIG_COM) +#define DMAMAP_DMA2_TIM15_TRIG_COM DMAMAP_MAP(DMA2, DMAMUX1_TIM15_TRIG_COM) +#define DMAMUX1_TIM15_UP 43 +#define DMAMAP_DMA1_TIM15_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM15_UP) +#define DMAMAP_DMA2_TIM15_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM15_UP) +#define DMAMUX1_TIM16_CH1 44 +#define DMAMAP_DMA1_TIM16_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM16_CH1) +#define DMAMAP_DMA2_TIM16_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM16_CH1) +#define DMAMUX1_TIM16_COM 45 +#define DMAMAP_DMA1_TIM16_COM DMAMAP_MAP(DMA1, DMAMUX1_TIM16_COM) +#define DMAMAP_DMA2_TIM16_COM DMAMAP_MAP(DMA2, DMAMUX1_TIM16_COM) +#define DMAMUX1_TIM16_UP 46 +#define DMAMAP_DMA1_TIM16_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM16_UP) +#define DMAMAP_DMA2_TIM16_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM16_UP) +#define DMAMUX1_TIM17_CH1 47 +#define DMAMAP_DMA1_TIM17_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM17_CH1) +#define DMAMAP_DMA2_TIM17_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM17_CH1) +#define DMAMUX1_TIM17_COM 48 +#define DMAMAP_DMA1_TIM17_COM DMAMAP_MAP(DMA1, DMAMUX1_TIM17_COM) +#define DMAMAP_DMA2_TIM17_COM DMAMAP_MAP(DMA2, DMAMUX1_TIM17_COM) +#define DMAMUX1_TIM17_UP 49 +#define DMAMAP_DMA1_TIM17_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM17_UP) +#define DMAMAP_DMA2_TIM17_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM17_UP) +#define DMAMUX1_USART1_RX 50 +#define DMAMAP_DMA1_USART1_RX DMAMAP_MAP(DMA1, DMAMUX1_USART1_RX) +#define DMAMAP_DMA2_USART1_RX DMAMAP_MAP(DMA2, DMAMUX1_USART1_RX) +#define DMAMUX1_USART1_TX 51 +#define DMAMAP_DMA1_USART1_TX DMAMAP_MAP(DMA1, DMAMUX1_USART1_TX) +#define DMAMAP_DMA2_USART1_TX DMAMAP_MAP(DMA2, DMAMUX1_USART1_TX) +#define DMAMUX1_USART2_RX 52 +#define DMAMAP_DMA1_USART2_RX DMAMAP_MAP(DMA1, DMAMUX1_USART2_RX) +#define DMAMAP_DMA2_USART2_RX DMAMAP_MAP(DMA2, DMAMUX1_USART2_RX) +#define DMAMUX1_USART2_TX 53 +#define DMAMAP_DMA1_USART2_TX DMAMAP_MAP(DMA1, DMAMUX1_USART2_TX) +#define DMAMAP_DMA2_USART2_TX DMAMAP_MAP(DMA2, DMAMUX1_USART2_TX) +#define DMAMUX1_USART3_RX 54 +#define DMAMAP_DMA1_USART3_RX DMAMAP_MAP(DMA1, DMAMUX1_USART3_RX) +#define DMAMAP_DMA2_USART3_RX DMAMAP_MAP(DMA2, DMAMUX1_USART3_RX) +#define DMAMUX1_USART3_TX 55 +#define DMAMAP_DMA1_USART3_TX DMAMAP_MAP(DMA1, DMAMUX1_USART3_TX) +#define DMAMAP_DMA2_USART3_TX DMAMAP_MAP(DMA2, DMAMUX1_USART3_TX) +#define DMAMUX1_USART4_RX 56 +#define DMAMAP_DMA1_USART4_RX DMAMAP_MAP(DMA1, DMAMUX1_USART4_RX) +#define DMAMAP_DMA2_USART4_RX DMAMAP_MAP(DMA2, DMAMUX1_USART4_RX) +#define DMAMUX1_USART4_TX 57 +#define DMAMAP_DMA1_USART4_TX DMAMAP_MAP(DMA1, DMAMUX1_USART4_TX) +#define DMAMAP_DMA2_USART4_TX DMAMAP_MAP(DMA2, DMAMUX1_USART4_TX) +#define DMAMUX1_UCPD1_RX 58 +#define DMAMAP_DMA1_UCPD1_RX DMAMAP_MAP(DMA1, DMAMUX1_UCPD1_RX) +#define DMAMAP_DMA2_UCPD1_RX DMAMAP_MAP(DMA2, DMAMUX1_UCPD1_RX) +#define DMAMUX1_UCPD1_TX 59 +#define DMAMAP_DMA1_UCPD1_TX DMAMAP_MAP(DMA1, DMAMUX1_UCPD1_TX) +#define DMAMAP_DMA2_UCPD1_TX DMAMAP_MAP(DMA2, DMAMUX1_UCPD1_TX) +#define DMAMUX1_UCPD2_RX 60 +#define DMAMAP_DMA1_UCPD2_RX DMAMAP_MAP(DMA1, DMAMUX1_UCPD2_RX) +#define DMAMAP_DMA2_UCPD2_RX DMAMAP_MAP(DMA2, DMAMUX1_UCPD2_RX) +#define DMAMUX1_UCPD2_TX 61 +#define DMAMAP_DMA1_UCPD2_TX DMAMAP_MAP(DMA1, DMAMUX1_UCPD2_TX) +#define DMAMAP_DMA2_UCPD2_TX DMAMAP_MAP(DMA2, DMAMUX1_UCPD2_TX) +#define DMAMUX1_I2C3_RX 62 +#define DMAMAP_DMA1_I2C3_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C3_RX) +#define DMAMAP_DMA2_I2C3_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C3_RX) +#define DMAMUX1_I2C3_TX 63 +#define DMAMAP_DMA1_I2C3_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C3_TX) +#define DMAMAP_DMA2_I2C3_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C3_TX) +#define DMAMUX1_LPUART2_RX 64 +#define DMAMAP_DMA1_LPUART2_RX DMAMAP_MAP(DMA1, DMAMUX1_LPUART2_RX) +#define DMAMAP_DMA2_LPUART2_RX DMAMAP_MAP(DMA2, DMAMUX1_LPUART2_RX) +#define DMAMUX1_LPUART2_TX 65 +#define DMAMAP_DMA1_LPUART2_TX DMAMAP_MAP(DMA1, DMAMUX1_LPUART2_TX) +#define DMAMAP_DMA2_LPUART2_TX DMAMAP_MAP(DMA2, DMAMUX1_LPUART2_TX) +#define DMAMUX1_SPI3_RX 66 +#define DMAMAP_DMA1_SPI3_RX DMAMAP_MAP(DMA1, DMAMUX1_SPI3_RX) +#define DMAMAP_DMA2_SPI3_RX DMAMAP_MAP(DMA2, DMAMUX1_SPI3_RX) +#define DMAMUX1_SPI3_TX 67 +#define DMAMAP_DMA1_SPI3_TX DMAMAP_MAP(DMA1, DMAMUX1_SPI3_TX) +#define DMAMAP_DMA2_SPI3_TX DMAMAP_MAP(DMA2, DMAMUX1_SPI3_TX) +#define DMAMUX1_TIM4_CH1 68 +#define DMAMAP_DMA1_TIM4_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM4_CH1) +#define DMAMAP_DMA2_TIM4_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM4_CH1) +#define DMAMUX1_TIM4_CH2 69 +#define DMAMAP_DMA1_TIM4_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM4_CH2) +#define DMAMAP_DMA2_TIM4_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM4_CH2) +#define DMAMUX1_TIM4_CH3 70 +#define DMAMAP_DMA1_TIM4_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM4_CH3) +#define DMAMAP_DMA2_TIM4_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM4_CH3) +#define DMAMUX1_TIM4_CH4 71 +#define DMAMAP_DMA1_TIM4_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM4_CH4) +#define DMAMAP_DMA2_TIM4_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM4_CH4) +#define DMAMUX1_TIM4_TRIG 72 +#define DMAMAP_DMA1_TIM4_TRIG DMAMAP_MAP(DMA1, DMAMUX1_TIM4_TRIG) +#define DMAMAP_DMA2_TIM4_TRIG DMAMAP_MAP(DMA2, DMAMUX1_TIM4_TRIG) +#define DMAMUX1_TIM4_UP 73 +#define DMAMAP_DMA1_TIM4_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM4_UP) +#define DMAMAP_DMA2_TIM4_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM4_UP) +#define DMAMUX1_USART5_RX 74 +#define DMAMAP_DMA1_USART5_RX DMAMAP_MAP(DMA1, DMAMUX1_USART5_RX) +#define DMAMAP_DMA2_USART5_RX DMAMAP_MAP(DMA2, DMAMUX1_USART5_RX) +#define DMAMUX1_USART5_TX 75 +#define DMAMAP_DMA1_USART5_TX DMAMAP_MAP(DMA1, DMAMUX1_USART5_TX) +#define DMAMAP_DMA2_USART5_TX DMAMAP_MAP(DMA2, DMAMUX1_USART5_TX) +#define DMAMUX1_USART6_RX 76 +#define DMAMAP_DMA1_USART6_RX DMAMAP_MAP(DMA1, DMAMUX1_USART6_RX) +#define DMAMAP_DMA2_USART6_RX DMAMAP_MAP(DMA2, DMAMUX1_USART6_RX) +#define DMAMUX1_USART6_TX 77 +#define DMAMAP_DMA1_USART6_TX DMAMAP_MAP(DMA1, DMAMUX1_USART6_TX) +#define DMAMAP_DMA2_USART6_TX DMAMAP_MAP(DMA2, DMAMUX1_USART6_TX) -/* TODO: ... */ +/* DMAMUX trigger input sources (Table 56, RM0444 Rev 6) */ -/* DMAP for DMA1 */ +#define DMAMUX_TRIG_EXTI0 0 +#define DMAMUX_TRIG_EXTI1 1 +#define DMAMUX_TRIG_EXTI2 2 +#define DMAMUX_TRIG_EXTI3 3 +#define DMAMUX_TRIG_EXTI4 4 +#define DMAMUX_TRIG_EXTI5 5 +#define DMAMUX_TRIG_EXTI6 6 +#define DMAMUX_TRIG_EXTI7 7 +#define DMAMUX_TRIG_EXTI8 8 +#define DMAMUX_TRIG_EXTI9 9 +#define DMAMUX_TRIG_EXTI10 10 +#define DMAMUX_TRIG_EXTI11 11 +#define DMAMUX_TRIG_EXTI12 12 +#define DMAMUX_TRIG_EXTI13 13 +#define DMAMUX_TRIG_EXTI14 14 +#define DMAMUX_TRIG_EXTI15 15 +#define DMAMUX_TRIG_EVT0 16 +#define DMAMUX_TRIG_EVT1 17 +#define DMAMUX_TRIG_EVT2 18 +#define DMAMUX_TRIG_EVT3 19 +#define DMAMUX_TRIG_LPTIM1_OUT 20 +#define DMAMUX_TRIG_LPTIM2_OUT 21 +#define DMAMUX_TRIG_TIM14_OC 22 -#define DMAMAP_DMA1_REQGEN0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0) -#define DMAMAP_DMA1_REQGEN1 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1) -#define DMAMAP_DMA1_REQGEN2 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2) -#define DMAMAP_DMA1_REQGEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3) -#define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1) +/* Sync inputs use the same values as trigger inputs (Table 57) */ -/* TODO: ... */ +#define DMAMUX_SYNC_EXTI0 0 +#define DMAMUX_SYNC_EXTI1 1 +#define DMAMUX_SYNC_EXTI2 2 +#define DMAMUX_SYNC_EXTI3 3 +#define DMAMUX_SYNC_EXTI4 4 +#define DMAMUX_SYNC_EXTI5 5 +#define DMAMUX_SYNC_EXTI6 6 +#define DMAMUX_SYNC_EXTI7 7 +#define DMAMUX_SYNC_EXTI8 8 +#define DMAMUX_SYNC_EXTI9 9 +#define DMAMUX_SYNC_EXTI10 10 +#define DMAMUX_SYNC_EXTI11 11 +#define DMAMUX_SYNC_EXTI12 12 +#define DMAMUX_SYNC_EXTI13 13 +#define DMAMUX_SYNC_EXTI14 14 +#define DMAMUX_SYNC_EXTI15 15 +#define DMAMUX_SYNC_EVT0 16 +#define DMAMUX_SYNC_EVT1 17 +#define DMAMUX_SYNC_EVT2 18 +#define DMAMUX_SYNC_EVT3 19 +#define DMAMUX_SYNC_LPTIM1_OUT 20 +#define DMAMUX_SYNC_LPTIM2_OUT 21 +#define DMAMUX_SYNC_TIM14_OC 22 #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h index df536a60d36..595e1886b4c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h @@ -101,7 +101,7 @@ /* AHB1 Base Addresses ******************************************************/ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ -#define STM32_DMAMUX_BASE 0x40020800 /* 0x40020800-0x40020bff: DMAMUX */ +#define STM32_DMAMUX1_BASE 0x40020800 /* 0x40020800-0x40020bff: DMAMUX */ #define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ #define STM32_EXTI_BASE 0x40021800 /* 0x40021800-0x40021bff: EXTI */ #define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h index 659c9c28d00..940cb9e6ba2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h @@ -202,7 +202,8 @@ /* AHB peripheral reset register */ #define RCC_AHBRSTR_DMA1RST (1 << 0) /* Bit 0: DMA 1 reset */ - /* Bits 1-7: Reserved */ +#define RCC_AHBRSTR_DMA2RST (1 << 1) /* Bit 1: DMA 2 reset */ + /* Bits 2-7: Reserved */ #define RCC_AHBRSTR_MIFRST (1 << 8) /* Bit 8: Memory interface reset */ /* Bits 9-11: Reserved */ #define RCC_AHBRSTR_CRCRST (1 << 12) /* Bit 12: Memory interface reset */ @@ -265,7 +266,8 @@ /* AHB Peripheral Clock enable register */ #define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA 1 enable */ - /* Bits 1-7: Reserved */ +#define RCC_AHBENR_DMA2EN (1 << 1) /* Bit 1: DMA 2 enable */ + /* Bits 2-7: Reserved */ #define RCC_AHBENR_MIFEN (1 << 8) /* Bit 8: Memory interface enable */ /* Bits 9-11: Reserved */ #define RCC_AHBENR_CRCEN (1 << 12) /* Bit 12: Memory interface enable */ @@ -321,7 +323,8 @@ /* AHB peripheral clock enable in Sleep mode register */ #define RCC_AHBSMENR_DMA1SMEN (1 << 0) /* Bit 0: DMA 1 enable in Sleep mode */ - /* Bits 1-7: Reserved */ +#define RCC_AHBSMENR_DMA2SMEN (1 << 1) /* Bit 1: DMA 2 enable in Sleep mode */ + /* Bits 2-7: Reserved */ #define RCC_AHBSMENR_MIFSMEN (1 << 8) /* Bit 8: Memory interface enable in Sleep mode */ /* Bits 9-11: Reserved */ #define RCC_AHBSMENR_CRCSMEN (1 << 12) /* Bit 12: Memory interface enable in Sleep mode */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c index 0d1dc0bd3bb..d597cd60842 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.c @@ -102,23 +102,26 @@ /* Sample time default configuration */ -/* G0 support additional sample time selection 2 */ +/* C0 and G0 support additional sample time selection 2 */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) # define ADC_HAVE_SMPR_SMP2 #endif #if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1) -# ifdef ADC_SMPR_13p5 -# define ADC_SMP1_DEFAULT ADC_SMPR_13p5 -# define ADC_SMP2_DEFAULT ADC_SMPR_13p5 -# else +# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) # define ADC_SMP1_DEFAULT ADC_SMPR_12p5 # define ADC_SMP2_DEFAULT ADC_SMPR_12p5 +# else +# define ADC_SMP1_DEFAULT ADC_SMPR_13p5 # endif #else /* Slow down sampling frequency */ -# define ADC_SMP1_DEFAULT ADC_SMPR_239p5 -# define ADC_SMP2_DEFAULT ADC_SMPR_239p5 +# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +# define ADC_SMP1_DEFAULT ADC_SMPR_160p5 +# define ADC_SMP2_DEFAULT ADC_SMPR_160p5 +# else +# define ADC_SMP1_DEFAULT ADC_SMPR_239p5 +# endif #endif #ifdef ADC_HAVE_SMPR_SMP2 @@ -218,12 +221,14 @@ struct stm32_dev_s uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif #ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME - /* Sample time selection. These bits must be written only when ADON=0. - * REVISIT: this takes too much space. We need only 3 bits per channel. - */ + /* Sample time selection. These bits must be written only when ADON=0. */ - uint8_t sample_rate[ADC_CHANNELS_NUMBER]; - uint8_t adc_channels; /* ADC channels number */ +# ifdef ADC_HAVE_SMPR_SMP2 + uint8_t sample_rate[2]; /* [0] for SMP1, [1] for SMP2 */ + uint32_t smpsel; /* ADC Sample Rate Selection Bits */ +# else + uint8_t sample_rate[1]; /* Only SMP1 is used */ +# endif #endif #ifdef ADC_HAVE_TIMER uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, @@ -1408,6 +1413,10 @@ static void adc_mode_cfg(struct stm32_dev_s *priv) clrbits |= ADC_CFGR1_EXTEN_MASK; setbits |= ADC_CFGR1_EXTEN_NONE; +#ifdef CONFIG_STM32F0L0G0_ADC1_CONTINUOUS + setbits |= ADC_CFGR1_CONT; +#endif + /* Set CFGR configuration */ adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); @@ -1437,8 +1446,33 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) /* Initialize the same sample time for each ADC. * During sample cycles channel selection bits must remain unchanged. */ - #ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME + struct adc_sample_time_s time_samples = { +# ifdef STM32_ADC1_SMPR_SMP1 + .smp1 = STM32_ADC1_SMPR_SMP1, +# else + .smp1 = ADC_SMP1_DEFAULT, +# endif + +# ifdef ADC_HAVE_SMPR_SMP2 +# ifdef STM32_ADC1_SMPR_SMP2 + .smp2 = STM32_ADC1_SMPR_SMP2, +# else + .smp2 = ADC_SMP2_DEFAULT, +# endif + +# ifdef STM32_ADC1_SMPR_SMPSEL + .smpsel = STM32_ADC1_SMPR_SMPSEL +# else + .smpsel = ADC_SMPSEL_DEFAULT +# endif +# else + .smp2 = 0, + .smpsel = 0 +# endif + }; + + adc_sampletime_set((struct stm32_adc_dev_s *)dev, &time_samples); adc_sampletime_write((struct stm32_adc_dev_s *)dev); #else struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1448,7 +1482,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) setbits |= ADC_SMP1_DEFAULT << ADC_SMPR_SMP1_SHIFT; -# ifdef ADC_HAVE_SMPR_SMP2 +#ifdef ADC_HAVE_SMPR_SMP2 /* Configure sample time 2 */ setbits |= ADC_SMP2_DEFAULT << ADC_SMPR_SMP2_SHIFT; @@ -1456,12 +1490,11 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) /* Configure sample time selection */ setbits |= ADC_SMPSEL_DEFAULT << ADC_SMPR_SMPSEL_SHIFT; -# endif +#endif /* Write SMPR register */ adc_putreg(priv, STM32_ADC_SMPR_OFFSET, setbits); - #endif } @@ -1596,7 +1629,7 @@ static void adc_configure(struct adc_dev_s *dev) adc_voltreg_cfg(priv); - /* Calibrate ADC - doesn't work for now */ + /* Calibrate ADC */ adc_calibrate(priv); @@ -2717,6 +2750,7 @@ static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, } #endif /* ADC_HAVE_DMA */ +#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME /**************************************************************************** * Name: adc_sampletime_write * @@ -2729,10 +2763,19 @@ static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME static void adc_sampletime_write(struct stm32_adc_dev_s *dev) { - #error TODO adc_sampletime_write + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t smpr = 0; + + smpr |= ((uint32_t)priv->sample_rate[0] << ADC_SMPR_SMP1_SHIFT); + +#ifdef ADC_HAVE_SMPR_SMP2 + smpr |= ((uint32_t)priv->sample_rate[1] << ADC_SMPR_SMP2_SHIFT); + smpr |= ((uint32_t)priv->smpsel << ADC_SMPR_SMPSEL_SHIFT); +#endif + + adc_putreg(priv, STM32_ADC_SMPR_OFFSET, smpr); } /**************************************************************************** @@ -2756,10 +2799,16 @@ static void adc_sampletime_write(struct stm32_adc_dev_s *dev) * ****************************************************************************/ -void adc_sampletime_set(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples) +static void adc_sampletime_set(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples) { - #error TODO adc_sampletime_write + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + priv->sample_rate[0] = time_samples->smp1; +#ifdef ADC_HAVE_SMPR_SMP2 + priv->sample_rate[1] = time_samples->smp2; + priv->smpsel = time_samples->smpsel; +#endif } #endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h index 23cb4b01842..89ac9b8da5d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.h @@ -326,30 +326,11 @@ enum stm32_adc_resoluton_e #ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME -/* Channel and sample time pair */ - -typedef struct adc_channel_s -{ - uint8_t channel:5; - - /* Sampling time individually for each channel. - * It differs between families - */ - - uint8_t sample_time:3; -} adc_channel_t; - -/* This structure will be used while setting channels to specified by the - * "channel-sample time" pairs' values - */ - struct adc_sample_time_s { - adc_channel_t *channel; /* Array of channels */ - uint8_t channels_nbr:5; /* Number of channels in array */ - bool all_same:1; /* All channels will get the - * same value of the sample time */ - uint8_t all_ch_sample_time:3; /* Sample time for all channels */ + uint8_t smp1; /* Sample time for channels with SMPSEL bit = 0 */ + uint8_t smp2; /* Sample time for channels with SMPSEL bit = 1 */ + uint32_t smpsel; /* Bitmask for selecting which channels use SMP2 */ }; #endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c index 2f354348ba5..460a84fc6e4 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c @@ -51,11 +51,23 @@ #define DMA_CONTROLLERS 2 #ifdef CONFIG_STM32F0L0G0_DMA1 -# if defined(CONFIG_ARCH_CHIP_STM32C0) +# if defined(CONFIG_ARCH_CHIP_STM32C0) || \ + defined(CONFIG_STM32F0L0G0_STM32G03X) || \ + defined(CONFIG_STM32F0L0G0_STM32G041) # define DMA1_NCHAN 5 # define DMA2_NCHAN 0 +# elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ + defined(CONFIG_STM32F0L0G0_STM32G061) || \ + defined(CONFIG_STM32F0L0G0_STM32G07X) || \ + defined(CONFIG_STM32F0L0G0_STM32G081) +# define DMA1_NCHAN 7 +# define DMA2_NCHAN 0 +# elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ + defined(CONFIG_STM32F0L0G0_STM32G0C1) +# define DMA1_NCHAN 7 +# define DMA2_NCHAN 5 # else -# error +# error "Unsupported STM32F0L0G0 subfamily" # endif #else # define DMA1_NCHAN 0 @@ -73,10 +85,20 @@ /* DMAMUX channels */ -#if defined(CONFIG_ARCH_CHIP_STM32C0) +#if defined(CONFIG_ARCH_CHIP_STM32C0) || \ + defined(CONFIG_STM32F0L0G0_STM32G03X) || \ + defined(CONFIG_STM32F0L0G0_STM32G041) # define DMAMUX_NCHANNELS 5 +#elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ + defined(CONFIG_STM32F0L0G0_STM32G061) || \ + defined(CONFIG_STM32F0L0G0_STM32G07X) || \ + defined(CONFIG_STM32F0L0G0_STM32G081) +# define DMAMUX_NCHANNELS 7 +#elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ + defined(CONFIG_STM32F0L0G0_STM32G0C1) +# define DMAMUX_NCHANNELS 12 #else -# error +# error "Unknown chip for DMAMUX channel count" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c index 18e34d9c557..ca15e3a737c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c @@ -125,6 +125,12 @@ static inline void rcc_enableahb(void) regval |= RCC_AHBENR_DMA1EN; #endif +#ifdef CONFIG_STM32F0L0G0_DMA2 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA2EN; +#endif + #ifdef CONFIG_STM32F0L0G0_MIF /* Memory interface clock enable */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig new file mode 100644 index 00000000000..9e314201850 --- /dev/null +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=64 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g0b1re" +CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y +CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_CHIP_STM32G0B1RE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=4164 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_NSAMPLES=1 +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=147456 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32F0L0G0_ADC1=y +CONFIG_STM32F0L0G0_ADC1_CONTINUOUS=y +CONFIG_STM32F0L0G0_ADC1_DMA=y +CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 +CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32F0L0G0_ADC_LL_OPS=y +CONFIG_STM32F0L0G0_ADC_OVERSAMPLE=y +CONFIG_STM32F0L0G0_ADC_OVSR=7 +CONFIG_STM32F0L0G0_ADC_OVSS=4 +CONFIG_STM32F0L0G0_DMA1=y +CONFIG_STM32F0L0G0_PWR=y +CONFIG_STM32F0L0G0_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h b/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h index eb7ddb5c28f..1e81287481c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h @@ -210,12 +210,15 @@ /* ADC */ -#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_A0 GPIO_ADC1_IN0_1 +#define GPIO_ADC1_A1 GPIO_ADC1_IN1_1 +#define GPIO_ADC1_A2 GPIO_ADC1_IN4_1 +#define GPIO_ADC1_A3 GPIO_ADC1_IN9_1 /* DMA channels *************************************************************/ /* ADC */ -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ +#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 #endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c index aed55de1d91..e2d73a3d207 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c @@ -46,7 +46,7 @@ /* The number of ADC channels in the conversion list */ -#define ADC1_NCHANNELS 1 +#define ADC1_NCHANNELS 4 /**************************************************************************** * Private Function Prototypes @@ -58,16 +58,22 @@ /* Identifying number of each ADC channel (even if NCHANNELS is less ) */ -static const uint8_t g_chanlist1[1] = +static const uint8_t g_chanlist1[ADC1_NCHANNELS] = { - 0 + 0, + 1, + 4, + 9 }; /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist1[1] = +static const uint32_t g_pinlist1[ADC1_NCHANNELS] = { - GPIO_ADC1_IN0 + GPIO_ADC1_A0, + GPIO_ADC1_A1, + GPIO_ADC1_A2, + GPIO_ADC1_A3 }; /****************************************************************************