From 04a66d2d3aaa8608d61e6ee79f5205791471b862 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 17 Nov 2022 10:58:42 +0100 Subject: [PATCH] arch/stm32g4: fix ADC clock after ef517ed --- arch/arm/src/stm32/stm32g4xxxx_rcc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/src/stm32/stm32g4xxxx_rcc.c b/arch/arm/src/stm32/stm32g4xxxx_rcc.c index 4f12436937c..35a029b0b3c 100644 --- a/arch/arm/src/stm32/stm32g4xxxx_rcc.c +++ b/arch/arm/src/stm32/stm32g4xxxx_rcc.c @@ -961,6 +961,25 @@ static void stm32_stdclockconfig(void) regval |= STM32_CCIPR_FDCANSRC; putreg32(regval, STM32_RCC_CCIPR); #endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) + /* Configure ADC12 clock */ + + regval = getreg32(STM32_RCC_CCIPR); + regval &= ~RCC_CCIPR_ADC12SEL_MASK; + regval |= RCC_CCIPR_ADC12SEL_PLLP; + putreg32(regval, STM32_RCC_CCIPR); +#endif + +#if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) || \ + defined(CONFIG_STM32_ADC5) + /* Configure ADC345 clock */ + + regval = getreg32(STM32_RCC_CCIPR); + regval &= ~RCC_CCIPR_ADC345SEL_MASK; + regval |= RCC_CCIPR_ADC345SEL_PLLP; + putreg32(regval, STM32_RCC_CCIPR); +#endif } /****************************************************************************