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riscv_vector.S: Align trap vector to 64 byte

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Bump align to 64 byte to support all interrupt mode, it is essential for CLIC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2024-06-17 19:49:54 +08:00 • committed by Xiang Xiao
parent 384610b253
commit 040e1379cd
1 changed files with 3 additions and 1 deletions
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4
arch/risc-v/src/common/riscv_vectors.S
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@ -23,7 +23,7 @@
****************************************************************************/
.section .text
.balign 8
.balign 64
.global __trap_vec
/****************************************************************************
@ -32,6 +32,8 @@
* Description:
* All M-mode exceptions and interrupts will be handled from here. If
* kernel is in S-mode delegated exceptions and interrupts are handled.
* Bump align to 64 byte to support all interrupt mode (PLIC/CLINT/CLIC)
* since 64 byte align is essential for CLIC.
*
****************************************************************************/