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arm64/imx9: Support & configure RGMII-ID on RTL8211F
For the RTL8211F PHY, configuration of RX/TXDLY was missing. At least on my i.MX93 EVK, this is necessary for transmission to work (RXDLY defaults to true on the PHY). This commit brings support for RGMII internal delay configuration (on or off for both directions) and enables it on the i.MX93 EVK board. The introduced Kconfig is set to default to 'n', to avoid breaking the functionality of other, out-of-tree boards based on i.MX93, running the RTL8211F PHY, or to avoid introducing unnecessary code on boards running other PHYs. Configuration of internal delay on other PHYs is not implemented, and results in a warning (but no error). Signed-off-by: George Poulios <gpoulios@census-labs.com>
This commit is contained in:
George Poulios
Xiang Xiao
parent
e540fae8b3
commit
03f7f59fa8
6 changed files with 134 additions and 1 deletions
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@ -1003,6 +1003,21 @@ config IMX9_ENET1_RGMII
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endchoice
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if IMX9_ENET1_RGMII
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config IMX9_ENET1_RGMII_ID
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bool "Enable the PHY internal delay on both TX & RX signals"
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default n
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depends on IMX9_ENET1_RGMII
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---help---
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In RGMII-ID mode, the PHY introduces an internal delay eliminating
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the need for a timing skew between the data and clock signals otherwise
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generated by the PCB design. This is currently only implemented for the
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RTL8211F chip; enabling or disabling it on any other PHYs will not make
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any difference.
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endif # IMX9_ENET1_RGMII
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config IMX9_ENET1_TX_CLOCK_IS_INPUT
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bool "ENET1 TX clock is input"
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default y if IMX9_ENET1_RMII
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@ -277,6 +277,11 @@ static int imx9_writemii(struct imx9_driver_s *priv, uint8_t regaddr,
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uint16_t data);
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static int imx9_readmii(struct imx9_driver_s *priv, uint8_t regaddr,
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uint16_t *data);
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#ifdef CONFIG_IMX9_ENET1_RGMII
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static int imx9_config_rgmii_id(struct imx9_driver_s *priv);
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#else
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# define imx9_config_rgmii_id(priv) (OK)
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#endif
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static int imx9_initphy(struct imx9_driver_s *priv, bool renogphy);
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static int imx9_readmmd(struct imx9_driver_s *priv, uint8_t mmd,
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@ -2677,6 +2682,102 @@ static int imx9_phy_wait_autoneg_complete(struct imx9_driver_s *priv)
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return imx9_read_phy_status(priv);
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}
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/****************************************************************************
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* Function: imx9_config_rgmii_id
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*
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* Description:
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* Configure the PHY internal delay. Currently only supported on RTL8211F.
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* If CONFIG_IMX9_ENET1_RGMII_ID is set, this function sets both TXDLY
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* and RXDLY bit on MIICR1 and MIICR2 respectively. Otherwise, it clears
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* the respective bits.
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*
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* Input Parameters:
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* priv - Reference to the private ENET driver state structure
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*
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* Returned Value:
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* Zero (OK) returned on success; a negated errno value is returned on any
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* failure;
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*
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****************************************************************************/
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#ifdef CONFIG_IMX9_ENET1_RGMII
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static int imx9_config_rgmii_id(struct imx9_driver_s *priv)
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{
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int ret;
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uint16_t prev_page;
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uint16_t reg;
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if (!imx9_phy_is(priv, GMII_RTL8211F_NAME))
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{
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nwarn("WARN: not configuring RGMII Internal Delay on %s phy\n",
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priv->cur_phy->name);
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return OK;
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}
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ret = imx9_readmii(priv, GMII_RTL8211F_PAGSR, &prev_page);
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if (ret < 0)
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{
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nerr("ERROR: Getting page, imx9_readmii failed: %d\n", ret);
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goto errout;
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}
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ret = imx9_writemii(priv, GMII_RTL8211F_PAGSR, 0xd08);
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if (ret < 0)
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{
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nerr("ERROR: Selecting page, imx9_writemii failed: %d\n", ret);
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goto errout;
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}
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ret = imx9_readmii(priv, GMII_RTL8211F_MIICR1_D08, ®);
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if (ret < 0)
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{
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nerr("ERROR: Reading MIICR1, imx9_readmii failed: %d\n", ret);
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goto errout;
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}
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#ifdef CONFIG_IMX9_ENET1_RGMII_ID
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reg |= GMII_RTL8211F_MIICR1_TX_DELAY;
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#else
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reg &= ~GMII_RTL8211F_MIICR1_TX_DELAY;
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#endif
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ret = imx9_writemii(priv, GMII_RTL8211F_MIICR1_D08, reg);
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if (ret < 0)
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{
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nerr("ERROR: Enabling TXDLY, imx9_writemii failed: %d\n", ret);
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goto errout;
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}
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ret = imx9_readmii(priv, GMII_RTL8211F_MIICR2_D08, ®);
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if (ret < 0)
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{
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nerr("ERROR: Reading MIICR2, imx9_readmii failed: %d\n", ret);
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goto errout;
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}
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#ifdef CONFIG_IMX9_ENET1_RGMII_ID
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reg |= GMII_RTL8211F_MIICR2_RX_DELAY;
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#else
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reg &= ~GMII_RTL8211F_MIICR2_RX_DELAY;
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#endif
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ret = imx9_writemii(priv, GMII_RTL8211F_MIICR2_D08, reg);
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if (ret < 0)
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{
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nerr("ERROR: Enabling RXDLY, imx9_writemii failed: %d\n", ret);
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goto errout;
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}
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ret = imx9_writemii(priv, GMII_RTL8211F_PAGSR, prev_page);
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if (ret < 0)
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{
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nerr("ERROR: Restoring page, imx9_writemii failed: %d\n", ret);
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goto errout;
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}
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errout:
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return ret;
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}
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#endif /* CONFIG_IMX9_ENET1_RGMII */
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/****************************************************************************
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* Function: imx9_initphy
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*
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@ -2897,6 +2998,17 @@ static inline int imx9_initphy(struct imx9_driver_s *priv, bool renogphy)
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imx9_enet_putreg32(priv, rcr, IMX9_ENET_RCR_OFFSET);
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imx9_enet_putreg32(priv, tcr, IMX9_ENET_TCR_OFFSET);
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if (priv->phy_type == PHY_RGMII)
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{
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ret = imx9_config_rgmii_id(priv);
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if (ret < 0)
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{
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nerr("ERROR: configure internal delay failed: %d\n", ret);
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return ret;
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}
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}
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return OK;
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}
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@ -68,6 +68,7 @@ CONFIG_IMX9_DMA_ALLOC=y
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CONFIG_IMX9_DMA_ALLOC_POOL_SIZE=81920
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CONFIG_IMX9_EDMA=y
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CONFIG_IMX9_ENET1_RGMII=y
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CONFIG_IMX9_ENET1_RGMII_ID=y
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CONFIG_IMX9_ENET=y
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CONFIG_IMX9_ENET_USE_OTP_MAC=y
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CONFIG_IMX9_FLEXIO1_PWM=y
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@ -73,6 +73,7 @@ CONFIG_IMX9_DMA_ALLOC=y
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CONFIG_IMX9_DMA_ALLOC_POOL_SIZE=81920
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CONFIG_IMX9_EDMA=y
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CONFIG_IMX9_ENET1_RGMII=y
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CONFIG_IMX9_ENET1_RGMII_ID=y
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CONFIG_IMX9_ENET=y
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CONFIG_IMX9_ENET_USE_OTP_MAC=y
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CONFIG_IMX9_FLEXIO1_PWM=y
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@ -46,6 +46,7 @@ CONFIG_IMX9_DMA_ALLOC=y
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CONFIG_IMX9_DMA_ALLOC_POOL_SIZE=81920
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CONFIG_IMX9_EDMA=y
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CONFIG_IMX9_ENET1_RGMII=y
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CONFIG_IMX9_ENET1_RGMII_ID=y
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CONFIG_IMX9_ENET=y
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CONFIG_IMX9_ENET_USE_OTP_MAC=y
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CONFIG_IMX9_FLEXIO1_PWM=y
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@ -94,7 +94,8 @@
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#define GMII_RTL8211F_PHYSCR_A46 20 /* PHY Special Config Register */
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#define GMII_RTL8211F_LCR_D04 16 /* LED Control Register */
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#define GMII_RTL8211F_EEELCR_D04 17 /* EEE LED Control Register */
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#define GMII_RTL8211F_MIICR_D08 21 /* MII Control Register */
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#define GMII_RTL8211F_MIICR1_D08 17 /* MII Control Register 1 */
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#define GMII_RTL8211F_MIICR2_D08 21 /* MII Control Register 2 */
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#define GMII_RTL8211F_INTBCR_D40 22 /* INTB Pin Control Register */
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/* MII register bit settings ************************************************/
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@ -308,6 +309,8 @@
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#define GMII_RTL8211F_PHYSR_100MBPS 0x10
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#define GMII_RTL8211F_PHYSR_1000MBPS 0x20
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#define GMII_RTL8211F_PHYSR_DUPLEX 0x8
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#define GMII_RTL8211F_MIICR1_TX_DELAY (1 << 8) /* Enable PHY internal TX delay */
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#define GMII_RTL8211F_MIICR2_RX_DELAY (1 << 3) /* Enable PHY internal RX delay */
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/****************************************************************************
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* Type Definitions
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