From 0332b78f9942fc4e012fc50bc363afbc941efff2 Mon Sep 17 00:00:00 2001
From: Huang Qi <huangqi3@xiaomi.com>
Date: Thu, 21 Apr 2022 12:23:18 +0800
Subject: [PATCH] arch/risc-v: Don't clear reserved bits in fcsr in
 riscv_fpuconfig

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
---
 arch/risc-v/src/common/riscv_fpu.S | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/risc-v/src/common/riscv_fpu.S b/arch/risc-v/src/common/riscv_fpu.S
index 3eae438f592..84989ccbf3a 100644
--- a/arch/risc-v/src/common/riscv_fpu.S
+++ b/arch/risc-v/src/common/riscv_fpu.S
@@ -64,7 +64,11 @@
 riscv_fpuconfig:
     li           a0, MSTATUS_FS_INIT
     csrs         CSR_STATUS, a0
-    csrwi        fcsr, 0
+
+    fsflags      zero
+    fsrm         zero
+
+    fence.i
     ret
 
 #endif /* CONFIG_ARCH_FPU */