nuttx/boards/xtensa/esp32/common/scripts/kernel-space.ld

611 lines
22 KiB
Text
Raw Normal View History

/****************************************************************************
* boards/xtensa/esp32/common/scripts/kernel-space.ld
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
xtensa/esp32: Let a protected build boot from simple boot. A protected build on the ESP32 could only use the legacy IDF image format. Kconfig allowed simple boot to be selected with BUILD_PROTECTED, because the legacy format is only a default and not a select, but the result did not link and then did not boot. Simple boot has no second-stage bootloader. __start() maps the flash itself, so everything it reaches must already be in RAM. kernel-space.ld pinned none of it, and it did not place esp32_start at all, so the entry point went to the flash the code was about to map. The chip loaded the RAM segments, jumped to 0x400d0ba4 and took an IllegalInstruction on the first instruction. So this pins the bootloader, flash, ROM, clock and log objects that bootloader_init() and map_rom_segments() reach, along with esp32_start itself, and defines the six _image_* symbols that __start() needs. All of it is behind CONFIG_ESPRESSIF_SIMPLE_BOOT, so a legacy build gets the same IRAM it had before. kernel-space.ld also had no `#include <nuttx/config.h>'. It held no conditionals until now, so nothing showed the omission: the new blocks compiled away silently and the link failed as if the file had not been changed. The default is unchanged. A protected build still selects the legacy format unless the user clears CONFIG_ESP32_APP_FORMAT_LEGACY. Verified on an ESP32-DevKitC V4, ESP32-D0WD-V3 revision 3.1, with esp32-devkitc:knsh and the legacy format turned off. The kernel flashes at 0x1000 and the user image at 0x90000, with no bootloader and no partition table. It maps seven segments, reaches NSH, and runs ostest to the same point as the legacy build. Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
2026-08-11 11:13:02 +02:00
#include <nuttx/config.h>
/* Provide these so there is no need for using config files for this */
__uirom_start = ORIGIN(UIROM);
__uirom_size = LENGTH(UIROM);
__uirom_end = ORIGIN(UIROM) + LENGTH(UIROM);
__udrom_start = ORIGIN(UDROM);
__udrom_size = LENGTH(UDROM);
__udrom_end = ORIGIN(UDROM) + LENGTH(UDROM);
__uiram_start = ORIGIN(UIRAM);
__uiram_size = LENGTH(UIRAM);
__uiram_end = ORIGIN(UIRAM) + LENGTH(UIRAM);
__udram_start = ORIGIN(UDRAM);
__udram_size = LENGTH(UDRAM);
__udram_end = ORIGIN(UDRAM) + LENGTH(UDRAM);
/* Provide the kernel boundaries as well */
__kirom_start = ORIGIN(KIROM);
__kirom_size = LENGTH(KIROM);
__kdrom_start = ORIGIN(KDROM);
__kdrom_size = LENGTH(KDROM);
__kdrom_start = ORIGIN(KDROM);
__kdrom_size = LENGTH(KDROM);
__kiram_0_start = ORIGIN(KIRAM_0);
__kiram_0_size = LENGTH(KIRAM_0);
__kiram_0_end = ORIGIN(KIRAM_0) + LENGTH(KIRAM_0);
__kiram_1_start = ORIGIN(KIRAM_1);
__kiram_1_size = LENGTH(KIRAM_1);
__kiram_1_end = ORIGIN(KIRAM_1) + LENGTH(KIRAM_1);
__kdram_0_start = ORIGIN(KDRAM_0);
__kdram_0_size = LENGTH(KDRAM_0);
__kdram_0_end = ORIGIN(KDRAM_0) + LENGTH(KDRAM_0);
__kdram_1_start = ORIGIN(KDRAM_1);
__kdram_1_size = LENGTH(KDRAM_1);
__kdram_1_end = ORIGIN(KDRAM_1) + LENGTH(KDRAM_1);
/* Heap ends at top of dram0_0_seg */
_eheap = 0x40000000;
ENTRY(_stext)
SECTIONS
{
/* Send .iram0 code to iram */
.iram0.vectors :
{
/* Vectors go to IRAM */
_init_start = ABSOLUTE(.);
__vectors_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN (16);
__vectors_end = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} >KIRAM_0
.iram0.text :
{
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
*librtc.a:(.literal .text .literal.* .text.*)
*libkarch.a:esp_spiflash.*(.literal .text .literal.* .text.*)
*libkarch.a:*esp_clk.*(.text .text.* .literal .literal.*)
*libkarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
*libkarch.a:xtensa_copystate.*(.literal .text .literal.* .text.*)
*libkarch.a:xtensa_interruptcontext.*(.literal .text .literal.* .text.*)
*libkarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
*libkarch.a:esp_app_desc.*(.literal .text .literal.* .text.*)
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
*libc.a:arch_atomic.*(.literal .text .literal.* .text.*)
*libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
*libsched.a:sched_note.*(.literal .text .literal.* .text.*)
*libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
*libsched.a:spinlock.*(.literal .text .literal.* .text.*)
*libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
*libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
*libkarch.a:esp_spiflash.*(.literal .text .literal.* .text.*)
*libkarch.a:esp_flash_api.*(.text .text.* .literal .literal.*)
*libkarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*)
*libkarch.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_encrypt_hal_iram.*(.text .text.* .literal .literal.*)
*libkarch.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_chip*.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*)
*libkarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*)
*libkarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*)
*libkarch.a:cache_esp32.*(.literal .literal.* .text .text.*)
*libkarch.a:cache_hal_esp32.*(.literal .literal.* .text .text.*)
*libkarch.a:cache_utils.*(.literal .literal.* .text .text.*)
*libkarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*)
*libkarch.a:critical_section.*(.literal .literal.* .text .text.*)
*libkarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical)
*libkarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical)
*libkarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno)
*libkarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu)
*libkarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get)
*libkarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg)
*libkarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item)
*libkarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg)
xtensa/esp32: Let a protected build boot from simple boot. A protected build on the ESP32 could only use the legacy IDF image format. Kconfig allowed simple boot to be selected with BUILD_PROTECTED, because the legacy format is only a default and not a select, but the result did not link and then did not boot. Simple boot has no second-stage bootloader. __start() maps the flash itself, so everything it reaches must already be in RAM. kernel-space.ld pinned none of it, and it did not place esp32_start at all, so the entry point went to the flash the code was about to map. The chip loaded the RAM segments, jumped to 0x400d0ba4 and took an IllegalInstruction on the first instruction. So this pins the bootloader, flash, ROM, clock and log objects that bootloader_init() and map_rom_segments() reach, along with esp32_start itself, and defines the six _image_* symbols that __start() needs. All of it is behind CONFIG_ESPRESSIF_SIMPLE_BOOT, so a legacy build gets the same IRAM it had before. kernel-space.ld also had no `#include <nuttx/config.h>'. It held no conditionals until now, so nothing showed the omission: the new blocks compiled away silently and the link failed as if the file had not been changed. The default is unchanged. A protected build still selects the legacy format unless the user clears CONFIG_ESP32_APP_FORMAT_LEGACY. Verified on an ESP32-DevKitC V4, ESP32-D0WD-V3 revision 3.1, with esp32-devkitc:knsh and the legacy format turned off. The kernel flashes at 0x1000 and the user image at 0x90000, with no bootloader and no partition table. It maps seven segments, reaches NSH, and runs ostest to the same point as the legacy build. Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
2026-08-11 11:13:02 +02:00
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
/* Simple boot has no second-stage bootloader. __start() runs
* bootloader_init() and map_rom_segments() before any flash mapping
* exists, so everything they reach must be resident in RAM.
*/
/* __start() itself runs before the mapping it creates, so it cannot
* live in the flash it is about to map.
*/
esp32_start.*(.literal .text .literal.* .text.*)
*libkarch.a:*esp_loader.*(.literal .text .literal.* .text.*)
*libkarch.a:*bootloader_init.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_common.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_console.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_esp32.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_flash_config_esp32.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_random.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_random_esp32.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*)
*libkarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_image_format.*(.text .text.* .literal .literal.*)
*libkarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*)
*libkarch.a:*flash_qio_mode.*(.text .text.* .literal .literal.*)
*libkarch.a:*brownout_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*cpu.*(.text .text.* .literal .literal.*)
*libkarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
*libkarch.a:*gpio_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*)
*libkarch.a:*clk.*(.text .text.* .literal .literal.*)
*libkarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*)
*libkarch.a:*rtc_init.*(.text .text.* .literal .literal.*)
*libkarch.a:*rtc_clk.*(.text .text.* .literal .literal.*)
*libkarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*)
*libkarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*)
*libkarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
*libkarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
*libkarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*efuse_utility.*(.text .text.* .literal .literal.*)
*libkarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*cache_esp32.*(.text .text.* .literal .literal.*)
*libkarch.a:*cache_hal_esp32.*(.text .text.* .literal .literal.*)
*libkarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libkarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
*libkarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
*libkarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*)
*libkarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*)
*libkarch.a:*log.*(.text .text.* .literal .literal.*)
*libkarch.a:*log_lock.*(.literal .literal.* .text .text.*)
*libkarch.a:*log_print.*(.literal .literal.* .text .text.*)
*libkarch.a:*log_timestamp.*(.literal .literal.* .text .text.*)
*libkarch.a:*log_timestamp_common.*(.literal .literal.* .text .text.*)
*libkarch.a:*log_write.*(.literal .literal.* .text .text.*)
*libkarch.a:esp_app_desc.*(.literal .literal.* .text .text.*)
*libkarch.a:esp_flash_api.*(.text .text.* .literal .literal.*)
*libkarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*)
*libkarch.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_encrypt_hal_iram.*(.text .text.* .literal .literal.*)
*libkarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*)
*libkarch.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
#endif
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.phyiram .phyiram.*)
_iram_text_end = ABSOLUTE(.);
/* IRAM heap starts at the end of iram0_0_seg */
. = ALIGN (4);
_siramheap = ABSOLUTE(.);
} >KIRAM_1
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
/* .bss initialized on power-up */
. = ALIGN (8);
_sbss = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.ext_ram.bss*)
_bt_bss_start = ABSOLUTE(.);
*libbt.a:(.bss .bss.* COMMON)
. = ALIGN (4);
_bt_bss_end = ABSOLUTE(.);
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN (4);
_btdm_bss_end = ABSOLUTE(.);
. = ALIGN (8);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
KEEP (*(.bss))
*(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
*libkarch.a:esp_spiflash.*(.bss .bss.* COMMON)
*libkarch.a:xtensa_cpupause.*(.bss .bss.* COMMON)
*libkarch.a:xtensa_copystate.*(.bss .bss.* COMMON)
*libkarch.a:xtensa_interruptcontext.*(.bss .bss.* COMMON)
*libkarch.a:xtensa_testset.*(.bss .bss.* COMMON)
*libsched.a:sched_suspendscheduler.*(.bss .bss.* COMMON)
*libsched.a:sched_thistask.*(.bss .bss.* COMMON)
*libsched.a:sched_note.*(.bss .bss.* COMMON)
*libsched.a:spinlock.*(.bss .bss.* COMMON)
*libsched.a:irq_csection.*(.bss .bss.* COMMON)
*libsched.a:irq_dispatch.*(.bss .bss.* COMMON)
. = ALIGN(8);
_bss_end = ABSOLUTE(.);
_ebss = ABSOLUTE(.);
} >KDRAM_0
.noinit (NOLOAD):
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
*(.noinit)
} >KDRAM_0
.dram0.data :
{
/* .data initialized on power-up in ROMed configurations. */
_sdata = ABSOLUTE(.);
_bt_data_start = ABSOLUTE(.);
*libbt.a:(.data .data.*)
. = ALIGN (4);
_bt_data_end = ABSOLUTE(.);
_btdm_data_start = ABSOLUTE(.);
*libbtdm_app.a:(.data .data.*)
. = ALIGN (4);
_btdm_data_end = ABSOLUTE(.);
KEEP (*(.data))
KEEP (*(.data.*))
KEEP (*(.gnu.linkonce.d.*))
KEEP (*(.data1))
KEEP (*(.sdata))
KEEP (*(.sdata.*))
KEEP (*(.gnu.linkonce.s.*))
KEEP (*(.sdata2))
KEEP (*(.sdata2.*))
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
*libphy.a:(.rodata .rodata.*)
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
*libkarch.a:esp_cache_utils.*(.rodata .rodata.*)
*libkarch.a:esp_spiflash.*(.rodata .rodata.*)
*libkarch.a:*esp_clk.*(.rodata .rodata.*)
*libkarch.a:xtensa_cpupause.*(.rodata .rodata.*)
*libkarch.a:xtensa_copystate.*(.rodata .rodata.*)
*libkarch.a:xtensa_interruptcontext.*(.rodata .rodata.*)
*libkarch.a:xtensa_testset.*(.rodata .rodata.*)
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
*libkarch.a:spi_flash_chip*.*(.rodata .rodata.*)
*libkarch.a:critical_section.*(.rodata .rodata.*)
*libkarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags)
*libkc.a:arch_atomic.*(.rodata .rodata.*)
xtensa/esp32: Let a protected build boot from simple boot. A protected build on the ESP32 could only use the legacy IDF image format. Kconfig allowed simple boot to be selected with BUILD_PROTECTED, because the legacy format is only a default and not a select, but the result did not link and then did not boot. Simple boot has no second-stage bootloader. __start() maps the flash itself, so everything it reaches must already be in RAM. kernel-space.ld pinned none of it, and it did not place esp32_start at all, so the entry point went to the flash the code was about to map. The chip loaded the RAM segments, jumped to 0x400d0ba4 and took an IllegalInstruction on the first instruction. So this pins the bootloader, flash, ROM, clock and log objects that bootloader_init() and map_rom_segments() reach, along with esp32_start itself, and defines the six _image_* symbols that __start() needs. All of it is behind CONFIG_ESPRESSIF_SIMPLE_BOOT, so a legacy build gets the same IRAM it had before. kernel-space.ld also had no `#include <nuttx/config.h>'. It held no conditionals until now, so nothing showed the omission: the new blocks compiled away silently and the link failed as if the file had not been changed. The default is unchanged. A protected build still selects the legacy format unless the user clears CONFIG_ESP32_APP_FORMAT_LEGACY. Verified on an ESP32-DevKitC V4, ESP32-D0WD-V3 revision 3.1, with esp32-devkitc:knsh and the legacy format turned off. The kernel flashes at 0x1000 and the user image at 0x90000, with no bootloader and no partition table. It maps seven segments, reaches NSH, and runs ostest to the same point as the legacy build. Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
2026-08-11 11:13:02 +02:00
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
/* The read-only data of everything pinned into IRAM above. */
esp32_start.*(.rodata .rodata.*)
*libkarch.a:*esp_loader.*(.rodata .rodata.*)
*libkarch.a:*bootloader_init.*(.rodata .rodata.*)
*libkarch.a:*bootloader_common.*(.rodata .rodata.*)
*libkarch.a:*bootloader_common_loader.*(.rodata .rodata.*)
*libkarch.a:*bootloader_console.*(.rodata .rodata.*)
*libkarch.a:*bootloader_console_loader.*(.rodata .rodata.*)
*libkarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*)
*libkarch.a:*bootloader_clock_init.*(.rodata .rodata.*)
*libkarch.a:*bootloader_clock_loader.*(.rodata .rodata.*)
*libkarch.a:*bootloader_efuse.*(.rodata .rodata.*)
*libkarch.a:*bootloader_esp32.*(.rodata .rodata.*)
*libkarch.a:*bootloader_flash.*(.rodata .rodata.*)
*libkarch.a:*bootloader_flash_config_esp32.*(.rodata .rodata.*)
*libkarch.a:*bootloader_mem.*(.rodata .rodata.*)
*libkarch.a:*bootloader_panic.*(.rodata .rodata.*)
*libkarch.a:*bootloader_random.*(.rodata .rodata.*)
*libkarch.a:*bootloader_random_esp32.*(.rodata .rodata.*)
*libkarch.a:*bootloader_sha.*(.rodata .rodata.*)
*libkarch.a:*bootloader_soc.*(.rodata .rodata.*)
*libkarch.a:*esp_image_format.*(.rodata .rodata.*)
*libkarch.a:*flash_encrypt.*(.rodata .rodata.*)
*libkarch.a:*flash_qio_mode.*(.rodata .rodata.*)
*libkarch.a:*brownout_hal.*(.rodata .rodata.*)
*libkarch.a:*cpu.*(.rodata .rodata.*)
*libkarch.a:*cpu_region_protect.*(.rodata .rodata.*)
*libkarch.a:*gpio_hal.*(.rodata .rodata.*)
*libkarch.a:*periph_ctrl.*(.rodata .rodata.*)
*libkarch.a:*clk.*(.rodata .rodata.*)
*libkarch.a:*clk_tree_hal.*(.rodata .rodata.*)
*libkarch.a:*esp_clk_tree.*(.rodata .rodata.*)
*libkarch.a:*esp_clk_tree_common.*(.rodata .rodata.*)
*libkarch.a:*rtc_init.*(.rodata .rodata.*)
*libkarch.a:*rtc_clk.*(.rodata .rodata.*)
*libkarch.a:*rtc_clk_init.*(.rodata .rodata.*)
*libkarch.a:*rtc_time.*(.rodata .rodata.*)
*libkarch.a:*regi2c_ctrl.*(.rodata .rodata.*)
*libkarch.a:*efuse_hal.*(.rodata .rodata.*)
*libkarch.a:*efuse_utility.*(.rodata .rodata.*)
*libkarch.a:*mmu_hal.*(.rodata .rodata.*)
*libkarch.a:*mpu_hal.*(.rodata .rodata.*)
*libkarch.a:*cache_esp32.*(.rodata .rodata.*)
*libkarch.a:*cache_hal_esp32.*(.rodata .rodata.*)
*libkarch.a:*uart_hal.*(.rodata .rodata.*)
*libkarch.a:*uart_hal_iram.*(.rodata .rodata.*)
*libkarch.a:*uart_periph.*(.rodata .rodata.*)
*libkarch.a:*wdt_hal_iram.*(.rodata .rodata.*)
*libkarch.a:*esp_rom_uart.*(.rodata .rodata.*)
*libkarch.a:*esp_rom_sys.*(.rodata .rodata.*)
*libkarch.a:*esp_rom_spiflash.*(.rodata .rodata.*)
*libkarch.a:*esp_rom_wdt.*(.rodata .rodata.*)
*libkarch.a:*log.*(.rodata .rodata.*)
*libkarch.a:esp_app_desc.*(.rodata .rodata.*)
*libkarch.a:esp_flash_api.*(.rodata .rodata.*)
*libkarch.a:esp_flash_spi_init.*(.rodata .rodata.*)
#endif
*libsched.a:sched_suspendscheduler.*(.rodata .rodata.*)
*libsched.a:sched_thistask.*(.rodata .rodata.*)
*libsched.a:sched_note.*(.rodata .rodata.*)
*libsched.a:spinlock.*(.rodata .rodata.*)
*libsched.a:irq_csection.*(.rodata .rodata.*)
*libsched.a:irq_dispatch.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} >KDRAM_0
.flash.rodata :
{
_srodata = ABSOLUTE(.);_rodata_reserved_start = ABSOLUTE(.);
_srodata = ABSOLUTE(.);
/* !DO NOT PUT ANYTHING BEFORE THIS! */
/* Should be the first. App version info. */
*(.rodata_desc .rodata_desc.*)
*(.rodata)
*(.rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
/* C++ constructor tables. Those are initialized by lib_cxx_initialize
* which calls constructor functions that may be on common source code.
*/
. = ALIGN(4);
_sinit = ABSOLUTE(.);
__init_array_start = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))
__init_array_end = ABSOLUTE(.);
_einit = ABSOLUTE(.);
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
. = ALIGN(4);
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
/* System init functions registered via ESP_SYSTEM_INIT_FN */
. = ALIGN(4);
_esp_system_init_fn_array_start = ABSOLUTE(.);
KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
. = ALIGN(4);
} >KDROM
.flash.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >KIROM
xtensa/esp32: Let a protected build boot from simple boot. A protected build on the ESP32 could only use the legacy IDF image format. Kconfig allowed simple boot to be selected with BUILD_PROTECTED, because the legacy format is only a default and not a select, but the result did not link and then did not boot. Simple boot has no second-stage bootloader. __start() maps the flash itself, so everything it reaches must already be in RAM. kernel-space.ld pinned none of it, and it did not place esp32_start at all, so the entry point went to the flash the code was about to map. The chip loaded the RAM segments, jumped to 0x400d0ba4 and took an IllegalInstruction on the first instruction. So this pins the bootloader, flash, ROM, clock and log objects that bootloader_init() and map_rom_segments() reach, along with esp32_start itself, and defines the six _image_* symbols that __start() needs. All of it is behind CONFIG_ESPRESSIF_SIMPLE_BOOT, so a legacy build gets the same IRAM it had before. kernel-space.ld also had no `#include <nuttx/config.h>'. It held no conditionals until now, so nothing showed the omission: the new blocks compiled away silently and the link failed as if the file had not been changed. The default is unchanged. A protected build still selects the legacy format unless the user clears CONFIG_ESP32_APP_FORMAT_LEGACY. Verified on an ESP32-DevKitC V4, ESP32-D0WD-V3 revision 3.1, with esp32-devkitc:knsh and the legacy format turned off. The kernel flashes at 0x1000 and the user image at 0x90000, with no bootloader and no partition table. It maps seven segments, reaches NSH, and runs ostest to the same point as the legacy build. Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
2026-08-11 11:13:02 +02:00
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
/* Simple boot has no second-stage bootloader to map the flash, so __start()
* does it. map_rom_segments() reads the segment table out of the image in
* flash, but the entry point still needs these to be defined.
*/
_image_irom_vma = ADDR(.flash.text);
_image_irom_lma = LOADADDR(.flash.text);
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) -
_image_irom_lma;
_image_drom_vma = ADDR(.flash.rodata);
_image_drom_lma = LOADADDR(.flash.rodata);
_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) -
_image_drom_lma;
#endif
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
.rtc.text :
{
. = ALIGN(4);
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
_rtc_data_start = ABSOLUTE(.);
*(.rtc.literal .rtc.text)
} >rtc_iram_seg AT>ROM
.rtc.data :
{
*(.rtc.data)
*(.rtc.data.*)
*(.rtc.rodata)
*(.rtc.rodata.*)
/* Whatever is left from the RTC memory is used as a special heap. */
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
} >rtc_slow_seg AT>ROM
.rtc.force_slow :
{
. = ALIGN(4);
_rtc_force_slow_start = ABSOLUTE(.);
*(.rtc.force_slow .rtc.force_slow.*)
. = ALIGN(4);
_rtc_force_slow_end = ABSOLUTE(.);
} >rtc_slow_seg AT>ROM
/* This section holds RTC FAST data that should have fixed addresses.
* The data are not initialized at power-up and are retained during deep
* sleep.
*/
.rtc_fast_reserved (NOLOAD):
{
. = ALIGN(4);
_rtc_fast_reserved_start = ABSOLUTE(.);
/* New data can only be added here to ensure existing data are not moved.
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
* Because data have adhered to the end of the segment and code is relied
* on it.
* >> put new data here <<
*/
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
xtensa/espressif: Update common-source integration for Xtensa devices This commit updates the common-source integration for Xtensa-based Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger common-source update split by architecture for better maintainability. Major components updated: - IRQ allocator refactoring with intr_alloc integration - Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.) - Espressif components upgrade to release/master.b-test - Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.) - Wireless adapters (Wi-Fi and BLE) - esp_timer migration to the common-source path for Xtensa devices - Common-source power management implementation (auto-sleep and wakeup paths) - Board defconfigs for all Xtensa Espressif boards - SMP support improvements for ESP32-S3 - Critical section handling improvements Key architectural changes: - IRQ Allocator: The new interrupt allocator enables multiple mapping options from interrupt sources to CPU interrupts, providing flexibility required by modern peripherals. Although this introduces breaking changes to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE Kconfig option is explicitly checked during startup to ensure proper configuration. This validation prevents runtime issues from configuration mismatches. - Xtensa-specific interrupt handling via esp_xtensa_intr.c providing NuttX-native implementations of xt_ints_on/off and interrupt handlers, avoiding conflicts with NuttX's core Xtensa macros. - Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific RTC/RT-timer code to common-source Espressif integration, including esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates. - Power management consolidation: Xtensa PM follows the common-source implementation, including common-source auto-sleep behavior, UART/Wi-Fi wakeup coordination, and tickless-safe sleep flow compatibility. Note: This is a large commit to maintain bisectability. Breaking the changes into smaller commits would result in non-building intermediate states across the common-source infrastructure update. Tested configurations: - All defconfigs were tested, including `ostest`. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2026-02-27 15:06:57 -03:00
_rtc_fast_reserved_end = ABSOLUTE(.);
} > rtc_fast_reserved_seg
_rtc_fast_reserved_length = _rtc_fast_reserved_end - _rtc_fast_reserved_start;
ASSERT((_rtc_fast_reserved_length <= LENGTH(rtc_fast_reserved_seg)),
"RTC FAST reserved segment data does not fit.")
/* This section holds RTC SLOW data that should have fixed addresses.
* The data are not initialized at power-up and are retained during deep
* sleep.
*/
.rtc_slow_reserved (NOLOAD):
{
. = ALIGN(4);
_rtc_slow_reserved_start = ABSOLUTE(.);
/* New data can only be added here to ensure existing data are not moved.
* Because data have adhered to the end of the segment and code is relied
* on it.
* >> put new data here <<
*/
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
_rtc_slow_reserved_end = ABSOLUTE(.);
} > rtc_slow_reserved_seg
_rtc_slow_reserved_length = _rtc_slow_reserved_end - _rtc_slow_reserved_start;
_rtc_reserved_length = _rtc_slow_reserved_length;
/* Get size of rtc slow data */
_rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
}