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Enhance Makefile to avoid "Argument list too long"

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define a macro for split long variable and redefine variable in batch.
see details in `apps/Make.defs` `SPLITVARIABLE`.
replace the variable reference that caused the error.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
This commit is contained in:
xuxin19 2023-07-24 21:50:54 +08:00 • committed by archer
parent 6bea926ef2
commit 8e71885ee5
4 changed files with 71 additions and 41 deletions
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9
Application.mk
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@ -266,9 +266,12 @@ register::
endif
.depend: Makefile $(wildcard $(foreach SRC, $(SRCS), $(addsuffix /$(SRC), $(subst :, ,$(VPATH))))) $(DEPCONFIG)
$(Q) $(MKDEP) $(DEPPATH) --obj-suffix .c$(SUFFIX)$(OBJEXT) "$(CC)" -- $(CFLAGS) -- $(filter %.c,$^) >Make.dep
$(Q) $(MKDEP) $(DEPPATH) --obj-suffix .S$(SUFFIX)$(OBJEXT) "$(CC)" -- $(CFLAGS) -- $(filter %.S,$^) >>Make.dep
$(Q) $(MKDEP) $(DEPPATH) --obj-suffix $(CXXEXT)$(SUFFIX)$(OBJEXT) "$(CXX)" -- $(CXXFLAGS) -- $(filter %$(CXXEXT),$^) >>Make.dep
$(call SPLITVARIABLE,ALL_DEP_OBJS,$^,100)
$(foreach BATCH, $(ALL_DEP_OBJS_TOTAL), \
$(shell $(MKDEP) $(DEPPATH) --obj-suffix .c$(SUFFIX)$(OBJEXT) "$(CC)" -- $(CFLAGS) -- $(filter %.c,$(ALL_DEP_OBJS_$(BATCH))) >Make.dep) \
$(shell $(MKDEP) $(DEPPATH) --obj-suffix .S$(SUFFIX)$(OBJEXT) "$(CC)" -- $(CFLAGS) -- $(filter %.S,$(ALL_DEP_OBJS_$(BATCH))) >>Make.dep) \
$(shell $(MKDEP) $(DEPPATH) --obj-suffix $(CXXEXT)$(SUFFIX)$(OBJEXT) "$(CXX)" -- $(CXXFLAGS) -- $(filter %$(CXXEXT),$(ALL_DEP_OBJS_$(BATCH))) >>Make.dep) \
)
$(Q) touch $@
depend:: .depend